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DDR2 CLK vs DSQ vs ADR length matching

I am tracing my first DDR2 with Cyclone V PCB and I can't find exact information about CLK vs DSQ vs ADR length matching. External Memory Interface Handbook Volume 2: Design Guidelines from Intel says ...
kornev.online's user avatar
0 votes
0 answers
77 views

DDR2 SDRAM with the Lattice ECP5

I have a FPGA design that requires some memory. I'd really like to use DDR2 because of cost and speed reasons. I'd be running it at its lowest allowed frequency of 125MHz. Now the ECP5 has some IP ...
dinocroc123's user avatar
0 votes
1 answer
890 views

DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?

While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock. The characteristic of DDR is that it transfers 2 sets of data every cycle. Therefore, for older versions of ...
ALPHA's user avatar
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2 votes
1 answer
426 views

Why is the DDR termination voltage half the supply voltage? [closed]

Why is the DDR termination voltage (VTT) one-half the VDD voltage?
Confused's user avatar
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3 votes
1 answer
827 views

Why is On Die Termination (ODT) only available for Data Lines (DQ, DQS) but not for Address Lines in in DDR2/DDR3 memory?

I am trying to understand the need for termination resistors in DDR2/DDR3 designs and I have seen some Max 10 dev kit boards that don't terminate the address lines with 50 Ω terminating resistors. ...
nmr's user avatar
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0 votes
0 answers
57 views

How do I find out what pins of an Intel FPGA can be used to connect to different pin groups in EMIF?

If I want to connect my Intel FPGA using EMIF to a high speed DDR Memory e.g Cyclone IV E to DDR3 memory or Max 10 to DDR2 memory, how do I find out what pins can be used for the data, strobe, clock, ...
quantum231's user avatar
0 votes
1 answer
289 views

Are reference resistors required for VRP and VRN when implementing an DDR2 memory controller in an Artix-7 device?

The generated pinout does not list any VRP or VRN pins, or anything similar. I have specified internal impedance for the DDR2 IF pins with IO standard SSTL18_II. On previous and other FPGAs, it is ...
EquipDev's user avatar
  • 579
-2 votes
1 answer
352 views

Additive latency for DRAM READ and WRITE commands [closed]

In TN-47-10 – DDR2 Posted CAS# Additive Latency Technical Note , what does it exactly mean by Additive latency (AL = 1) is only used for READ commands and will not affect WRITE command timing ?
kevin998x's user avatar
  • 413
4 votes
1 answer
381 views

Why do DDR RAMs have both xDQ and xDM signals?

DDR2 RAMs have these control signals RAS, CAS - address strobes UDQ, LDQ - byte strobes WE - write enable UDM, LDM - write mask Why do we need UDM and LDM? Can't you write a byte by asserting WE and ...
Mark Sullivan's user avatar
3 votes
3 answers
606 views

what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?

In this day and age we can just use the memory IP provided to us by the FPGA vendor be it a soft IP or hard IP. This makes it almost trivial to communicate with high speed memory devices like DDR2 and ...
gyuunyuu's user avatar
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0 votes
1 answer
366 views

Interfacing a RAM chip from a commercial computer with an ARM cpu such as Stm32

I need to interface some sort of RAM with an ARM processor for my embedded project. Around 128 MB to be exact. I found a computer RAM which claims to be DDR and 1 GB. As I only need 128 MB of RAM for ...
James B. Reese's user avatar
2 votes
0 answers
407 views

DDR2 and DDR3 ODT and ZQ calibration

Can anyone please explain what is the difference in ODT and ZQ technique used in DDR2 and DDR3?? Which method is very useful for DDR2 termination? whether ODT or External parallel termination?? ...
M.Arun kumar's user avatar
1 vote
2 answers
153 views

calibration working in DDR2/3 memory devices [closed]

Does anyone know exact working and what will be blocks present inside the calibration module of DDR2/3 memory devices? Any information related to calibration process of DDR2/3 SDRAM's is appreciated.....
Balakrishna's user avatar
7 votes
3 answers
714 views

DDR(2-4) Training and Length Matching

Today I learned about the concept of memory training for DDR2, 3, and 4 (I'm not sure if DDR1 has it). The purpose of memory training is to correct for skew in data, address, and command bits being ...
cr1901's user avatar
  • 504
2 votes
1 answer
689 views

What is the more frequent error in DDR Memory?

this is about DDR memory data corruption and not about STUCK address or data lines. If we have a good DDR with no memory stuck issues and we perform lots of writes and reads which type of error is ...
arun's user avatar
  • 43
2 votes
1 answer
107 views

Replacing a DDR2 memory with another that is faster

Are there any known timing issues with directly replacing on board one DDR2 SDRAM with another package and pin compatible DDR2 that is slightly faster?
Rustin's user avatar
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3 votes
3 answers
12k views

DDRx Memory: Memory Clock vs I/O Bus Clock?

When referring to DDR/DDR2/DDR3/DDR4 memories, I am not able to understand the difference between memory clock and I/O clock. As per: https://en.wikipedia.org/wiki/Double_data_rate DDR-200 - Memory ...
LoveEnigma's user avatar
0 votes
1 answer
320 views

DDR2 ODT pulled low

I was looking at a DDR2 design that had it's ODT pin pulled low, presumably this was done because the CPU doesn't have and ODT pin. Reading the datasheet though I don't see a clear explanation of ...
confused's user avatar
  • 1,806
5 votes
2 answers
994 views

waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?

I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm ...
lamont cranston's user avatar
2 votes
1 answer
3k views

DDR2 decoupling/bypassing - 100nF or 10nF?

I am slightly confused in deciding decoupling/bypass capacitor for DDR2 power supply pins. Some recommendations mention using 100nF and some mention using 10nF. I know that lower capacitance is more ...
LoveEnigma's user avatar
1 vote
1 answer
518 views

DDR2 data rate and data bus confusion

I've been reading about DDR2 memory for the past few days and have got confused with some of the terms involved. I am mainly confused with discrete memory (single DDR2 memory IC) rather than DIMM ...
LoveEnigma's user avatar
5 votes
2 answers
335 views

First DDR2 Layout - How much of a data lane must have the same reference?

Doing my first DDR2 layout and I'm hitting some conflicting requirements. I have dogbones to an internal ground-referenced layer, and then short top layer traces at the other end going from the ...
Rudolf's user avatar
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1 vote
2 answers
2k views

Series Termination DDR

I was Going through some application notes for the placement of Series termination of DDR and found it should be placed near to the processor. But if I am not wrong termination resistor are placed to ...
Sanjeev Kumar's user avatar
9 votes
2 answers
6k views

Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?

If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz. DDR For example,DDR-400 Efficient frequency data bus is 400 MHz True clock rate (IO buffer ...
Sanjeev Kumar's user avatar
3 votes
1 answer
741 views

Can I use full-size 64/72 bit DDR2/DDR3 memory module with CycloneV hardware controller of 24 + 24 bits?

I thinking of using Cyclone V FPGA and its hardware memory controller: There is "Cyclone V FPGA Multiport Memory Controller" document from Altera: http://www.altera.com/devices/fpga/cyclone-v-fpgas/...
osgx's user avatar
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2 votes
1 answer
127 views

DDR2 memory addressing error

I have a Freescale MPC8640-based board with 4 Micron DDR2 chips of 128Mx16 density (total of 1GB) attached to it. The memory has been mapped to address range from 0x0000_0000 to 0x3FFF_FFFF. While ...
Avin's user avatar
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2 votes
1 answer
2k views

What is DDR software leveling?

What is DDR software leveling ? How it is different from DDR2 and DDR3 ? Why it is required and important ? Is there a hardware leveling ? I have found some explanation here about DDR3 and a ...
Abdurahman's user avatar
2 votes
2 answers
2k views

How DDR2 SDRAM works?

I have the Xilinx Spartan-3AN Starter Kit and I need to use the on board DDR2 SDRAM (MT47H32M16CC-XX). Until now I only used Static RAM and this type of memory is new for me. Can someone explain me ...
Oceanic815's user avatar
  • 1,189
9 votes
1 answer
2k views

Is there a PCB-layout related reasoning behind DDR memory package and footprint?

BGA DDR packages have a unique footprint. There are two columns of pads on both sides of the device, and an empty column in between. Is there a reasoning behind the placement of these pads (in terms ...
SomethingBetter's user avatar
2 votes
3 answers
756 views

Single Board Computer (SBC) suggestion for interfacing with DMA

I am taking over a project where a Spartan 6 FPGA provides the interface between an ADC and a DDR2 memory chip. The FPGA takes 16-bit data out of the ADC and stores it into the RAM at a rate of 28MHz. ...
Peter's user avatar
  • 350
4 votes
1 answer
630 views

Crosstalk on PCB

I am currently working on a PCB with DDR2 on it. We are bringing out the DDR2 CLK, DQS signals using pogo pins to make some timing measurements. The length of the pins are about 5 cm. The problem is ...
Sdatt's user avatar
  • 41
0 votes
2 answers
258 views

Localized RAM readback errors: chip or timing issue?

I'm currently testing the hardware of a prototype board using DDR2 memory, and I get RAM readback errors when performing a memory test. The errors happen in this fashion: ...
cJ Zougloub's user avatar
4 votes
1 answer
488 views

Will DDR2 memory work with DM pins tied to LOW, if no data masking is required?

I have a board with the LDM and UDM pins swapped. If they are tied to low, will the memory still 'work', given that data is always written to mod 4 addresses and always using all 4 bytes? Memory is ...
user3812's user avatar
  • 410
2 votes
2 answers
1k views

DDR2-SDRAM Termination methods: passive vs. active

for a project I'm designing I am currently using a simple parallel Resistor Termination on the DDR2-Traces. But I'm wondering, what is the advantage of using a voltage regulator with serial-...
Nico Erfurth's user avatar
2 votes
1 answer
1k views

Do I need to control trace impedance for DDR2 memory?

I am going to try to interface low-speed 8bit DDR2 chip to FPGA, and I've got some questions crucial to make it work :-) 3) What is up with controlled impedance of PCB traces? Why it's important? ...
BarsMonster's user avatar
  • 3,219
4 votes
1 answer
577 views

Do DDR2 chips and controllers have on-die termination?

I am going to try to interface a low-speed 8-bit DDR2 chip with an FPGA, and I've got some questions crucial to make it work: Is that correct that there is on-die termination on both DDR2 memory and ...
BarsMonster's user avatar
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