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Questions tagged [ddr3]

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4
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2answers
405 views

PCB - Ram connectors problem

Currently following an schematic for NanoPI NEO4 to make my own RK3399 board. On their schematic for the K4B4G1646D-BCK0,I noticed for pins DQ1-DQ15 on both chips connect to a randomised list of ...
1
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1answer
29 views

What do terms half-rate and quarter-rate mean for DRAM memory controllers?

DDR3 Memory controller are often presented as being half rate or quarter rate, but what does this mean? e.g if I have a DDR3 SDRAM that is x16, what does the half or quarter rate imply in that case ...
1
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1answer
87 views

Unused bits on a DDR3 chip

I have 2 DDR3 x16 chips (MT41K256M16xx) interfaced with an FPGA (M2S150TS-1FCS536). I plan on using point-to-point data & fly-by address/command topologies. I'm using ECC with a 16 bit bus, so 18 ...
0
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1answer
43 views

DDRx timing analysis

I have a question regarding timing analysis for DDR3 and DDR4 signals. How do we do timing analysis to see if all setup and hold requirements are fulfilled correctly, considering they have write ...
0
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0answers
25 views

Confusion in walking 1s test on data and address lines of DDR3 to figure out address/data line shorted/open connection

We have beaglebone black based custom board with 256MB DDR3 RAM and 4GB eMMC. We are having two different kinds of DDR3 for our boards. MT41K128M16JT - 16 Meg x 16 x 8 banks : Size 256MB MT41K256M16 –...
2
votes
0answers
128 views

DDR2 and DDR3 ODT and ZQ calibration

Can anyone please explain what is the difference in ODT and ZQ technique used in DDR2 and DDR3?? Which method is very useful for DDR2 termination? whether ODT or External parallel termination?? ...
1
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1answer
79 views

DDR3 trace length: need a confirmation

I am reading JEDEC DDR3 specification, and so many other documents on DDR3 guidelines. Before I move to pcb prototyping, I just need a confirmation. I connected all my lines, respected the grouping, ...
0
votes
1answer
270 views

DDR3 SE signal, is 50Ohm impedance necessary?

I want to design a 6 layer PCB for an Allwinner H3 and DDR3, but the PCB workshop just have the stack-up shown in the image. With this stack-up, The calculation for striplines impedance is difficult. ...
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0answers
86 views

How far away can DDR3 memory be placed from the SoC?

I thought of an idea where i have a pcb with a soc on it, and a seperate one with the DDR3 memory that can snap into each other. This way i can replace or debug specefic parts of the system and have e....
1
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0answers
130 views

What is write/read leveling(each DQ relative to DQS)

DDR3 supports write and read leveling on DQ. I know we need them because of Fly-by topology. But I want to know more detailed reason why we need them for DDR3.
2
votes
1answer
221 views

Understanding GDDR5 clamshell mode

Let suppose a 256 bit memory controller is installed on a PCB with GDDR5 memory modules. In normal mode you can split the lines into 8 group of 32 bit and drive 8 modules x 1Gbit (128 MB) = 1 GB of ...
3
votes
1answer
94 views

DDR(2-4) Training and Length Matching

Today I learned about the concept of memory training for DDR2, 3, and 4 (I'm not sure if DDR1 has it). The purpose of memory training is to correct for skew in data, address, and command bits being ...
1
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1answer
298 views

Theoretical calculation of DDR3L transfer speed

I am not sure if this questions belongs to this stack exchange site but I didn't find other better one. In case it doesn't, let me know and I will move it to some other place. I am working with a ...
2
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0answers
126 views

1GB single DDR3 Chip for ZYNQ(XC7Z020-2CLG400I), is it possible?

I'm putting together a PCB and I want to use single 8Gb (512*16) DDR3 chip (MT41K512M16HA) but the DDR3 address bank is less than the DDR3 chip. Is it possible to use single 8Gb chip for this IC?
0
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0answers
75 views

Discrete DDR3 Layout Check

I have 8 chips of 512 Mb DDR3 interfaced with the processor with point to point Data & fly by Address/command topology. I need to remove 1 DDR3 & keep it unmount. The rest 7 DDRs should work ...
1
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1answer
657 views

Why address mirroring in some SDRAMs?

I have seen references to that feature here and here (pg 20) I can't quite get why it is useful. Since the memory controller selects the rank, wouldn't be the same if the address on the rank would ...
0
votes
1answer
276 views

How to estimate the peak current of DDR3L DRAM and design a power supply

I am designing a board which will have 5x DRAM DDR3L Micron MT41K512M8DA-107XIT:P (\$V_{DDQ}=1.35V\$). The question is, how to estimate the peak current consumption of the DRAM and then design a power ...
0
votes
1answer
53 views

Same DDR3 total capacity, different chip capacity configuration, speed different?

Let say I want to have 1GB DDR3 in my board. I could use: 2 pieces MT41K256M16 – 32 Meg x 16 x 8 banks 1 piece MT41K512M16 – 64 Meg x 16 x 8 banks Will configuration #1 be faster since 32 data buses ...
2
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2answers
319 views

DDR3 Series Termination Length Matching

I am implementing a DDR3 interface on a PCB and I have a question regarding the termination of address/control/command/clk traces. I have series terminations for all the required traces mentioned ...
1
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1answer
70 views

Minimum time to write all memory of DDR3 (micron)

I have a 1GB DDR3 memory from micron. Do you know how to calculate the minimum time to write the entire memory consecutively ? My problem is to know how to include all timing in the bandwidth ...
0
votes
1answer
370 views

How to design DDR3 PCB without any termination resistor in processor and RAM connection

As I'm going to design my first high-speed PCB, I'm confused with some mismatches between what i see in high-speed PCB design tutorials and what i see in real world designs. in the PCB handbook named "...
1
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1answer
273 views

DDR3 length-matching between signal groups

I currently dig into the design incorporating an application processor and one piece of DDR3 memory. I already found out how the individual signal groups are formed and about the guidelines concerning ...
1
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1answer
263 views

Using a high frequency LPDDR3 RAM with a lower RAM frequency supported Processor

I'm designing a board with Allwinner A64 processor and i'm confused in choosing the proper RAM. the SDRAM controller characteristics of the processor is listed as follows: Compatible with JEDEC ...
3
votes
1answer
69 views

Electrical principle of row hammer glitch

There is a fairly new and exploitable bug happening in some DDR3 DRAMs called the "row hammer" in which it's possible to bit flip memory cells. I understand how the exploit works, but not the ...
0
votes
1answer
176 views

ODT Termination and driver impedance Question

I am analyzing signal integrity between an applications processor and DDR3 modules.I was looking at IBIS models for the device I am using. I was confused because certain IBIS models had "driver ...
0
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0answers
105 views

Is the DDR3 specification required to implement DDR3 modules

The DDR3 specification maintained by JEDEC costs approximately 6k USD annually. Is it absolutely required? If this is the wrong place to ask this I apologize.
2
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3answers
963 views

DDR3 routing: swapping data wires

Is it possible to swap wires in data bus between CPU and DDR3 x16 memory for routing optimization? So, for data lines depends on the correct order? For example connect DQ0 on CPU to DQ1 on memory ...
4
votes
2answers
2k views

How many layers at least for proper DDR3 fanout and routing?

I'm working on a project and have been banging my head against the wall for the past couple of weeks with the DDR3 fanout and wiring. I'm trying to keep the cost to the minimum, so I'm using the most ...
0
votes
1answer
177 views

What makes PC SDRAM so much more expensive than the same capacity in a chip?

I'm picking a SDRAM IC for a custom embedded board and was surprised by the low prices. Was expecting orders of magnitude similar to PC ram of the same capacity. For example H5TC8G63AMR-PBA chip ...
0
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0answers
282 views

DDR3 trace impedance - short traces but high impedance

I'm putting together a small PCB based around a Xilinx Zynq (the CLG225 one), because the DDR3 pads are all in a big block on one side of the device and because I've been designing for a 4 layer PCB, ...
0
votes
1answer
97 views

Pin name confusion with Allwinner A20 and DDR3L/2GB

I've been trying for the past hour to find the correct definition and the proper way to use the, DML, DQSL, DQUO, DMU, DQSU, DQSU, the part has two DQSU pins. There are no corresponding pins on ...
0
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1answer
313 views

Are DDR3 SDRAM's DQL and DQU pins different?

Obviously they are, but I am using the Allwinner A20 and alliance memories AS4C128M16D3B-12BCN 2GB, it has DQU1,2,3,4 etc pins, but the Allwinner A20 does not, it only has the DQL, no DQU. This ...
2
votes
1answer
267 views

What is the more frequent error in DDR Memory?

this is about DDR memory data corruption and not about STUCK address or data lines. If we have a good DDR with no memory stuck issues and we perform lots of writes and reads which type of error is ...
1
vote
1answer
637 views

Is it good practice to length match all traces of DDR3, or are only data traces important? [duplicate]

I am researching single board computers with the hope of designing on at the end of this, I am at the stage of DDR3, but can't find any good info on routing ddr3, regarding what traces need to be ...
3
votes
1answer
165 views

can high speed memory interfaces like GDDR5 or XDR ever become mainstream?

Given the limited memory on GPUs, I'm wondering why there are no socketed GDDR5 memory modules so that you can install more RAM. The main challenge seems to be maintaining signal integrity since ...
4
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1answer
1k views

Tolerances for DDR3 trace matching?

What would be an acceptable tolerance for length matching trace, for DDR3 SDRAM?
1
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1answer
5k views

DDRx Memory: Memory Clock vs I/O Bus Clock?

When referring to DDR/DDR2/DDR3/DDR4 memories, I am not able to understand the difference between memory clock and I/O clock. As per: https://en.wikipedia.org/wiki/Double_data_rate DDR-200 - Memory ...
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0answers
151 views

GDDR Power Calculation

I'm wondering if there is any publicly available documents or research papers that cover GDDR power estimation? Micron provides very nice documentation and calculators for DDR up to DDR4, however I ...
3
votes
2answers
1k views

Reset the configuration of FPGA without reprogramming

I am doing an experiment on Xilinx VC709 board. The experiment involves removing and plugging in the DDR3 RAM while the FPGA is running. But every time I plug back the RAM I have to reprogram the FPGA....
4
votes
2answers
3k views

Termination resistors with DDR3, are they needed?

I'm using a DSP processor with one chip Micron DDR3 MT41J128M16JT in a project. I read a lot about the termination resistors, but I'm still confused about if I really need those, I didn't start the ...
3
votes
1answer
320 views

What references cover DDR3 layout considerations?

I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout. I know that trace length matching, via style and back-drilling, and signal grouping all matter. I know that ...
0
votes
3answers
314 views

DDR3 Address Bus Quations

I'm new to EMIF (external memory interfaces) and I ran into kind of a dumb question about DDR3- not super important but mostly me just wondering if there's an answer I'm not thinking of. Basically I'm ...
5
votes
2answers
744 views

waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?

I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm ...
1
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1answer
1k views

What type of memory allows for most parallel read/write operations per clock cycle in an FPGA?

If you imagine basic motion detection where you have two frames stored in memory: a previous 640x480 frame and the current 640x480 frame, what type of memory (SRAM, DRAM, SDRAM, DDR SDRAM, etc) would ...
1
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2answers
822 views

Series Termination DDR

I was Going through some application notes for the placement of Series termination of DDR and found it should be placed near to the processor. But if I am not wrong termination resistor are placed to ...
2
votes
1answer
3k views

How is the DDR3 SDRAM addressing done?

In order to work on programming a DDR3 SDRAM, I was going through the JEDEC standard DDR3 SDRAM specification (link to pdf, pg 30). I got a bit confused about the DDR3 addressing, a snapshot of which ...
1
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0answers
273 views

Creating Serial Pressence Detect data from discrete DDR RAM datasheet

I have a board that has soldered discrete DDR RAM chips. The datasheet for the DDR RAM chips is available to me. The DDR memory controller is programmed manually using pre-calculated values. I have ...
3
votes
2answers
3k views

Why All DDR's (DDR, DDR2, DDR3) internal clock sets to 200MHz

If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz. DDR For example,DDR-400 Efficient frequency data bus is 400 MHz True clock rate (IO buffer ...
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1answer
165 views

Independence of the two channel architecture of LPDDR4

I'm working on a project involving LPDDR4. I've read the pertinent sections of the recently released JEDEC LPDDR4 spec. I have several questions regarding the independence of the two channel ...
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5answers
1k views

High speed memory interface between 2 FPGAs (Virtex 6)

I have a board with 2 Virtex 6 FPGAs, which are connected to each other through 64 parallel IO lines that can operate up to 400 MHz. One FPGA, let's call it B, also has 2 GB of DDR3 memory connected ...