Questions tagged [ddr3]

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What references cover DDR3 layout considerations?

I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout. I know that trace length matching, via style and back-drilling, and signal grouping all matter. I know that ...
Bryce's user avatar
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9 votes
1 answer
683 views

DDR3 Data Errors

I am looking for post layout solutions for DDR3 data errors. I have a PCB with a FPGA and a 2 banks (2 rank) DDR3 ram setup. Data errors occur either when the RAM (FPGA is not confirmed, but could be)...
Eggi's user avatar
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9 votes
1 answer
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Is there a PCB-layout related reasoning behind DDR memory package and footprint?

BGA DDR packages have a unique footprint. There are two columns of pads on both sides of the device, and an empty column in between. Is there a reasoning behind the placement of these pads (in terms ...
SomethingBetter's user avatar
8 votes
1 answer
404 views

Compensating for unbalanced via count in DDR3 routing

I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). ...
Steinar's user avatar
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6 votes
3 answers
632 views

DDR(2-4) Training and Length Matching

Today I learned about the concept of memory training for DDR2, 3, and 4 (I'm not sure if DDR1 has it). The purpose of memory training is to correct for skew in data, address, and command bits being ...
cr1901's user avatar
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4 votes
3 answers
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DDR3 routing: swapping data wires

Is it possible to swap wires in data bus between CPU and DDR3 x16 memory for routing optimization? So, for data lines depends on the correct order? For example connect DQ0 on CPU to DQ1 on memory ...
vlk's user avatar
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3 votes
3 answers
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what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?

In this day and age we can just use the memory IP provided to us by the FPGA vendor be it a soft IP or hard IP. This makes it almost trivial to communicate with high speed memory devices like DDR2 and ...
gyuunyuu's user avatar
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1 vote
1 answer
89 views

Is there any chance to configure DDR3L SDRAM on Digilent Arty A7 FPGA development board to Dual Channel memory?

There are 256MB DDR3L SDRAM installed on Digilent Arty A7 FPGA development board. Dual Channel memory is popular nowadays in a PC. So I was wondering if there is any chance to configure the DDR3L ...
zzzhhh's user avatar
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