Questions tagged [ddr3]
The ddr3 tag has no usage guidance.
124
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Why is length matching performed with the clock trace length as the target length?
Length matching is performed mainly to avoid the skew generated among the parallel data lines/data bus width.
All the high speed PCB design guideline suggest performing length matching with the clock ...
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Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?
If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz.
DDR
For example,DDR-400
Efficient frequency data bus is 400 MHz
True clock rate (IO buffer ...
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1
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Is there a PCB-layout related reasoning behind DDR memory package and footprint?
BGA DDR packages have a unique footprint. There are two columns of pads on both sides of the device, and an empty column in between.
Is there a reasoning behind the placement of these pads (in terms ...
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DDR3 Data Errors
I am looking for post layout solutions for DDR3 data errors.
I have a PCB with a FPGA and a 2 banks (2 rank) DDR3 ram setup.
Data errors occur either when the RAM (FPGA is not confirmed, but could be)...
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How many layers at least for proper DDR3 fanout and routing?
I'm working on a project and have been banging my head against the wall for the past couple of weeks with the DDR3 fanout and wiring. I'm trying to keep the cost to the minimum, so I'm using the most ...
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Compensating for unbalanced via count in DDR3 routing
I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). ...
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3
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DDR(2-4) Training and Length Matching
Today I learned about the concept of memory training for DDR2, 3, and 4 (I'm not sure if DDR1 has it). The purpose of memory training is to correct for skew in data, address, and command bits being ...
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LPDDR4 layout, should we avoid having signals in same byte group on different layers?
Is it a bad idea to route intra byte DQx on different layers?
I am trying to interface AM6442 to LPDDR4 16bit. I have followed every constraint in TI's DDR layout guidelines to the letter, ...
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Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?
Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-...
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DDR3 pcb design routing
I am trying to layout DDR3 128MB chip and a Spartan-6 FPGA. DDR signal pins located on specific memory controller pins and could not be swapped.
I've never done DDR routing and went with SP605 Xilinx ...
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Termination resistors with DDR3, are they needed?
I'm using a DSP processor with one chip Micron DDR3 MT41J128M16JT in a project.
I read a lot about the termination resistors, but I'm still confused about if I really need those, I didn't start the ...
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waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?
I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm ...
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No terminations on point to point DDR3?
Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ...
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DDR3 routing: swapping data wires
Is it possible to swap wires in data bus between CPU and DDR3 x16 memory for routing optimization?
So, for data lines depends on the correct order?
For example connect DQ0 on CPU to DQ1 on memory ...
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Using multiple DDR3 controllers on FPGA
We are designing an image processing pipeline on an FPGA which will need the use of memory interfaces at various pipeline stages. Because of the size of the memory required we decided to go with a ...
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PCB - Ram connectors problem
Currently following an schematic for NanoPI NEO4 to make my own RK3399 board.
On their schematic for the K4B4G1646D-BCK0,I noticed for pins DQ1-DQ15 on both chips connect to a randomised list of ...
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Tolerances for DDR3 trace matching?
What would be an acceptable tolerance for length matching trace, for DDR3 SDRAM?
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Reset the configuration of FPGA without reprogramming
I am doing an experiment on Xilinx VC709 board. The experiment involves removing and plugging in the DDR3 RAM while the FPGA is running. But every time I plug back the RAM I have to reprogram the FPGA....
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what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?
In this day and age we can just use the memory IP provided to us by the FPGA vendor be it a soft IP or hard IP. This makes it almost trivial to communicate with high speed memory devices like DDR2 and ...
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DDRx Memory: Memory Clock vs I/O Bus Clock?
When referring to DDR/DDR2/DDR3/DDR4 memories, I am not able to understand the difference between memory clock and I/O clock.
As per: https://en.wikipedia.org/wiki/Double_data_rate
DDR-200 - Memory ...
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Why is the burst order of DDR3 DRAM not sequential?
Based on the JEDEC DDR3 documentation as shown below, when we are reading with burst length of 8 and starting column address of 010 (0x2), the burst order will be <...
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Is it good practice to length match all traces of DDR3, or are only data traces important? [duplicate]
I am researching single board computers with the hope of designing on at the end of this, I am at the stage of DDR3, but can't find any good info on routing ddr3, regarding what traces need to be ...
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Why is On Die Termination (ODT) only available for Data Lines (DQ, DQS) but not for Address Lines in in DDR2/DDR3 memory?
I am trying to understand the need for termination resistors in DDR2/DDR3 designs and I have seen some Max 10 dev kit boards that don't terminate the address lines with 50 Ω terminating resistors.
...
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How is the DDR3 SDRAM addressing done?
In order to work on programming a DDR3 SDRAM, I was going through the JEDEC standard DDR3 SDRAM specification (link to pdf, pg 30).
I got a bit confused about the DDR3 addressing, a snapshot of which ...
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Sharing DDR3 memory between two sources
I have an FPGA and a powerful ARM processor both support DDR3. I am an experienced designer for smaller more embedded designs with less powerful CPUs but this is my first rodeo with a powerful ARM and ...
- 2,236
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Drive strength and impedance
I have a custom embedded board with an MPU (i.MX6ULL) interfaced to a DDR3L. After noticing occasional hangs and crashes, I started tinkering with the DDR Drive Strength settings and was surprised how ...
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DDR3 Series Termination Length Matching
I am implementing a DDR3 interface on a PCB and I have a question regarding the termination of address/control/command/clk traces.
I have series terminations for all the required traces mentioned ...
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can high speed memory interfaces like GDDR5 or XDR ever become mainstream?
Given the limited memory on GPUs, I'm wondering why there are no socketed GDDR5 memory modules so that you can install more RAM.
The main challenge seems to be maintaining signal integrity since ...
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What references cover DDR3 layout considerations?
I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout. I know that trace length matching, via style and back-drilling, and signal grouping all matter. I know that ...
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Can I use full-size 64/72 bit DDR2/DDR3 memory module with CycloneV hardware controller of 24 + 24 bits?
I thinking of using Cyclone V FPGA and its hardware memory controller:
There is "Cyclone V FPGA Multiport Memory Controller" document from Altera:
http://www.altera.com/devices/fpga/cyclone-v-fpgas/...
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696
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JLC2313 stackup with DDR3 fly-by
I’m building a simple SBC based on Allwinner A33 for my undergraduate final project, includes two x8 DDR3 chips. I’m going with 6 layers JLC2313 Stackup 1.2mm thickness (cost reasons). It’s my first ...
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DDR3 SODIMM slow clock specification
I am considering to design memory controller handling 1GB of the RAM. I did already design controller for Micron's 32MB SDRAM in the past using Cyclone III device.
The new design is for retro ...
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Is my meander a bad idea?
Autodesk Eagle's Meander:
My compact meander:
How bad of an idea is it to use "My compact meander" meander instead of the Eagles's version? The Autodesk Eagle's meander tool is very bad, ...
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How to design DDR3 PCB without any termination resistor in processor and RAM connection
As I'm going to design my first high-speed PCB, I'm confused with some mismatches between what i see in high-speed PCB design tutorials and what i see in real world designs. in the PCB handbook named "...
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What type of memory allows for most parallel read/write operations per clock cycle in an FPGA?
If you imagine basic motion detection where you have two frames stored in memory: a previous 640x480 frame and the current 640x480 frame, what type of memory (SRAM, DRAM, SDRAM, DDR SDRAM, etc) would ...
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Selecting different impedances then 50 ohm in DDR3
I've worked with DDR2 and DDR3 memories and usually stuck to 50 ohm impedance for traces. But i do see that SoCs and DDR2/3 memories seem to support other impedances such as 30, 60 and 150 ohms.
...
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What is DDR software leveling?
What is DDR software leveling ?
How it is different from DDR2 and DDR3 ?
Why it is required and important ?
Is there a hardware leveling ?
I have found some explanation here about DDR3 and a ...
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Why is the DDR termination voltage half the supply voltage? [closed]
Why is the DDR termination voltage (VTT) one-half the VDD voltage?
- 2,690
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310
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Length matching on DDR3 dataline in simulation for STM32MP1
I'm using HyperLynx to emulate my STM32MP157AAA3 small form factor system board with DDR3-1066 memory.
When I use DDRx batch simulation:
I confirmed that my ODT model is configured correctly. Use 48 ...
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Does fly-by order of bytes matter in DDR3+ design?
DDR3 introduces a Fly-by mode, which complicates memory controller, which now needs to account for different round-trip times amongst bytes, in exchange for a greater flexibility in PCB design.
I've ...
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DDR4 board bringup issue
I am struggling with a DDR4 related board bringup issue.
Can anyone out there recognise what the problem is by studying the attached memory dumps?
The memory dump is from Preboot loader PB31 area of ...
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1
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DDR3 trace length: need a confirmation
I am reading JEDEC DDR3 specification, and so many other documents on DDR3 guidelines.
Before I move to pcb prototyping, I just need a confirmation.
I connected all my lines, respected the grouping, ...
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Understanding GDDR5 clamshell mode
Let suppose a 256 bit memory controller is installed on a PCB with GDDR5 memory modules.
In normal mode you can split the lines into 8 group of 32 bit and drive 8 modules x 1Gbit (128 MB) = 1 GB of ...
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What is the more frequent error in DDR Memory?
this is about DDR memory data corruption and not about STUCK address or data lines. If we have a good DDR with no memory stuck issues and we perform lots of writes and reads which type of error is ...
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DDR3 Termination resistor value regarding
In a design, my senior put a 49.9ohm termination resistor to terminate the control, address, and control lines.Here I can't find the correct explation for this.
My question is,
1.How to choose the ...
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Xilinx FPGA and DDR3 Memory. Confusing Impedance combinations
Currently I'm planning on doing a PCB with DDR3 memory and an Artix7 FPGA. During my research a few questions accumulated.
When looking at the reference manual of the Arty7 board, I see that I have to ...
- 1,735
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Electrical principle of row hammer glitch
There is a fairly new and exploitable bug happening in some DDR3 DRAMs called the "row hammer" in which it's possible to bit flip memory cells. I understand how the exploit works, but not ...
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DDR3 DQS "preamble"
I'm building a small testbench for a DDR3 memory controller and would like to verify that my unterstanding of DQS and DQ sampling points is correct.
The line state before the transmission is undefined ...
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DDR2 and DDR3 ODT and ZQ calibration
Can anyone please explain what is the difference in ODT and ZQ technique used in DDR2 and DDR3??
Which method is very useful for DDR2 termination? whether ODT or External parallel termination??
...
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1GB single DDR3 Chip for ZYNQ(XC7Z020-2CLG400I), is it possible?
I'm putting together a PCB and I want to use single 8Gb (512*16) DDR3 chip (MT41K512M16HA) but the DDR3 address bank is less than the DDR3 chip.
Is it possible to use single 8Gb chip for this IC?
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