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How to handle unused 32-bit data, dqs and dbi on DDR4 SODIMM module

In a design, I have used a DDR4 SODIMM module, which has 64-bit data, thus 8 groups of data (DQ), DQS and DBI. However, I will only use the lower 32 bit on the module, thus have to handle the ...
EquipDev's user avatar
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What is the DDR4/5 Colum-to-Column access latency for within bank access

Since DDR4, the banks are divided into bank-groups, where Column-to-Column delay (CCD) for accessing in different bank-groups is lower (tCCD_s) than than of accessing bank-to-bank within a bank-group (...
Kraken's user avatar
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Difference between using a single x16 DDR4 memory device or two x8 DDR4 memory devices

I'm working on a design that has a 16 bit DDR4 memory controller and also has a reference schematic. The reference design has two separate x8 DDR4 memory devices connected to the controller DQ[0:7] ...
Rockker's user avatar
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DDR4 Routing Consideration on pcb (no DIMM)

I need to route DDR4x2(3200MHz) to my FPGA. my stackup is 12 Layers, TH Via only, and thickness of 2mm PCB. my question regard which layer to route the FPGA to DDR4, when the two component on the TOP(...
Knowledge's user avatar
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Modern DDR4 memory access latency system analysis

The memory access latency for the Intel Core i7-11800H (source: chipsandcheese, cpu latency for Intel Core i7-11800H), using DDR4-3200, reveals specific timings: 1 ns for L1, 3 ns for L2, and 13 ns ...
Prajwal Rathnakar Hegde's user avatar
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1 answer
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Why is there a tRRD in DDR3? There does not seem to be a resource conflict between different banks

In DDR3, bank activation is specific to the Bank, for different banks, they all have their own sense amp and do not seem to affect each other, so why would there be tRRD?
LurenAA's user avatar
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What's the purpose of the DDR4 1X, 2X and 4X refresh modes?

The DDR4 specification defines 1x, 2x and 4x refresh modes as follows: The default Refresh rate mode is fixed 1x mode where Refresh commands should be issued with the normal rate, i.e., tREFI1 = ...
geschema's user avatar
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1 answer
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How do I length match different signal classes for DDR3 or DDR4 routing on a PCB?

DDR3 and DDR4 memory routing can be confusing to for length matching because of the many tolerances and specs of all the different busses. How do I length match different signal classes for DDR3 or ...
Voltage Spike's user avatar
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What is mean by VREF Training in DDR4?

While going through DDR3 and DDR4, there is a term called vref. Where in DDR3 it is outside the DDR and for DDR4 it is inside the chip. Why we need training for it. What is the use of it.
Selva97's user avatar
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Memory density understanding

I am trying to understand DDR4 datasheet. All memory chips listed on page 3 have density equal to organization multiplication except 16Gb B-die and 32Gb A-die ones. Let's pick K4A8G165WC. Chip have ...
kab00m's user avatar
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Is there a breadboard for DDR4 card slots? [closed]

I've got a TE 2309413-1 card slot on my project board and I'm looking for a development board that I can use and plug into the slot. Does anyone know if such a thing exists? My Google-fu isn't turning ...
Jedi Engineer's user avatar
2 votes
3 answers
2k views

What are the recommended CK, DQ, DQS, ADDR impedances for LPDDR4?

I am using a micron part with LPDDR4, in many datasheets from micron there are no references to a specific impedance for CLK, DQ, DQS, ADDR. The datasheet mentions that the LVSTL is tuneable, but what ...
Voltage Spike's user avatar
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How much skew correction can typically be applied to DQS during DDR4 link training?

My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync. Is there ...
Polynomial's user avatar
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2 votes
1 answer
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DDR4 Routing Consideration

I'm designing a new PC based on Intel Tiger Lake UP3. In Intel Design Guide, I saw that there recommendation for DDR4 signals is to have two BO segments (BO1 and BO2). each BO has different impedance ...
Firas Abd El Gani's user avatar
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Can a pin to DDR4 be as thin as household tinfoil? (0.016 mm)

Edit: I think using the term "bus" might be wrong here. A "bus" needs to be large enough to facilitate an entire DDR4 stick's bandwidth to the Northbridge. The connection to each ...
J.Todd's user avatar
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DDR4 clock termination

In many places I have seen that an AC termination scheme is recommended for high speed clock termination. What is the reason for choosing this scheme? For AC termination, can a capacitor be connected ...
Sumama Hahsir's user avatar
1 vote
2 answers
3k views

SPD I2c Address for DDR4 SODIMM

While designing DDR4 SODDIM schematic for a mini-pc motherboard, I understood that I need to set an address to Serial Presence Detect (SPD) EEPROM so the CPU can identify the memory. While looking at ...
Firas Abd El Gani's user avatar
1 vote
1 answer
384 views

Termination Regulator for DDR4

I went through a previous Industrial PC Motherboard design in my company where Ritchtek RT9045 was used for DDR4 design. it's clearly recommended tat this device is ideal for DDRII/DDRIII in the ...
Firas Abd El Gani's user avatar
1 vote
1 answer
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DDRx JEDEC Standard: Retention Time

Different scientific publications [1,2] mention that DDRx memory has a (data) retention time of 64 ms while on average each cell is refreshed every 7.8 us (tREFI). I want to know where this ...
Patrick's user avatar
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Why is length matching performed with the clock trace length as the target length?

Length matching is performed mainly to avoid the skew generated among the parallel data lines/data bus width. All the high speed PCB design guideline suggest performing length matching with the clock ...
Ananthesh's user avatar
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1 answer
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DDR4 DIMM/component, different CL?

I'm learning the DDR4 technology and I don't understand how the DIMM/component can change its CL automatically. FPGAs/ASICs can basically choose the frequency to apply to the DIMM/component. Why do ...
None's user avatar
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What is the difference between source-synchronous and source clocked signals in DDR4?

Main signals comes under the source-synchronous group are data, ECC and strobe lines. My understanding about source-synchronous signal is that all of these signals would be latched on both edges of ...
student7's user avatar
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6 votes
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Why DDR4 Specs recommend that Address, Control and Clock buses be referenced to VDD?

Micron's Technical Note TN-40-40: DDR4 Point-to-Point Design Guide, page 19, says (emphasis mine): Timing Budget Suggested practice is to look at the design from a timing budget standpoint to provide ...
mFeinstein's user avatar
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