Questions tagged [design-rules]
Design Rule Checking (DRC) is the area of Electronic Design that determines whether the physical layout of a particular (PCB) layout satisfies a series of recommended parameters called Design Rules.
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Is there single column Wallace tree?
I googled and learn the rules about Wallace tree.
If I understand right, wallace tree is designed to multiply. However, I want to know Is there single column wallace tree in the initial layer just to ...
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Final design considerations for LM5143A-Q1 buck converter. Are these features needed?
After a few days of learning how to make a buck converter using the LM5143A-Q1 TI IC, it's finally becoming a reality! This is the final design, highly inspired from page 30 in the datasheet, some ...
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Altium Designer: Is it possible to detect PCB track router over cut in GND plane using DRC?
It is essential that high speed tracks have continuos ground plane with no cuts. This is essential to ensure signal integrity. That being said, can Altium designer use some sort of user defined design ...
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How can I disable hole to polygon clearance in Altium?
I have a polygon reaching to the outside of the board. There I want to place mousebites for the panel, but when they are placed, there is a clearance generated around the holes that I don't want:
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Altium Designer Rules: How to create paste rule for pads of specific component type?
I'm using Altium Designer 20.0.9 to create a PCB to be assembled by the manufacturer with the exception of several components that I will add manually later. I do not want to have paste placed on the ...
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Track to track clearance in Altium
While designing PCB in Altium, I defined a rule as follows:
Clearance > Track to Track > 20 mils
But I have LQFP100 component, and it has ~8 mils gap between pads. So I can't do routing. How can ...
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What is the minima rule for a Metal 1 layer for the 2 contacts on a poly shown on the figure? I'm using 0.18um library
Contact on a poly using 0.06 spacing for the metal 1 layer
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Why is the actual position of things in a circuit diagram not considered? What is the type of diagram that cares about the ordering?
After looking at several circuit diagrams and their actual implementation, I found that the position of the parts is not considered in the diagram. Is there any reason for this?
If all parts are ...
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Altium: Design rule to highlight a plane that is not assigned to a net
In Altium Designer 20.1.14.287 I tried to create a design rule that would highlight that a plane is not assigned to any net after running the DRC. But in the PCB Rules and Constraints Editor I only ...
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Filter query to match a via ring only on a specific layer
I'm working on a 4-layer PCB which uses 210µm copper internally and 70µm copper on the outer layers. Also I only use Thru (1:4) and remove unused via pads with...
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Why is it necessary that the poly line extends the diffusion strip in a layout?
Here the poly ends exactly at the diffusion without clearing it, why is this a "catastrophic error" ? I understand that the transistor would never turn off if the poly only partially ...
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Feedback for a circuit
I am designing my first original circuit, which is a take on the 'Useless Box'. I have designed a schematic and I am seeking feedback on it. I am a complete newbie so most likely there will be some ...
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How can I set clearance based on IPC-2221?
Below are two pictures.
The first picture is from IPC-2221. I made the second picture.
Which categories do the L1, L2, L3 and L4 clearances in the second picture belong to in the first picture at 310 ...
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How should the clearance calculation be on a coated PCB?
How many mm should the clearance be between the A and B pads in the picture below?
And clearance between C pad and D pad?
And clearance between E pad and F track?
And clearance between F track and G ...
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Altium - Keepout Area Causing Short-Circuit Warning
I have the following footprint in my PCB library with 6 through hole pads:
When I add the purple keep out area (to either the Keep-Out layer or the top layer), I get a bunch of short circuit warnings ...
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Altium: priorities not respected?
I'm designing a board with an inverted F antenna. This antenna is connected to a ground plane.
I added a specific polygon plane called "Antenna_GND" aligned with the ground pads of the ...
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What is the current state of the art design rule for SiC VLSI? Technological impediments to making a SiC microcontroller for a Venus lander at 460 °C?
A sub-discussion below Is there any demonstrated or even proposed technology that can sterilize a spacecraft with 100% certainty and yet leave it electronically functional? in Space Exploration SE ...
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I/O voltage compatibility checks as part of design rule checks during schematic design
Schematic design programs have concept of design rule checks. What exactly does this feature check?
Can it check if the input voltage on different pins of an IC is compatible with its I/O voltage? For ...
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Altium: Polygon-Specific Rules
I am making a PCB where I want to have some polygons directly connect to all the components within them, and some to only relief connect. Normally this isn't an issue as I can just set up some design ...
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100V LED signaling
I am working on a device that will convert 4,5–100V into 3v3. It is done with a DC/DC regulator.
I want to use LEDs to signal that input is plugged in and that 3v3 is also available.
What is the ...
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What is the minimum clearance I need to set between two tracks with voltage difference 36 V
What is the minimum clearance I need to set between two tracks with voltage difference of 36 V.
External traces, given that solder mask is applied on the board if it matter in calculation. And is ...
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Optimum phase margin Controller Design
I am designing a PI voltage and current Controller (Cascaded Control for Buck Converter with LC filter) and I am confused about what is the perfect phase margin to choose for the application.
I read ...
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Track clearance with flex region cutout in Altium Designer
In Altium Designer, I created a simple rigid-flex board with the 4 layers in the rigid part (top, in1, in2, bottom) and 2 layers in the flexible part (in1, in2).
I set 5mm clearance on a top layer ...
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MCU near sensors or on external board
I currently work on a sensorbox which needs to measure analog signals (temperature, power consumption,..), digital signals (magnetic contacts, positions,...) and control digital switches (relays). All ...
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KiCad 5.1: where are the design rules?
I'm following the tutorial series on YouTube at https://www.youtube.com/playlist?list=PLEBQazB0HUyR24ckSZ5u05TZHV9khgA1O, specifically the "An Intro to KiCad" videos. I'm using KiCad 5.1.2 on macOS, ...
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Altium: how to assign a net class to unconnected pins?
I have PCB with a clearance rule for nets that can be exposed for higher voltages:
In the schematic I put a blanket around the area I need to be assigned as higher voltages nets (I called this class "...
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ERC for power pin drive - Altium Designer
It'd be of great use for us to emit correct rule check violations for power pins in IC we use.
The logic is to force compiling failure when power pins of ICs are not driven correctly from power ...
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How can I allow a smaller clearance value for differential pairs in Altium?
I have finished routing a PCB in Altium (v17) and am resolving design rules violations.
In short, everything checks out except differential pairs that are violating the ...
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Why are power components meant to be power inputs in KiCad?
This was asked before but not answered properly (at least I don't get it). Why are default power components in KiCad libraries are power inputs? What is the idea behind it? I would like connect an IC ...
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Why sometimes some PCB designer add extra traces to connect two pin to each other?
I've checked a PCB board which has designed by very famous company and I saw something weird.They connected two pin to each other 2 times and from the top and the bottom of the board I am going to ...
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I2C line pulled low by MCP23017
A simple interface of MCP23017 with Rpi using I2C lines. Since there is already an internal pull-up resistor of 1.8k on rpi I didn't use any pull-ups n I2C lines.
Running ...
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How to apply a rule to only one component in altium?
I would leave the insulation of copper with 0.35 mm across the board except in a microcontroller. It requires that the insulation allowed is 0.2 mm because of the distances between the pad. How to ...
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Update tracks on board to reflect new design rules - Kicad
A PCB has been laid out with track widths according to a set of design rules by net class.
I have modified the net class design rules (Setup → ...
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Altium individual clearance for polygonpour
I want to use a poured plane in my design, but i need more clearance on the bigger pads. If i increase the clearance in the rules, all the spaces between pads, will increase. Is there a way to specify,...
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Altium: avoiding a collision check
I'm trying to create a rule to ignore a collision between some pads on the top layer and a track on another layer. So far my rule is this:
But it still says I have a collision.
These are the pads ...
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Altium. Can't apply a rule of plane connect to Polygon
Problem with Altium Designer!
I'm trying to use Plane Connect to Polygon with four conductors, but in existing PCB it dosen't work. (in new projects it working)
What could be wrong?
My actions: 1) ...
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Altium Design Rules: Short-Circuit and Clearance
I am using an older version of Altium (14.1) and I cannot stop the short-circuit errors from being flagged.
I am trying to route an eMMC BGA that has many pads that are NC (internally not ...
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Design of 7400 Series IC
Why is pin number 7 GND and 14 VCC in 7400 ICs ( logic gate ICs) ? Could the designer have put VCC and GND in some other pin number? Is there a constraint for that specific number? (Except a few cases,...
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What's the name of the Altium designer rule that warns if component "enters" another component area (PCB)?
The trouble is that this PCB is a capacitive pad and needs to stay inside the other component square area. What's the Altium rule to exclude this component?
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DxDesigner Design Rule Check Errors
I'm using Mentor Graphics's DxDesigner to design a PCB. As a side note, I do know what design rule checks (DRCs) are, but I'm completely new to DxDesigner and am not sure what each of their DRCs are.
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Which standard use for custom communication DC
I want to transmit data and power over 10 meters at 12 volts with 1 amp. I don't know if I could do it using UTP, because that's a standard for other things. Which standard should I choose? Number of ...
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Altium Design Rule - How to apply to one named component?
How can I build an Altium Designer rule that applies to only one component or reference designatorrefdes?
I tried selecting my component, S1, from the Query Helper, but that just puts the string 'S1' ...
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Altium: Starved Thermal error
I'm getting the following error on all of my GND vias. Internal Plane 1 is my GND plane:
Starved Thermal on Internal Plane 1: Via (11.002mm,23.798mm) Top Layer to Bottom Layer. Blocked 3 out of 4 ...
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Altium: how to display all DRC errors?
I've routed my PCB but had to change the minimum keepout rules which means I'll now have a lot of DRC errors - most tracks are too closely placed together and that would violate the new keepout rule.
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The need for SMD neck-down constraints
I am designing a PCB which has +5V input from a USB jack and I want this power trace to be as large as possible to reduce input resistance. While doing my large traces on my PCB tool, one of the stock ...
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Altium : How to design a width rule for a subset of a net?
On my current design, I want to set a width rule for some nets which provide power in order to get them fatter. I set a net class on the net,set a rule and it works pretty well.
Now, this net is also ...
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Altium Differential Pair Routing Via to Via Clearance
In Altium 14.3 how can one define via to via clearance in differential pair routing to produce a different spacing between via to via and track to track?
I defined a design Rule: Electrical->...
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Altium Designer Rules - Nets with different width
I would like to know if is it possible to build up a rule that treats a single net in different way.
I have some circuits in which some nets needs to be dimensioned for high current. So I create a ...
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"Net Antennae Violation" on Pad -> Via -> GND plane connection
I just started routing my first PCB on Altium. It is a simple 2-layer board with bottom layer as dedicated GND plane.
I started out placing GND vias for GND pads of the top layer SMD components like ...
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Rules and guidelines for drawing good schematics
There are a lot of poorly drawn schematics here. A few times people have actually asked for critiques of their schematics. This question is intended as a single repository on schematic drawing rules ...