Questions tagged [design-rules]

Design Rule Checking (DRC) is the area of Electronic Design that determines whether the physical layout of a particular (PCB) layout satisfies a series of recommended parameters called Design Rules.

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265 views

How to apply a rule to only one component in altium?

I would leave the insulation of copper with 0.35 mm across the board except in a microcontroller. It requires that the insulation allowed is 0.2 mm because of the distances between the pad. How to ...
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7answers
120k views

Rules and guidelines for drawing good schematics

There are a lot of poorly drawn schematics here. A few times people have actually asked for critiques of their schematics. This question is intended as a single repository on schematic drawing rules ...
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2answers
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KiCad 5.1: where are the design rules?

I'm following the tutorial series on YouTube at https://www.youtube.com/playlist?list=PLEBQazB0HUyR24ckSZ5u05TZHV9khgA1O, specifically the "An Intro to KiCad" videos. I'm using KiCad 5.1.2 on macOS, ...
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1answer
100 views

Altium: how to assign a net class to unconnected pins?

I have PCB with a clearance rule for nets that can be exposed for higher voltages: In the schematic I put a blanket around the area I need to be assigned as higher voltages nets (I called this class "...
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1answer
389 views

Altium avoiding a collision check

I'm trying to create a rule to ignore a collision between some pads on the top layer, and a track on another layer. So far my rule is this: But it still says a have a collision. These are the pads ...
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1answer
67 views

ERC for power pin drive - Altium Designer

It'd be of great use for us to emit correct rule check violations for power pins in IC we use. The logic is to force compiling failure when power pins of ICs are not driven correctly from power ...
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2answers
60 views

How can I allow a smaller clearance value for differential pairs in Altium?

I have finished routing a PCB in Altium (v17) and am resolving design rules violations. In short, everything checks out except differential pairs that are violating the ...
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1answer
89 views

What's the name of the Altium designer rule that warns if component “enters” another component area (PCB)?

The trouble is that this PCB is a capacitive pad and needs to stay inside the other component square area. What's the Altium rule to exclude this component?
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1answer
143 views

Why are power components meant to be power inputs in KiCad?

This was asked before but not answered properly (at least I don't get it). Why are default power components in KiCad libraries are power inputs? What is the idea behind it? I would like connect an IC ...
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1answer
779 views

Altium Designer Rules - Nets with different width

I would like to know if is it possible to build up a rule that treats a single net in different way. I have some circuits in which some nets needs to be dimensioned for high current. So I create a ...
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2answers
203 views

Why sometimes some PCB designer add extra traces to connect two pin to each other?

I've checked a PCB board which has designed by very famous company and I saw something weird.They connected two pin to each other 2 times and from the top and the bottom of the board I am going to ...
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I2C line pulled low by MCP23017

A simple interface of MCP23017 with Rpi using I2C lines. Since there is already an internal pull-up resistor of 1.8k on rpi I didn't use any pull-ups n I2C lines. Running ...
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1answer
788 views

Update tracks on board to reflect new design rules - Kicad

A PCB has been laid out with track widths according to a set of design rules by net class. I have modified the net class design rules (Setup → ...
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1answer
324 views

Altium individual clearance for polygonpour

I want to use a poured plane in my design, but i need more clearance on the bigger pads. If i increase the clearance in the rules, all the spaces between pads, will increase. Is there a way to specify,...
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1answer
265 views

Altium. Can't apply a rule of plane connect to Polygon

Problem with Altium Designer! I'm trying to use Plane Connect to Polygon with four conductors, but in existing PCB it dosen't work. (in new projects it working) What could be wrong? My actions: 1) ...
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1answer
251 views

Altium Design Rules: Short-Circuit and Clearance

I am using an older version of Altium (14.1) and I cannot stop the short-circuit errors from being flagged. I am trying to route an eMMC BGA that has many pads that are NC (internally not ...
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3answers
315 views

Design of 7400 Series IC

Why is pin number 7 GND and 14 VCC in 7400 ICs ( logic gate ICs) ? Could the designer have put VCC and GND in some other pin number? Is there a constraint for that specific number? (Except a few cases,...
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1answer
310 views

DxDesigner Design Rule Check Errors

I'm using Mentor Graphics's DxDesigner to design a PCB. As a side note, I do know what design rule checks (DRCs) are, but I'm completely new to DxDesigner and am not sure what each of their DRCs are. ...
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1answer
57 views

Which standard use for custom communication DC

I want to transmit data and power over 10 meters at 12 volts with 1 amp. I don't know if I could do it using UTP, because that's a standard for other things. Which standard should I choose? Number of ...
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1answer
199 views

Altium Design Rule - How to apply to one named component?

How can I build an Altium Designer rule that applies to only one component or reference designatorrefdes? I tried selecting my component, S1, from the Query Helper, but that just puts the string 'S1' ...
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2answers
2k views

Altium: Starved Thermal error

I'm getting the following error on all of my GND vias. Internal Plane 1 is my GND plane: Starved Thermal on Internal Plane 1: Via (11.002mm,23.798mm) Top Layer to Bottom Layer. Blocked 3 out of 4 ...
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2answers
859 views

Altium: how to display all DRC errors?

I've routed my PCB but had to change the minimum keepout rules which means I'll now have a lot of DRC errors - most tracks are too closely placed together and that would violate the new keepout rule. ...
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1answer
2k views

The need for SMD neck-down constraints

I am designing a PCB which has +5V input from a USB jack and I want this power trace to be as large as possible to reduce input resistance. While doing my large traces on my PCB tool, one of the stock ...
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1answer
732 views

Altium : How to design a width rule for a subset of a net?

On my current design, I want to set a width rule for some nets which provide power in order to get them fatter. I set a net class on the net,set a rule and it works pretty well. Now, this net is ...
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1answer
805 views

Altium Differential Pair Routing Via to Via Clearance

In Altium 14.3 how can one define via to via clearance in differential pair routing to produce a different spacing between via to via and track to track? I defined a design Rule: Electrical->...
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2answers
8k views

“Net Antennae Violation” on Pad -> Via -> GND plane connection

I just started routing my first PCB on Altium. It is a simple 2-layer board with bottom layer as dedicated GND plane. I started out placing GND vias for GND pads of the top layer SMD components like ...