Questions tagged [digital-logic]

Digital electronics treats discrete signals, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.

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How to read data from two shift registers in serial

I am dealing with an old circuit which has 2 shift registers in series and suppose to output 16 different values using SPI. The logic behind this circuit is a bit strange to me and I have a hard time ...
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How to multiply BCD numbers? [closed]

I have a uni project that requires me to multiply a 4-digit BCD number. This way: 1234 * 6789 = 0001 0010 0011 0100 * 0110 0111 1000 1001. How do I do this? Can you give an explanation on how to do ...
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How is the PC reset on startup?

I am reading a book about digital design. There it says in a side note that the PC (program counter) is reset to 0x00000000 upon startup. But I am wondering, how is this really done? There must be a ...
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How would I externally drive the Reset signal alongside a classic Power-On Reset circuit?

Say I have a D Flip Flop and I have a resistor, capacitor, diode, and Schmitt buffer to keep its reset line low for a few ms during startup (as per this answer) This takes care of power-on, but during ...
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VHDL FSM with several counters

I am trying to create a FSM that gets a 128-bit-long serial input and outputs it in a parallel way. The final goal is to synthesise the code for an ASIC implementation using Cadence environment. ...
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Is Quine–McCluskey algorithm globally optimal or is there a better way for K-Map reduction?

A bit of context... We are working on a project to convert FA (Finite Automata) to Digital Sequential Circuits and vice-versa. In this process we came across a step: Reduction of Karnaugh (K-Maps). ...
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Identify this chip is on a Dell OptiPlex 745 motherboard

I have a Dell OptiPlex 745 motherboard. I am unable to identify the below chip.
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Puzzling CD4060 behavior

Objective To achieve a 12-hour interval between 30-minute runs (on for 30 minutes, off for 12 hours). Circuit On (foolishly) thinking that this would be implemented more simply using discrete ICs as ...
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To drive current with open-collector gate when input is high, do I need a buffer or an inverter?

Once upon a time I knew the answer, or could just try it. But with distance I forgot. When I use an open collector, I do it to drive some load. So High means current is flowing. But when it is used as ...
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What is order of signals in streaming interface handshake?

A simple streaming interface consists of two signals, ready and valid. The streaming source asserts its valid output and the streaming sink asserts its ready output. Data is transmitted when ready and ...
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Disconnect mains voltage when voltage or frequency is out of spec [closed]

I am designing a panel that needs to disconnect single phase mains when the frequency or voltage is higher/lower than specified values. I plan to disconnect both live and neutral via a DPDT relay. The ...
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Frequency counter schematic

I was wondering what's wrong with my Proteus schematic. This schematic is supposed to show the frequency in Hertz on the display but instead only three zeroes are displayed. Is there any component ...
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How to create a mod-100 counter with two 7-segment displays using JK flip-flops?

Here is my whole diagram. There is no output while also clock is ticking... I think there is a problem with the counter, but I can't figure it out. I use rising-edge flipflops.
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Motor Controller Cloning Service? [closed]

I am a total amateur and seek the hardware engineer wizards that frequent this website, lol. Anyway, does there exist a service to clone a PCB given just a few pictures? Does a service exist that will ...
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Generate appropriate signals triggered by user input signal [closed]

The clock signal is fixed by default There is a input signal defined by me, if I give the input a pulse, it will trigger signal A, B, C. The signals like A B C can be short/long pulses or step ...
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A high-voltage logic part in PSpice

I'm trying to build the following part of a circuit: I'm wondering what the part is that has "HI" written on it; I couldn't find it in any PSpice guide.
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74xxx logic. Cheapest, most space saving way to invert 10 logic outputs

Please see this circuit. I'm trying to design a circuit that allows you to use a single button to increment a counter from 0 to 9 (then it will loop). Diode logic will convert the 10 logic outputs to ...
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Undefined(U) values in Vivado sim

I am designing a nanoprocessor and below is my instruction decoder code. As you can see I have used case statements for specific operations based on the input signal. Because of this, as you can see, ...
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How is the output (input but inverted) of a hex inverter affected by how I approach the Chip with my human body?

Currently I am messing around with the HC74 4049 Hex Inverter, which has the following pinout: I began by connecting one input (marked by the lowest brown stripe on the breadboard) to the first input ...
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Three-state buffer SPI termination requirements

I have question regarding SPI termination when using three-state buffers: Do we need termination resistor from master to three-state buffers (since ICs are very close) If we do, then do calculate the ...
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Is there a general algorithm to give result for designing m:1 mux using n:1 muxes where n<m?

I have seen a lot of examples like using 4:1 muxes to create a single 8:1 mux or using 2:1 muxes to create a single 16:1 mux. However, so far I have not seen a general purpose algorithm which can tell ...
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Show how two 74293 chips can be connected to become an 8-bit counter

In the logic symbol below, in order to create an 8-bit counter, how should I make the connections so that each 74293 chip (4-bit counter) can turn into an 8-bit counter? I know that in an asynchronous ...
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3 votes
2 answers
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Reading a file in Verilog

I want to read a file in Verilog that contains both positive and negative numbers. For example, the file contents are: -4 20 28 -52 and so on. Also, after reading ...
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Source of noise

The picture shows the circuit I am working on. A sinusoidal burst of 4 MHz (24 cycles) is generated from a waveform generator. This sinusoidal input is connected to a comparator IC through an SMB jack ...
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Controlling the RESET in this IC

I'm using this - Ethernet Switch IC - KSZ9897S This is its Hardware Checklist. On page 193 of the datasheet, they have provided the guidelines on how to connect a signal to the RESET pin. My question ...
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Create a logic circuit only using AND & OR gates

yesterday I had an exam, in which I still don't know how to resolve the problem. The question of the exam was: Create a logic circuit with 4 inputs (A,B,C,D) using ONLY AND & OR with 2 INPUTS ...
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Can a reset level from a voltage supervisor be controlled for power-on transitions?

This question is related to another circuit about I have talked in an previous post. But I think by the nature of the question, this must be treated apart, in a new post. I need to keep a signal from ...
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1 answer
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Correcting the lower output level of a square wave generator

I have assembled a square wave generator following this schematic from an old book. R1 and R2 are both 1 kohm, C1 is 68 pF, and C2 is 2.2 nF. The author of the book claims that this combination is ...
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2 votes
2 answers
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How can I design a digital circuit where the output is 5 times the input? [closed]

I tried to solve this challenge by enhancing my skills in digital circuits, but could not solve it. How can I design a digital circuit where the input is only 2 bits and the output equals 5 times the ...
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1 answer
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Identifying Protocol Using a Logic Analyzer

I used a logic analyzer to read the data line from a small camera battery and would like to understand the authentication my camera is doing to the battery over the one data line. Is there any way to ...
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CORDIC module for (0, 90)

I found this CORDIC Verilog code online. It calculates sine and cosine from (0, 360). I was thinking if there is a way to modify it to (0, 90) and then use 4 such CORDIC modules in a pipelined ...
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STM32H7 DMA not transferring correct values into TIM15 CCR1 register, why?

I feel like I am running out of options as to why this is occurring as the RM isn't that accurate to setup DMA + PWM using Timers. The goal is to use TIM15 as a PWM generator running @ 800kHz running ...
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SystemVerilog testbench giving don't care (X)

Can anyone help me figure out as to why I'm getting don't cares? I think it's not reading the signaldata.txt file which is why it prints don't care. ...
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1 vote
1 answer
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D flip-flop frequency divider

I'm using a transmission gate base DFF to build a simple frequency divider. It worked, but I'm getting some weird waveform at some intermediate nodes and the power consumption is high too (11 μW). ...
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FSM for carpark system with 2 sensors

Basically, I want to design a system where a vehicle goes through one of the sensors, then both, then leaves one, leaves both and finally counter goes up by 1. I've been able to draw the graph below. ...
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1 answer
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Error (10500): VHDL syntax error at setpoint.vhd(37) near text "when"; expecting ";"

It may be simple but I don`t know what's the error. ...
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2 votes
1 answer
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How to achieve signal gating with trigger input

I am currently working on a project that generates enable pulses of extremely diverse lengths from microseconds to days and under normal operation will start execution under a trigger input. However, ...
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Trying to understand how to design properly asynchronous signals in SystemVerilog

I have implemented a serial-in parallel-out register implemented in SystemVerilog: ...
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1 answer
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"Tiny " XOR gate simulation not working

I am trying to implement this below XNOR circuit in Cadence. I am using GPDK 180nm and 1.8 V power supply. Here is the schematic in Cadence. Doing a DC simulation, I am not getting proper voltages at ...
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1 vote
1 answer
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In SystemVerilog, will assign a variable to itself within an always_comb block generate a latch?

In SystemVerilog, always_comb blocks must always specify the value of all the signals within them for all possible case branches ...
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Strange behaviour AT28C64B

I recently got a bunch of AT2864B EEPROMs that I am using to make multiplexer for a display. I've hooked up all values correctly and looked through my code countless times without any trace of such ...
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Trigger falling signal on hi/low chatter

I want to use one of those tilt-ball switches on an interrupt with a microcontroller that can only trigger an interrupt on a signal FALLING from high to low, in a low power circuit. The tilt ball ...
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2 votes
1 answer
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Is it acceptable to gate an SPI clock (sck) to disable it when ss is high? (in an FPGA)

As far as I know, gating a clock in an FPGA is a very bad design practice because it can lead to clock skew and higher power consumption. This is specially true for the system's main clock, but what ...
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Which edges (h->l or l->h) does this circuit detect? [closed]

Which edges (h->l or l->h) does this circuit detect? When I simulate it, the output voltage is constant, so it does not seem like it would detect any edges, which I did not expect.
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How does a TTL gate input strain an ALS-TTL gate output, and how does it strain a CMOS gate output?

How does a TTL gate input strain an ALS-TTL gate output, and how does it strain a CMOS gate output? Or do you maybe know where I can find resources on the topic?
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D flip-flop BCD upcounter

I am trying to design BCD upcounter (0~9) using Dff in Pspice. From the state table below, my optimized boolean expression is like this: input D8 = Q4Q2Q1 + Q8Q1’ input D4 = Q4’Q2Q1 + Q4Q2’ + Q4Q1’ ...
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Can circuit without memory give output depending on the order in which input pins were activated for non-commutative operations?

Going trough making small NAND based computer. I have two input pins zy (zero 16 bit Array y), ny (negate bitwise 16 bit Array y). Implementing each one separately or in connection is no problem but ...
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Manchester encoding where the initial state is low

Is this correct? I thought in Manchester encoding the 0's had to be high-low transition, even if the initial state is assumed to be low and 1's low-high.
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How to design, build and test synchronous sequential circuits using T-Flip Flops?

I want to Use T flip-flops to design the circuit specified by the state diagram of following figure. Zi represents the output of the circuit. This is my school project. I did everything. But I cannot ...
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Does VGA (video graphics array) carry an analog-modulated digital video signal?

If VGA (video graphics array) is analog, then how is it compatible with a digital monitor? When I say "digital monitor", I am referring to TFT LCD display monitor. My guess is that maybe it ...
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