Questions tagged [digital-logic]
Digital electronics treats discrete signals, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.
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Future of Electronics [on hold]
Actually I am studying electronic engineering and I have to make a choice of specialization.
Until now what I have learnt about circuits can be divided in two cathegories: on one hand everything ...
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1answer
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Why is this signal considered to be uninitialized?
In my VHDL design, I have a counter, and a reset mechanism. The counter counts up to 50M, and sets the "ready" signal to '1' and starts over. The reset signal is active high and resets the "ready" ...
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Frequency Sensitive Switch
A legacy product we are making uses this obsolete Frequency Sensitive Switch, Consumer Micro FX-301L.
The switch is setup such that it switches on (-12V) at 2000Hz +-100Hz and switches off at 250Hz. ...
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2answers
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Trigger based on Time Difference between two sensors / Catch a Miss on sensor
I have two Sensors S1 and S2, S1 is a 24v inductive proximity sensor which i isolated using octocoupler to work at 5v and S2 is a transmissive type phototransistor sensor, both are placed at a fixed ...
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1answer
61 views
Different implementations of JK flip flop
I know following variants of SR flip flop:
Using NAND-NAND combination
Using AND-NOR combination
I was guessing how we can obtain JK flip flop for each of these variants. I found below approach ...
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Earth Leakage current understanding
In our design used TRIAC to control the load, As per the product field test setup i should short the neutral and earth connect together also the digital GND is connected with chassis.
The input AC ...
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1answer
60 views
How can I create a long (10 second) pulse from a short active pulse?
So let's say I have an incoming signal: 1 clock cycle from a ~1-100 MHz (50 MHz for this example) clock domain. And I want to drive an output that must be active high for 10 seconds for each time the ...
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Multi-cycle operations within Logisim [on hold]
I'm working on a circuit within Logisim. I have a FSM and a set of Registers the register in the diagram is a Parallel Access Shift Register and my question isn't in regards to the FSM itself, my ...
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2answers
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VHDL UART core transmitter bits
I was studying the VHDL uart core given here. At the bottom of the page is shown the transmitter code. Notice the line
tx_data <= "1"&data_i&"01";
...
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1answer
51 views
Finite State Machine using 3 bit down counter in Logisim
I had previously asked this question: Start/Stop MOD N Counter And this is sort of a continuation off of the original question as my main goal is to be able to stop the counter from counting when it ...
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2answers
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Replace an inverter and a MOSFET with an IC for 3v3 to 5v level shifting?
First, I'll go through what I think is going on in this circuit. If I understand it correctly it's basically a logic converter. The 3v input comes from STM32 GPIO and the output goes to a floppy disc ...
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1answer
39 views
Different variations of SR latch
Wikipedia gives following circuits of flip flops:
SR latch using NORs
SR latch using NANDs
Note that circuit 1 have R input at top and S below it.
Also note that circuit 2 have active LOW inputs, ...
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2answers
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CMOS inverter propagation delay
Let's consider a CMOS inverter. It is known that its propagation delay depends on supply voltage (VDD) and on output parasitic capacitance Cout (which is due both to its transistors' output intrinsic ...
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1answer
42 views
Forming synchronous SR flip flop from asynchronous SR flip flop
Wikipedia gives following circuits of flip flops:
SR latch using NORs
SR latch using NANDs
Clocked SR latch using NORs:
Clocked SR latch using NANDs:
I understand how circuit 3 is obtained from ...
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1answer
25 views
Starting and stopping of a Mod N Counter for a FSM in Logisim
I'm working on a circuit for control logic. I'm using a 3 bit down counter. There is a control signal that when it goes high starts the counter by presetting it with a value of 5. The counter is ...
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1answer
67 views
How JK flip flop works?
Consider below JK flip flop circuit and truth table:
I was guessing how Qn+1 column in truth table is calculated.
Interpretation 1
One text book says:
Consider the case J=1, K=0, Qn=0, Qn'=1, line ...
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4answers
62 views
What does measuring voltage do to the current or signal of a pin? [SOLVED]
I have a problematic digital signal which starts working when I measure the voltage between the pin and ground. What's the effect of a voltmeter on a pin (or to rest of the circuit) when you measure ...
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High Voltage Push-Pull MOSFET logic gates
Hello, I would like to implement typical MOSFET logic gates in my circuit with V+ at 24V and Input ranging from 0-24V. This posts a problem for the MOSFET however as I would either exceed the gate ...
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2answers
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Simulate Shift Register on AVR (Configurable Logic/Timers?)
Recently I set up two MCUs (ATtiny1616) to perform basic serial communication using shift registers I made myself.
simulate this circuit – Schematic created using CircuitLab
Here is the logic ...
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2answers
96 views
Is there possibility for a race condition in the following circuit?
On this wikipedia page, there is an example of a circuit which implements a D latch using NAND gates :
Let's say the flip flop is initialized correctly (eg : Q = 0 and !Q = 1).
If D = 1 and E = 0, ...
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0answers
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How to understand min/max voltage specification in datasheet?
I've seen different types of min/max voltages in this datasheet and not sure whether I've understood them correctly, so I want to double-check it here.
As shown below, there two types of min/max ...
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1answer
51 views
VHDL simulation 'X' output (Vivado)
I'm trying to build a modulo-4 counter using dataflow modeling. I devised the logic circuit like the following;
simulate this circuit – Schematic created using CircuitLab
I wanted to implement ...
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1answer
168 views
NOT gate without resistors [closed]
I want to make an IC with homemade bipolar junction transistors. Since I have a large number of logic gates, I don't want to use resistors in the NOT gate because it saves space on the board and I can ...
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0answers
78 views
Choosing a suitable PFD for PLL
I'm building a capacitive vibration sensor and it has to reject the stray capacitance by locking the LC oscillator at 64 MHz, where I can demodulate relatively small frequency changes. The best way to ...
2
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0answers
70 views
Bipolar transistors that only connect via base to emitter
I am trying to understand how to use this configuration of the LTC2992 power measure IC and the only part I am confused with so far is the two transistors which I have circled.
What I know so far ...
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3answers
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Communication protocols
Are the I2C and SPI protocols implemented in the integrated circuits?
For I2C,
There must be some circuit to be able to process the start bit, device address, internal register Address, Data and ...
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2answers
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Logic inverter feedback resistor, SPDIF Input/Ouput circuit
What purpose of these resistors? Spdif level about 0.5Vpp. Do I need use feedback resistor if I will convert 3.3V SPDIF to 5V?
I want to make 4-way SPDIF Input/Output for WM8805 I2S<>SPDIF ...
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2answers
153 views
How to analyze S-R latch circuits?
I'm trying to understand the circuit below (from the Apollo Guidance Computer), which is two S-R latches connected together. The top input resets the output and the bottom input sets the output. But ...
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Cannot make a couple of HT12E & HT12D work properly together
I have built the following setup, which pretty much comes from the specification documents of the HT12E & HT12D thelselves:
https://www.holtek.com/documents/10179/116711/2_12ev120.pdf
https://...
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2answers
57 views
Logic circuit for making sure that only one of several signals are logic-high
simulate this circuit – Schematic created using CircuitLab
I have a circuit as seen in the schematic above. It has 4 different output stages. Each one has an "Enable" pin. The user is able to ...
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1answer
64 views
Clock failure detection on FPGA
So I'm designing an FPGA based device, it has two clock sources, one is 48 and other is 64 MHz and I need to implement a detector if one of them (or both) is not present and light a warning LED. How ...
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1answer
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Make an OR gate from 2 NAND gates? [closed]
I have a homework problem on logic gates, in the picture below:
Now, I have already made NOT and AND gates. On these OR gates, (I used a simulator by the way) I could not find any solution.
I have ...
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1answer
57 views
Multiplex Analog pin and digital pin on single pin
I have to manage one single analog pin with other digital IO.
I am using a PIC micro, where I have utilized all the pins and I want one more pin for analog input. At the current stage, I can not ...
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2answers
56 views
Digital Alarm Clock in Multisim. (Home Work/ Final)
I apologize for the schematic. I know it is not the prettiest to look at. My clock runs slow. I know this is because of my 555 timer. I was off somewhere in my calculations and ended up with a 70hz ...
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2answers
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Is there an intuitive reason for why NAND gate is a universal gate?
Now I know the maths and logic to figure out that every boolean function can be expressed using only AND and NOT gates, which in turn can be expressed using only NAND gate and hence every boolean ...
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2answers
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Switch multiple contacts in parallel from a single 24V DDC output
I have a DDC (direct digital control) with a 24V digital output and I need to control around 100 external circuits, each having their own input.
The switching distance between DDC and remote panel ...
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1answer
32 views
Implementing a SN74LS245 Octal Bus Transceivers With 3-State Outputs in Logisim
I'm testing out different circuit simulator programs and I was able to build the integrated circuit SN74LS245 Octal Bus Transceiver in a program called Digital ...
0
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1answer
46 views
Number of implicants in given k-map
Why pairs and quad of 1's are not counted as implicants in the given k-map
ref:- https://www.google.com/amp/s/www.geeksforgeeks.org/digital-logic-implicants-k-map/amp/
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Number of implicants in case of don't cares
How many implicants are present in the given k-map?
I know that there are 6 prime implicant and 0 essential prime implicants.
My attempt:-
by taking each 1 and X individually(as a product term) we ...
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0answers
22 views
Mask Extension and Logic Minimization
I was reading a paper (Routing Table Compaction in Ternary CAM) which reads as following :
"The mask extension technique reduces to a logic minimization problem.
In the discussion, I use cube to ...
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1answer
87 views
How to automate Instantiation of modules in Verilog? (permutation)
Consider this file tb_sr_latch.v:
...
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1answer
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1answer
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If you wire together two TTL outputs, which one wins?
If you connect together two outputs from 7400 NAND gates, which output will dominate - high or low?
Background: I'm reverse-engineering a 1969 circuit board, and in multiple cases they tie together ...
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2answers
58 views
Finite State Machine and Reset Signal
let's consider a certain finite state machine, for instance a Mealy Machine:
I was told that it cannot work properly in absence of a reset signal (for the State Register), since we would not know the ...
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0answers
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How to convert 3/3 to 2/3 clock ratio?
How to convert 3/3 to 2/3 clock ratio?
Clock : 10 10 10 (3/3 clock ratio)
Output : 10 10 00 (2/3 clock ratio)
Clock using NE555, work at low frequency about 3 Hz to 6 Hz.
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1answer
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IC Enable Pin not working as expected
I'm working with a TH3122 I/K-Bus transceiver with a built in 5v/100mA regulator. I'm trying to use my PIC24FJ1024GA606 to pull the EN pin of the TH3122 up/down in order to enable and disable the ...
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1answer
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H-bridge logic driver in Verilog
I am trying to come up with a driver logic for an H-bridge (seen in the image attached) which would provide a single-ended or a differential pulse based on a user choice.
Input signals: clk (clock, ...
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1answer
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Error in simulating bdf with Waveform.vwf.vht, but bdf compiles successfully
I am trying to design an instruction register and controller for an ALU that I designed previously. I made the register with 2 muxes and 2 D flip-flops, and I made the controller with a T flip-flop ...
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1answer
40 views
Voh value not provided
I have this EEPROM IC where I want to check the logic level compatibility with another IC.
But here Voh value is not given. I have observed this in my other IC also.
Why is the Voh value not provided?...
