Questions tagged [digital-logic]

Digital electronics treats discrete signals, unlike analog electronics which treats continuous signals. Digital logic is used to perform arithmetic operations with electric signals and constitutes the base for building CPUs.

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What is the difference between an integer frequency divider and a fractional frequency divider?

Let's say I have a 5-bit integer frequency divider first. Does this mean that I can divider my input frequency anywhere from 1 to 2^5 (or 2 to 2^5+1 as dividing by 1 doesn't make much sense)? Now let'...
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How do I add a secondary power source only if there is a primary one active?

Sorry, this question might seem super basic to some people, but I'm new to circuits. (I am learning on Tinkercad). What I'm doing is I have a power supply from an Arduino. When a button is pressed, it ...
DaCuteRaccoon's user avatar
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Why am I getting unknown states in output for Booth multiplier Verilog code?

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Siddhali Gadiya's user avatar
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For a simple sequence detector, is there a problem with the FSM diagram for unused states?

This is the diagram, and the sequence we are detecting is 1011. The problem did not specify whether it is Mealy or Moore FSM, or whether it is overlapping or non-overlapping. When we get an input of ...
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9T SRAM Circuit Supporting 1-bit Multiplication

I was reading a paper that added a 3T NAND gate, consisting of two NMOS and one PMOS, to the regular 6T SRAM, achieving 1-bit multiplication. However, I'm struggling to understand how the NAND part of ...
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Implementing a circuit using only NAND-2 gates

I have this boolean expression that I got through a k-map twice, once using POS and the other SOP, and I am supposed to implement both minimized f's that I found using only NAND-2 gates but I am very ...
Salma Mostfa's user avatar
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4 answers
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Is the Gray code unique?

After googling, I found that a Gray code is not unique and the only requirement for a sequence of binary strings to be a Gray code is that two adjacent binary strings differ by only one bit. Can we ...
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Minimum voltage to register a 1 on 74HC devices

It must be late in the day or I am just losing it. I can't quite understand what this datasheet is saying for input voltage level. I am running my 74HC245 at 3.3V. I have the OE tied high, but ...
Kevin McQuown's user avatar
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How to convert an interrupt signal to toggle a continous signal

I am working on a project where a momentary contact micro switch is used to activate the Vdd pin of a 555timer IC - [Datasheet Link]. Thus, I need to toggle the Vdd pin every time a micro switch is ...
Roy's user avatar
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P-Channel Mosfet as a switch, always open when voltage to source and digital HIGH to gate

I have a signal provided by an Attiny (in this case I am using an Arduino to simulate the signal). It's digital out, so HIGH and LOW. I pass this through a NOR Gate to invert the signal. When I ...
kissumisha's user avatar
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Z80 interfacing, address decoding logic produces noisy signals

I really would like to have suggestions and feedback from someone. It's about digital logic, in detail, the Z80 interfacing. In this design, I used a 74HC30 which is a 8-input NAND Gate. I'm using it ...
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Problem with LED driver - LEDs do not switch on when button is pressed

The below circuit is not working how I'd expect it to. The circuit has two parts, the top half is a battery charger that takes in 5V and charges a battery. The bottom half is an LED driver, that ...
Handsome's user avatar
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1 answer
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Verilog output register not changing

I have to use combinational logic to write Verilog for a circuit schematic. However, my output registers, CLK1 and CLK2, do not change and are stuck at the initial values. What is causing this bug? ...
Gabriel Zhang's user avatar
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1 answer
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Timing parameters of sequential circuit - digital electronic

Problem Determine the timing parameters (\$T_\text{cQ,bb}, T_\text{su,bb}, T_\text{h,bb}\$) for the black box logic circuit seen below: - Attempt \$T_\text{cQ,bb}\$ is the time it takes for the ...
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Can you transmit a number stored on a digital counter over a network protocol without a micro-controller? [closed]

TL;DR I am storing a 24-bit number that represents number of pulses from a clock on a digital counter IC, and want to transmit that number to a more sophisticated device to perform a speed = distance/...
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74LS173 output voltage won't go above 3V when it should be HIGH. Any ideas why?

I'm seeking a solution to understand why the output voltage of the 74LS173 is not reaching 3V or is not in an undetermined state when the output is expected to be HIGH. What could be the the cause of ...
youssef1452hakam's user avatar
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Is there any way to know how real discrete components are being connected to each other using logical gates?

Let's say we created some gates or something with VHDL. How can I convert that code into those diagrams that show how discrete components (such as transistors and resistors) are connected to each ...
dsa's user avatar
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6 answers
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Synchronization of handshake channel with different clock domains

My course on design of digital systems uses the book "Introduction to Asynchronous Circuit Design" by Jens Sparsø. On page 156 he talks about synchronizing a handshake protocol between a ...
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Tri-state buffer, why is it called high-impedance?

I found this picture of a tri-state buffer: When the enable signal is 0, the output is disconnected from the voltage sources. But why is this called high-impedance? From what I understand impedance ...
user394334's user avatar
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1 answer
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Misunderstanding in sequential and combinational implementation, based on blocking or non-blocking behaviour

I have a very simple module that waits for the valid signal to become 1 and then sets the ...
Saeed Jazaeri's user avatar
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2 answers
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Contamination delay of 74 series chips

I'm a beginner in digital design, so my question might seem dumb. But how can I get the contamination delays of common 74 series chips? This is the datasheet for 7404, but it only mentions the ...
Julian's user avatar
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How do I make a gate diagram for \$a'c'+abc+ac'\$? [closed]

I have checked with the program Logic Friday and it checked the shown gate diagram, which showed me another result and came with this gate diagram: Is this the correct answer?
Invulnerable Immortal's user avatar
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Proteus adder-subtractor circuit simulation

I made an adder-subtractor circuit using Proteus and wanted to simulate the circuit. The full adder circuits were made using the sub-circuit mode . Here's the ...
Ogweno Emmanuel's user avatar
1 vote
1 answer
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Designing a sorting network with an FSM as opposed to combinational logic

During this semester I have been spending a bit of time learning how to use Verilog. I took on a project to develop a sorting network for 1024 32-bit numbers and tried to develop the circuit by ...
IdenticallyEulerian's user avatar
2 votes
3 answers
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LED to the carry out pin of my 7483 IC doesn't glow in Proteus

This is the simulation I did in Proteus: The BCD adder will work for ABCDE=00010,00111,01000,01101. The LED connected to the Cout pin doesn't glow for any ...
Anya's user avatar
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1 answer
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Verilog variables updated only when assigned as an output

I am facing a strange issue, and I am not sure what is going on here: assign output_data = {3'b000, cmd_state[1:0], w_data[2:0]}; Where last 5-bits of output data ...
Nicka S's user avatar
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3 votes
2 answers
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Is it possible to create a logic gate design for a clocked D flip-flop register where there is a synchronous reset and an enable pin?

I'm currently designing a register where there needs to exist a data input pin (DIN), Clock (CLK), Reset (RST), and a RUN pin. The register is designed such that, only at positive edges of the clock ...
RizqiBusiness 's user avatar
1 vote
1 answer
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Reason for the degraded I2S signal

I'm working with one of the devices from the NXP's IMX family - the IMX93 evaluation board. I've managed to setup the sound card drivers already, the next step was to test I2S signals output via the ...
Antoni's user avatar
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1 answer
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VHDL schematic without connections [closed]

I'm learning VHDL and I tried to replicate a circuit that I found surfing in internet. The problem is that the schematic shows without connections in the input ports. The program is a frequency ...
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Problem with getting data properly from memory using RoCC interface

I am using RoCC interface to communicate with Memory in chipyard. The memory has the width of 64 bits, and I need to read the first 64 bits and put it in lower register and then read the next 64 bits ...
engineer1155's user avatar
2 votes
2 answers
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Can anyone please take a look of this Verilog HDL code? Does it look strange by any means?

I am wondering if it is ok to use output instead of wire for another output in Verilog coding (using Quartus for this). Just ...
towel Lijiang's user avatar
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1 answer
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74LS74N did not work exactly as I expected [closed]

74LS74-Dual DFF module driven both Q and Q' to high even when I turn on Preset or Clear pin. What wrong?
South goodman's user avatar
2 votes
1 answer
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On a method of clock gating with a latch

My textbook (CMOS VLSI Design: A Circuits and Systems Perspective, 4th edition, by Weste and Harris) gives the following discussion of a particular method of clock gating into some digital block. I ...
EE18's user avatar
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What may cause a too long DS2482 reset pulse?

We experience odd behavior with the DS2482-800 8-Channel 1-Wire Master. Often, when reconnecting a 1-Wire slave (DS28E17 1-Wire-to-I2C Master Bridge in our case), communication does not resume because ...
Bosz's user avatar
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1 answer
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Is a feedback loop from program counter input to output problematic?

I'm designing a very simple CPU to be built on a custom PCB. I designed the CPU in LogicCircuit, and it seems to work. But I'm wondering it a specific part of the CPU will also work in real life. I ...
RenX's user avatar
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7 votes
1 answer
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Unknown logic gate on circuit

I'm studying the CMI decoder circuit from Maniatopoulos, Antonakopoulos and Makios, 1995, but I can't understand some symbols in the diagram. They look like a small logical OR. Can anyone tell me what ...
P0nyL0v3r's user avatar
1 vote
1 answer
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Which is the preferred circuit layout? Horizontal vs. Vertical (Combinational logic)

I have 2 equivalent circuits Picture 1 (Compact, a bit messier) Picture 2 (Easier to read, less compact)
NonComposMentis's user avatar
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3 answers
102 views

What property of gray code makes it minimum error code?

Other way round, If I am building a new code how should I make it minimum error code?
barnyard9's user avatar
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2 answers
65 views

Does the chipset act as a "gateway" to the system bus?

I am trying to understand how exactly the main memory and peripheral devices like NIC, video card, hard disk, USB, etc. are physically or electrically connected to the system bus. Pasting here the ...
Noob_Guy's user avatar
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0 answers
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LJ18A3-8-Z/BX Proximity sensor Connection with ESP32

I am using LJ18A3-8-Z/BX proximity sensor with ESP32 as Digital input. Issue is LJ18A3-8-Z/BX i dont know its esp32 compatible or not. I don't want to use resistor divider as it does not feel ...
Zunuran Nasrullah's user avatar
2 votes
1 answer
99 views

Is this Mealy FSM representation correct for 00111? [closed]

Is this Mealy FSM representation correct for a non-overlapping input bit sequence detector for the sequence 00111?
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1 vote
1 answer
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How to make a waveform simulation in Quartus II from testbench module

I wrote a Verilog gate-level description and a testbench for these requirements. However, I don't know how to make a waveform simulation in Quartus II. How can I make the waveform simulation to get ...
South goodman's user avatar
2 votes
1 answer
68 views

Practical Considerations for a Square-Wave Inverter [closed]

I'm hoping to understand some practical considerations for a square wave inverter. Particularly, is there additional circuitry I need around the transistors to ensure proper operation? (e.g., ...
pbandlead's user avatar
1 vote
1 answer
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RTL viewer diagram shows no logic gates

I'm trying to write a Verilog gate-level description of this circuit: My code is here. I compile it on Quartus II (there is no error): ...
South goodman's user avatar
5 votes
1 answer
555 views

What does "strobe" mean in the context of semiconductors?

I was reading the data sheet for SN7425, and it calls the semiconductor a "Dual 4-Input NOR Gates With Strobe" What does it mean by "Strobe"? Does it affect input/output? https://...
persononthenet's user avatar
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Working of the 74LS76A (JK Flip-Flop)

I have been trying to understand the logic diagram of the 74LS76A as shown in this datasheet. Let's say that the flip-flop has been cleared using the CLR input and then it becomes stable as follows - ...
Kushagr Jaiswal's user avatar
2 votes
1 answer
147 views

My 1-bit ALU is not able to do subtraction [closed]

I am trying to make a 4-bit ALU in Verilog which can perform the following functions: Add Subtract Compare (>,<,=) AND The approach I have taken is to make 4, 1-bit ALUs and connect them in ...
Koustubh Jain's user avatar
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1 answer
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What is this symbol (for an inverter)? [duplicate]

In Weste and Harris's VLSI text, they use the following symbol for a buffer \$Y = A \$. Why does the second inverter symbol have the inverting bubble in front of the gate? Is there some significance ...
EE18's user avatar
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1 answer
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How to legally/properly run a Verilog file that needs other files?

I have written a simple ripple carry adder in Verilog (in a structural fashion), and I have defined the required half adder in a module in another file. When I run them (using ...
Koustubh Jain's user avatar
3 votes
1 answer
368 views

Am I correct that this digital IO protection diode choice doesn't make sense?

I'm currently redesigning a breakout board for an expensive FPGA data acquisition device we work with frequently. The designer of the past version added some components between the FPGA's digital IO (...
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