Questions tagged [digital-logic]
Digital electronics treats discrete signals, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.
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If I connected two outputs with a wire, one with the information A+B and the other with C+D what would these two combined signals make?
Lets suppose:
I connected the output of 2 different OR logic gates:
out 1: A+B
out 2: C+D
with a wire leading out such that these 2 outputs are connected.
what would these signals form to make?
...
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1answer
51 views
How do I make a double dabble circuit with logic gates
Im attempting to make a 8 bit binary calculator that displays on multiple seven segment displays. Can double dabble be done with logic gates. If so, how?
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2answers
52 views
How to get a 24 V signal generated when the input circuit state changes?
So I'm an IT guy with no electrical experience trying to figure this out.
How do I set up a circuit that puts out a 24 V signal for a short time or puts out a continuous 24v signal that quickly turns ...
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0answers
49 views
I need some help with 555 timer IC in water level indicator [on hold]
I am working on a project that is water level indicator. Here's the condition:
Motor turns ON after every 1 min and if water is present in the tank then it remains ON else it turns OFF after 5 sec.
...
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38 views
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70 views
Adder / Subtractor in VHDL, wrong output
i make one subtractor/adder in vhdl, i use the modelsim, but have a problem in the output, few results be correct, someone can analysis if the logic is incorrect.
FullAdder
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1answer
47 views
How does this serial input DAC work?
This is the datasheet for 6379A:
datasheet
I looked at the timing charts, but I’m still having trouble figuring out how the IC treats the serial input.
Apparently, SI is sampled at positive clock ...
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0answers
33 views
In NMOS inverter with enhancement load, why the load is always saturated?
Why the load in NMOS with enhancement is always in saturated mode?
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2answers
44 views
What is the minimum output frequency according to this datasheet?
Can this DDS output down to 0.05Hz sine?
I think the resolution is 0.0291 Hz. Does that mean that is also the miimum freq. it can synthesize?
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1answer
36 views
Make a circuit that indicates an odd number of ones using a 3-8 Demux and two logic gates
Using 3-8 Demux and two logic gates, make a circuit that received 4 bits and returns 1 if the number of 1's is odd and else returns 0.
My try:
Using truth table, we get that the desired function is:
...
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0answers
22 views
Find the essential prime implicants [on hold]
find the prime implicants(PI),essential prime implicants(EPI) and selective prime implicants(SPI) for the function
F = summetion m(0,2,3,5,7,8,10,11,14,15)
I am confused regarding EPI and SPI for this ...
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2answers
58 views
How to measure 2.5 volts out of 5 volts and serial resistors?
I have a circuit that's being run from a 5v and is essentially a series of resistors. I want to be able to "tap" it to get 2.5v - 3v out of it, which I think would be straightforward, but I want to do ...
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1answer
46 views
Using 2 Data Flip Flops to create an up counter from 0 to 3 and repeats
I've done most of the legwork. I've got this design working using 2 set reset(SR) flip flops, but I need to make it using 2 data flips, a.k.a D flip flops.
What I did:
Note the numbers not in ...
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1answer
25 views
Reducing the amount of controller output required - making k of n binary to unary decoder out of 1-of-n decoders
I am a kind of self-taught electronics dabbler and being a selftaught tinkerer has the unfortunate consequence of reinventing the metaphorical wheel quite often. I'd like to avoid this fate again if ...
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1answer
94 views
Implement an 8 input AND gate with least delay
I'm trying to implement an 8-input AND gate using CMOS technology with the best number of stages and least delay (I have attached the schematic in the link given).
Using logical effort I have so far ...
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0answers
31 views
Karnaugh Maps in POS instead of SOP
From my understanding, to use karnaugh maps to simplify an expression, you would have an SOP expression that does not have to be canonical and then group the 1s in the table.
So that got me wondering....
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1answer
68 views
Ultrasonic Sensor Serial Output Grounding Issue
I have a small circuit which uses a Maxbotix Ultrasonic sensor (Datasheet: https://www.maxbotix.com/documents/HRLV-MaxSonar-EZ_Datasheet.pdf) to take distance measurements and then transmit them over ...
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1answer
37 views
Setup and Hold Time: A general method to find whether a block satisfies the constraints
How to determine whether setup and hold time constrains are satisfied in a digital block? I encountered a question on the same, and it would be really helpful to know a general way to determine the ...
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1answer
54 views
verilog code for 2bit * 2bit multiplier [closed]
There will be two 2 bit inputs (0 to 3 in binary), binary multiplication is to be done on these inputs, the output should be a 4-bit binary number, this output will be fed to a 7 segment display on an ...
4
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1answer
58 views
How to generate a clock for my ring counter?
I want to run a 4 phase switched reluctance motor at low speed. The expected conduction sequence for the motor winding(y, r, b, g) follows the output similar to that of a 4-bit ring counter and thus I ...
0
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2answers
45 views
How to get the MSB into a logic gate which will check if a number is negative or not?
I need to create a logic gate which will find out whether a number is negative or not.
The input is 8 bits and the output is 1 bit, and if the input is 1 (i.e. negative number) then the output ...
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1answer
49 views
Separate two batteries getting charged by one charger with diodes?
I've got a robot that I use two batteries on. One of the batteries power the servos and engines and the other is for the digital boards.
The servos need 5 V.
The control board and LCD run on 5&...
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1answer
68 views
How to find out if the input of a logic gate is negative in two's complement?
I'm trying to create something which will output whether the input of the logic gate is a negative number or not in two's complement. I understand how twos complement works etc, but i'm not entirely ...
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3answers
54 views
How to find out if a binary number is zero or not using logic gates?
I'm trying to put some logic gates together which would perform a task of finding out whether a number is zero or not. I came across a thread like this on here already (How to find out if a binary ...
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0answers
29 views
Variable input MUX in Verilog
What's the best way to make an N:1 multiplexer in Verilog (NOT SystemVerilog), where the maximum N is 64? Each input is 32-bits wide and there are N such inputs. Verilog doesn't allow two-dimensional ...
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0answers
39 views
Problem based on Latches (Sequential Circuits)
I am trying to solve the following question:
I want to know:
If the truth table for \$ Q_{n+1}\$ and \$\bar Q_{n+1}\$ is correct.
I have found out the Reset and \$Q_{n}\$ conditions. However, I see ...
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0answers
65 views
How to generate two individual signals based on falling/rising edges from two different PWM signals?
I am looking to implement a discrete circuit that can generate two different waveforms based on the rising/falling edge of two individually limited 50% duty cycle PWM signals.
See following figure:
...
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2answers
47 views
Question on output of an FPGA
I have been trying to solve this basic FPGA problem with multiplexers, but I cannot garner the meaning of the notation 0/1. Can someone throw some light in this regard? What do notations like 0/1 mean?...
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0answers
56 views
I’m having trouble solving this digital circuit. Help!
I need to design sequential logic circuit from this state diagram using only 2 D-latches.
And this is my attempt:
If I put it in the simulator it just gives me error and wont count. I assumed that ...
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1answer
42 views
How to use comparator functions of 74LS181?
I'm experimenting with the 74LS181 ALU (see here if you like), and it is going well, but I am unable to figure out how to use the A=B, A>B, and A<B comparator functions.
The datasheet states, "...
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1answer
23 views
WolframAlpha results for logic statement input
I was trying to simplify the following Boolean logic equation using wolframalpha.com.
(not (A) and B and C) or (A and (not(B)) and C) or (A and B and not (C)) or (A and B and C)
When I entered it ...
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0answers
33 views
signed adder and subtractor
I need to create a circuit that accepts 2 numbers that consist of 4 bits (the first bit is their sign and the 3 rest the number).then with an input S I will choose whether i want to subtract them or ...
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4answers
60 views
Multiple sensor circuits connecting to one counter and a 555 timer IC [closed]
I have to use a 555 timer in a context where I have multiple sensor circuits connecting to one counter circuit.
The idea is that the counter should indicate how many activated sensor circuits are ...
1
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1answer
37 views
Confused why outputs of a priority encoder could be X instead of 0 or 1
So this is the truth table given for the Priority Encoder:
and this is its logic diagram:
I am extremely confused with the part where the outputs x and ...
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3answers
109 views
How is something level trigger vs edge triggered? [duplicate]
I understand what they both are, but how exactly is something "made" to be edge triggered? I understand some computer architecture concepts, and while I understand individual components (gates/flip ...
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0answers
56 views
Logic-based light system
I need to develop a system that turns on the red light when all three switches are off, and turns on the orange light when any two out of three switches are off. The red light part is already sorted ...
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1answer
59 views
Pull-down resistors on logic gate and decoder inputs?
I'm designing a very basic circuit for testing a switch sequence. I'm using a CMOS decoder CD4028B (link to datasheet) and XOR gate (CD74HC86E - link to datasheet). Reading the switch sequence is ...
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1answer
54 views
Digital Logic: What are “hamming code” and “Binary code” state machines?
I'm asked to draw the circuit for a state machine in one hot, hamming code and binary code models. I know what is one hot state machine, but i'm not sure what are the other 2. Google also didn't help. ...
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2answers
58 views
How to differentiate between multiple different connections connecting to a common socket?
I'm working on a project that involves 9 female connections on the top of a box, and 4 male connections coming from the front of the box. The requirements of the project involves connecting these male ...
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0answers
14 views
How to understand coefficients of Jakes' channel?
I've been reading materials covering Rayleigh fading channel. One of the simulation methods is to generate coefficients \$[h(0), h(1), h(2), ..., h(n), ...]\$ using Jakes' model.
I am having a ...
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1answer
104 views
Vivado simulation stuck at 0 fs
I am trying to simulate a D flip flop using Vivado 2018.2.2.
But upon running the simulation a window pops up stating Current time: 0 fs. The program doesn't freeze, it just doesn't progress. Here is ...
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1answer
53 views
Reimplement circuit using 1 2x4 decoder and 2 logic gates
I am a Computer Science undergraduate taking a module on Computer Organisation. There is this typical circuit design question that always appear in my assignment and I'm not sure what is the standard ...
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1answer
38 views
7 Segment Display Segment C Kmap Confusion
I am working on the Kmap for the Segment C on the 7 Segment Display.
The list of numbers that light up the 7 segment displays segment C are as follows:
The Kmap I came up with, without grouping yet, ...
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0answers
24 views
Calculating Hold time for a lenient latch
Hold time is the difference between the TGQ and Tpd to be 3ns-2ns=1ns as
for example if input changed after G by 1.5ns so G takes 3 ns to propagate to Q and the input takes 2ns of AND&OR gates ...
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3answers
58 views
Verilog router design and best way to handle variable size packets in verilog?
I have a synthesizable Verilog/logical design question. My question is more logical than syntax.
I wish to implement some sort of router that has three input/output ports of full-duplex UART RS232, ...
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1answer
55 views
XOR complement simplification
What is (A⊕B)' simplification?
i know that :
> (A⊕B)=A'B+AB'
but what is the complement of that expression?
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24 views
Confusion regarding working of Petrick's method of generating minimized boolean expression
I was reading about Petrick's method from
http://www.cs.columbia.edu/~cs6861/handouts/quine-mccluskey-handout.pdf. The material stated that before applying Petrick's method the dominating rows and ...
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1answer
52 views
How do I learn-by-practicing digital circuits - MIPS R2000 (or similar) processor or board? [closed]
I already do have a book which I am studying for a university course. I've searched online to buy a development kit for MIPS R2000 (or similar) and have been suggested the MIPS CI20. Don't know if or ...
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1answer
30 views
Implementing a simple logic equation
I need to do a lab that seemed like it was simple, but for some reason i cant get the right output for this function. its G(0)= T1T3'+T5T7'. These are data inputs.. I can only use NAND and NOR gates. ...
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0answers
26 views
Doubt Counter Circuit with FF and MUX
Hello,
I have got some doubts concern this circuit. If I assume q=0 the signal processing on conditional (0==6) is false;
Then the control signal will be 1 so the MUX will choose the second signal (...
