Questions tagged [digital-logic]
Digital electronics treats discrete signals, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.
4,102
questions
0
votes
0
answers
62
views
Looking for inventer and/or name of fast sorting algorithm
Back in 1992, when I was a grad student in the Computer Science and Engineering Department at the University of Washington, my faculty advisor told me of a sorting algorithm that takes as input N ...
2
votes
1
answer
23
views
How to complete the truth table for a JK flip flop? And why?
I saw this question, but am unsure how to solve it. I have tried various approaches and get some of the answers correct, but never all of them...so my method is obviously wrong
For example, what ...
2
votes
2
answers
75
views
Voltage controlled 555 bistable operation
[Updated with working schematic!!!]
I have a circuit which I tried to adapt from the 555 bistable configuration to have the 555 states controlled by input A and B; B always goes high before A.
I am ...
- 23
1
vote
1
answer
34
views
An over- and under-voltage protection system
How can the block diagram below operate as an over and under voltage protection system?
I thought it will work as follows:
A step-down transformer is used to bring down the alternating current supply ...
- 11
0
votes
2
answers
75
views
Logic analyzer gives me much more pulses than expected
Let me start the question by saying that I am using a logic analyzer for the first time, so I am probably doing something wrong.
I sniffed the signal that goes to a speaker. The signal is probably PWM....
- 847
1
vote
3
answers
116
views
+50
Turn on switches sequentially - ONLY ONCE - when triggered
I have some circuits in which I have to give two signals (I mean signals as positive) through push buttons to do some work like latch, and it is the only work of these buttons.
I feel that this should ...
1
vote
1
answer
70
views
Digital input conditioning?
I'm designing a schematic with opto-coupled digital inputs (BNC). For better noise/ground loops immunity/reflections should I add 50 ohm resistors on both input lines, signal(+) and GND, along a ...
- 51
0
votes
0
answers
38
views
Instrumentation box, digital input signal conditioning [duplicate]
I'm designing an instrumentation box with opto-coupled digital inputs (BNC). For better noise/ground loops immunity/signal reflections I added 50 ohm resistors and 1n filtering capacitor (if needed). ...
- 51
0
votes
0
answers
45
views
How is a robust test also a non-robust test?
I found the last line of this slide quite confusing. How is a robust test also a non-robust test? Can anyone elaborate?
Using path sensitization and any other criteria, I am not able to relate both of ...
0
votes
0
answers
59
views
NAND gate output doesn't change to logic 1 when expected
I've been assigned to make a breadboard from a circuit and then take its NAND implementation and build that on the breadboard.
Logically what I've done seems to me like it should work. Essentially ...
0
votes
0
answers
52
views
Minimizing number of logic gates
For a boolean function, after drawing K-map we got that function in the form of the sum of products (minimal representation) but problem is that when we implement that minimal representation we use ...
- 69
0
votes
0
answers
39
views
7-segment display decoder truth table
I am trying to make a decoder that can display all alphabetical letters on a 7-segment display. My inputs are ABCDE and the outputs are abcdefg
Is this the correct truth table for a circuit? If yes, ...
1
vote
0
answers
35
views
Clear D Flip Flop when FF input is not equal to 1
I am trying to implement magnitude comparators with storage as a D FF. In this picture, if X is equal to 0, second AND gate on magnitude comparator (that comparator in rectangle) will give 1, as Q' &...
- 11
1
vote
2
answers
46
views
Contradictory information in current capability of open drain output for the MAX7317 IO expander
I am looking at the datasheet of the MAX7317 IO expander and it is not clear to me if it can drive simultaneously 8 pins when each pin sinks 16mA. I don't have a lot of options because I need SPI.
The ...
- 1,080
0
votes
1
answer
63
views
CD4053B Triple 2:1 MUX/DEMUX For Switching Three LED Channels To Multiple Zones
My last post (Multi-Zone Addressable RGB+CCT LED Mode Switching) got closed as off-topic because I was “seeking recommendations for a specific product”... I found on my own what I believe to be the ...
- 1
0
votes
1
answer
67
views
When should we switch from an internal FPGA oscillator to an external one?
I'm about to design a 5Mbps UART on a ICE40U0-5k and I've got a hunch I'll need an external oscillator when I spin my own board after I'm done with the dev board, but I would like to know how I can ...
- 1,080
3
votes
2
answers
57
views
Can a register remove the race condition in this case?
My book has this example of a race condtion:
The race condition is: If D and CLK is 1, and CLK goes to zero, then we want the output Q to remain 1, however if the inverter is slow compared to the ...
- 141
-1
votes
1
answer
54
views
Mosfet circuit-function
Hello,
I am doing digital electronics and I have never seen this notation 5o define a function. Can someone explain me with details what happens when CLK is 1 please
Thank you
- 7
0
votes
1
answer
49
views
How will I implement this function with decoder and multiplexer? [closed]
Inputs Output
A B F
0 0 C.D
0 1 C
1 0 C+D
1 1 C XOR D
According to the logic input-output relations
a-) Find the ...
0
votes
1
answer
82
views
Advantages of using 2 NPN transistor NOT gate
Is there any benefit using 2 NPN transistors for a NOT gate rather than one NPN transistor?
- 31
0
votes
2
answers
82
views
What TTL circuit should I use for an SRAM cell
I am trying to build a 16 byte RAM module with only bjt transistors and resistors. And I am looking for a suitable circuit for a memory cell.
From what I have understood there are two paths I can take:...
- 39
2
votes
1
answer
73
views
Correct way of estimating delays in FPGAs
What is the correct way of estimating delays when doing operations in Verilog?
For example:
reg [31:0] a, b;
...
wire [31:0] res;
assing res = a + b;
The above <...
- 913
1
vote
1
answer
43
views
Hamming code error correction multiple bits
If we send a message from a sender and the noisy channel produces 2 bits with error can we detect both bits using hamming code or is it just for 1 bit?
- 467
0
votes
2
answers
92
views
How can I combine 4 separate bits into one 4 bit output?
Say I hypothetically have four switches 0-3. I want each switch to represent a bit in a four bit long number, switch 0 being the first bit and switch 3 being the last. The end goal is to be able to ...
- 11
0
votes
5
answers
126
views
How does a ring oscillator get voltage?
I am reading a book about digital design, and I came across the ring oscillator:
What I do not understand is where does it get a voltage from if there is no input? How can it then oscillate?
- 141
0
votes
1
answer
53
views
Difference between waveform and truth table [closed]
Is there a difference between waveform and truth table to represent the values of a circuit?
For example:
Are there particular cases where one or the other should be used?
2
votes
1
answer
46
views
Parallel several inputs of a multi-input gate
Often I see the following circuit (example 1.), e.g. using an additional gate of an NAND gate to invert a signal when using only one 74xx00 CMOS IC with 4 x 2-NAND gates:
simulate this circuit –...
- 501
2
votes
3
answers
120
views
Unidirectional level shifter 1.8-5V -> 3.3V
I'm looking for a circuit/IC to shift logic levels between 1.8/3.3/5V and 3.3V.
This is to connect various devices via UART to the ESP8266. As such, I only need unidirectional translation - the ...
- 23
-1
votes
1
answer
47
views
Why is gate fanout calculated like that for general gate?
In the given example I am currently struggling to understand why the fanout of each gate is equal to the ratio of the size of this gate to the previous gate.
In a simple chain of inverters, the fan ...
2
votes
1
answer
143
views
What's the difference between these two logic diagrams?
I have these two xor logic diagrams, they seem to work the same on inputs which are not even, but what is the difference between them? What is the purpose of it and which one would be faster?
- 137
2
votes
1
answer
128
views
74HC74D initial output value after power up
I use a touch sensor (Active Low) to light up a light bulb. here I've used a 74HC74D D flip flop to turn on an off the bulb with the sensor pulse (sensor output is active low which is then converted ...
0
votes
0
answers
41
views
TinkerCAD 7-Segment Display Not Showing on Simulation
I am only on my 5th week trying out TinkerCAD for our Logic Circuits course. We are tasked to create a 7-Segment Display Using Logic Gates only. I did all the boolean expressions needed for each ...
-1
votes
0
answers
39
views
How to design the circuit such that it automatically stops when the input to the circuit matches the output to the circuit?
I have designed circuit of PISO(Parallel in serial Out) having LED in inputs. I needed to show the LEDs same as input and automatically stop when the inputs and outputs are same. So i also added ...
- 1
0
votes
0
answers
43
views
Making a 2 digit passcode circuit with a 3*3 matrix keyboard
I have been trying to make a 2 digit passcode circuit with a predefined code (80) with a maximum of attempts of 3, the code is entered by a 3*3 matrix number keyboard. I'm using the 74HC147 as matrix ...
1
vote
1
answer
43
views
How can one pass values to a bus in Verilog without first making a wrapper bus?
I have just defined an SR flip flop, and I need to now define a D flip flop. I am going about this by using an SR flip flop within my D flip flop. However, because I used a bus for my S and R inputs ...
- 35
0
votes
0
answers
30
views
Analog to digital conversion for neural network weights
I am a machine learning researcher, and lately I am getting interested in neural networks trained on analog hardware. However, I have some doubts about their potential, probably because I am missing ...
- 101
0
votes
0
answers
34
views
FIR filter implementation porblem
I want to know how( z^-1) delay unit can be implemented in digital circuits or how can be implemented in VLSI system using("VHDL")
1
vote
1
answer
93
views
What drives an input from 0 to 1 inside of a digital circuit?
Inside of a digital circuit, like a computer, what is acting as the switch that drives the inputs or internal values from 0 to 1, and how does this work? Like in instructions for a computer, how are ...
-1
votes
2
answers
72
views
How do you go from gate level to transistor level?
Is there a good method to go from circuit at gate level or truth table to transistor level, other than trial and error?
I have an example here to illustate what I am asking.
We have the function \$X=(...
0
votes
0
answers
66
views
High Voltage & Low Voltage PCB Design
I am trying to make a PCB that acts as a "Raspberry PI HAT" and allows me to connect the raspberry to different sensors. Specifically, I'm having difficulties in defining the design rules ...
2
votes
3
answers
89
views
What is the best way to make an inverter from a NAND or NOR?
As stated in this answer, there are two ways to make an inverter out of a NAND gate, and similarly for NOR:
Connect the signal to both inputs.
Connect the signal to one of the inputs, and the other ...
- 121
1
vote
1
answer
78
views
iCE40LP1K FPGA - Performing an analog to digital function (Power monitoring) without an ADC
I'm using iCE40LP1K FPGA and I wanted to create a block that is responsible for doing a fast power down of all devices on the platform when the 12V is shut down due to powercut.
Whcih means, when 12V ...
- 533
1
vote
2
answers
70
views
Falstad Circuit not running
I created this Falstad circuit that is supposed to run to toggle between the 3 circuits to power the LED. The top AND gate leads to a circuit that makes a strobe light effect. The second is supposed ...
- 11
1
vote
0
answers
74
views
Amplitude modulation on FPGA
I'm trying to implement amplitude modulation on a Xilinx Vivado using Verilog HDL, but can't seem to get the proper output. Can anyone point out what I am doing wrong?
This is in reference to my last ...
0
votes
0
answers
36
views
Clock diagram schematic symbol [duplicate]
I am not familiar with the schematic symbols outlined in the above digital clock diagram.
I gather it indicates an on / off switching connection of crystals "EXTAL" and / or "XTAL" ...
- 387
1
vote
1
answer
49
views
Level shifting of a 3 state pin
I want to design a simple battery charger using MCP73831/2. This chip has a 3-State state pin according to the table below:
I have a 3.3V MCU and I want to connect this pin to a GPIO. The MCU is not ...
- 555
0
votes
1
answer
94
views
What is the maximum number of inputs to a logic gate that is being used in computing hardware these days?
I was referring to this question, but I had a confusion due to the concept of programmable logic devices. Image from UW page 7. Here the OR section can have up to 8 inputs to it. I'm confused about ...
- 377
1
vote
1
answer
53
views
create_generated_clock quartus for derived clock
I am working in a design that creates a 1Hz clock from 20MHz PLL out.
For that purpose, I have created a counter that switches its out when its value arrives to 10 000 000.
That 1Hz clock is used as ...
- 41
0
votes
2
answers
68
views
Logic gates propagation delay
I'm studying digital circuits and I have a question about the propagation delay of a logic gates. I've read that propagation delay is defined as the time required for the output to reach 50% of its ...
- 103
1
vote
0
answers
40
views
How to determine if a gate/inverter can drive a fanout of 4 gates?
I have a circuit in which a driving inverter output (Fanout of 4) with equal Wn Wp sizing (m=4) is driving 4 other gates having same equal Wn Wp sizing (m=1). How to calculate if the inverter fanout ...
