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Questions tagged [digital-logic]

Digital electronics treats discrete signals, unlike analog electronics which treats continuous signals. Digital logic is used to perform arithmetic operations with electric signals and constitutes the base for building CPUs.

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Reference for synthesizable loops in Systemverilog

I am looking for practical examples (and hopefully an explanation) about loop constructs in Systemverilog (for, while, do-while, repeat, etc.) done for synthesis of digital modules, not for ...
Jacob Morales Gonzalez's user avatar
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46 views

How to output quasi-analog sine wave using microcontroller DAC [closed]

I'm using a dsPIC33f microcontroller that has a audio 16-bit DAC module. I'm interested in outputting a sine wave look-up table using one of the pins so that I can see the the waveform on the ...
Nobody Else's user avatar
-1 votes
0 answers
75 views

Why is demux in electronic circuits rare compared to mux? [closed]

Whenever I see a circuit diagram of a circuit like CPU, FPGA etc. there is no demux but there are always decoders or muxes. Are there any examples of selecting output lines using demux in a large ...
MaGNuM's user avatar
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Using 1.8V digital signals with TPS281C100A and AP22653A

I plan to use the following two devices: AP22653A and TPS281C100A and drive the enable pin from 1.8V logic. They are specified for minimum 3V3 operation, but for both inputs the VIH is 1.5V. Would ...
Cez Chi's user avatar
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-1 votes
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multiplier with 2 binary inputs x and y, each input 3 bits, with 5 outputs [closed]

multiplier with 2 binary inputs x and y, each input 3 bits, with 5 outputs can someone show me how it should look in Multisim I tried to do it but couldn`t do it BTW IM new to Multisim and the Digital ...
4yow Faris's user avatar
3 votes
4 answers
248 views

Is the resistor between the clock and the NPN needed?

I have a circuit that uses an NPN transistor inverter to invert a clock signal. The circuit calls for two resistors, a pull up and one in between the input signal. Virtually all of the circuits found ...
Zackery Fleming's user avatar
1 vote
1 answer
31 views

Voltage input low of nmos inverter with enhancement load

I have the following schematic in LTSPICE For each of these circuits I have to find the values for the VOH, VOL, VIL and VIH. To find the input voltages I observe the derivative of the V_out_NMOS ...
S214ky's user avatar
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How do i write my synopsis design constraint(sdc) for a generated clock with a variable frequency?

Here is what I got so far for my SDC: create_clock -name clk -period 20 -waveform {1.7 19} This is the part of my verilog code that derives a variable frequency ...
Mister Moron's user avatar
2 votes
1 answer
53 views

Multiplexer with transmission gates

I have a multiplexer with 2 selection bits (S0 and S1), 4 inputs (x0, x1, x2, x3) and 1 output (y). The truth table for this circuit is the following: S1 S0 y 0 0 x0 0 1 x1 1 0 x2 1 1 x3 I also ...
S214ky's user avatar
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1 answer
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Voltage drop in NMOS inverter with enhancement load

In the enhancement load NMOS inverter, why is the voltage drop across M2 at least equal to Vth when VIN is low ? Is it because for M2 when VIN is low the voltages VGS = VDS, so VDS > VGS - Vth and ...
S214ky's user avatar
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-3 votes
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Whats the error?

I'm trying to make a counter but Vivado display an error, and I cannot see what's the problem. As far as I know the design is correct. Someone can tell if I'm missing something, please.
A. V.'s user avatar
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2 answers
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Why isn't the CLK input manipulated directly in flip flops?

In Ben Eater's video he uses a circuit below to create a D-Flip-Flop with a LOAD pin. From my understanding, the circuit makes it so that the flip flop only loads in D1 or input when LOAD is high, ...
Mahad's user avatar
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5 votes
2 answers
156 views

Well protected digital input with long wires

I've created simple circuit to protect MCU's digital input against eg. induced spikes. I want to connect quite long wires to this HW and highly probable that this board will be placed close to the ...
szymo092's user avatar
1 vote
3 answers
64 views

Output Variable stays unintialised in my VHDL testbench

I am pretty new to VHDL and was trying to write a VHDL simulation for a simple master-slave toggle flip flop. Following is the VHDL code that I have written: ...
Rohan's user avatar
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Valid/Ready based streaming interface: Should control signals be registered?

There are variants of the control signals of streaming interfaces but basically there are two signals. One from the source is usually called valid. One from the ...
quantum231's user avatar
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A good rising edge D Flip Flop CMOS implementation

I'm currently trying to create a basic CPU with SOT32 CMOS transistors. I have made a good design and architecture and began testing and ordering PCB's. However, I found that there are a lot of rising ...
MathijssY Klaver's user avatar
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2 answers
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Start counting from 1 and go up to 9 | 7-segment Display

so I have this circuit in Falstad that counts up to 9 (from 0 to 9) but I need to it to count from 1 to 9. In falstad I am using a counter, 7 segment decoder and a 7 segment display. Any thoughts on ...
Albii's user avatar
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-1 votes
0 answers
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How exactly do we make transistors behave like logic gates? [duplicate]

From what I gather, CPUs are pretty much a collection of transistors which do logic and calculations in the forms of flip-flops, ALUs, registers and such. But if a transistor is just a semi-conductor, ...
WaveCave's user avatar
1 vote
1 answer
49 views

Verilog set bit counter

I'm trying to create a Verilog program that would display the digit with greater number of bits set. The code is working. However, it counts the bits from the previous values instead of its current ...
Paula Bianca Pascual's user avatar
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Identifying unmarked IC in CNC controller board

I have a Camxtool v3.5 CNC controller (similar to this, although this is v3.4) that has an unmarked IC that I haven't been able to identify: The IC is connected between pin PB3 of the ATmega328P (...
puq_87's user avatar
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ADC(MC3208) Interface Circuit Design

I am currently designing a Multi-ADC PCB for use different sensors, I've researched a range of different sources and would like some clarification on a few things before I finalise my design. I am ...
NDougall32's user avatar
1 vote
1 answer
70 views

How to Resolve LINT-1 Warning During Synthesis?

I am currently working on the synthesis stage of a hardware design project and encountering a specific warning from the LINT-1. I'm seeking assistance to resolve this issue. Tool: design compiler ...
강영완's user avatar
1 vote
1 answer
39 views

Synthesis with Verilog Parameter AUDIO_DW = 32 Results in LINT-1 Warning

I'm working on a Verilog project and encountering a warning during synthesis. When I set the parameter AUDIO_DW = 32, I get a ...
강영완's user avatar
2 votes
2 answers
63 views

Passing Matrices (larger arrays) between modules

I'm trying to have my design be more compartmentalized and separate each task into different modules/source files. I basically want to pass a matrix and a vector into a module I created where I'll do ...
Samuel's user avatar
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2 votes
3 answers
117 views

ARM Cortex-M Processor Reset Behavior

I am trying to understand the ARM cortex-M hardware behavior on reset; particularly how the SP and PC values are written upon a cold start or hard reset. A quick search did find a few similar ...
NeedToKnow's user avatar
0 votes
1 answer
54 views

How to implement the Instruction Set in Logisim

I have an assignment that requires me to build an 7-bit CPU. I’m done with implementing some of the requirements that includes 4 8-bit registers (the requirements say I have to store the parity bit), ...
maira's user avatar
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2 votes
2 answers
70 views

Please help me with my verilog code for processor (extension)

This is an extension to my previous question. I am an undergraduate student and am new to Verilog. I am writing Verilog code which simulates a processor along with registerFiles and memory (...
Damstridium's user avatar
1 vote
1 answer
82 views

Can someone help me with this Verilog code for a processor?

I am an undergraduate student and am new to Verilog. I am writing Verilog code which simulates a processor along with registerFiles and memory (instruction + data memory). Here is the instruction ...
Damstridium's user avatar
1 vote
1 answer
62 views

Error while building a MIPS ALU Controller Design

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Zelda's user avatar
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2 answers
66 views

What does Vdd and Voh mean?

I truly apologize if this question title is vague I don’t really know entirely what to ask. I’m a programmer interested in computer architecture and I’ve been reading a book about digital design. ...
mox's user avatar
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1 vote
2 answers
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Is a state machine with a register for return state a good design choice?

I want to design a state machine for one module that has to communicate with another module via a protocol. Multiple states need might end up needing to communicate, State A, State B, State C. they ...
Weijie Chen's user avatar
1 vote
1 answer
87 views

Driving 5 and 3.3 V square wave from a single terminal

I'm quite new to the topic and for fun I'm building a low frequency square wave generator with parts I currently have. Overall it works just fine while built on a breadboard, however I would like to ...
Maxim Pavlov's user avatar
0 votes
2 answers
57 views

3 Phase Pulse Generator

I cobbled together a simple 3 phase pulse generator for a project I am working on. I've attached a picture of the circuit. I need to get a quick (~50ns) pulse on each phase. I have concerns about the ...
Brian's user avatar
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2 votes
2 answers
547 views

Can I cascade two different shift register?

I would like to drive multiple nixie tubes using shift register. I wonder that can I cascade two different shift registers to control them using arduino or another MCU? My plan is to connect DATA OUT ...
enis's user avatar
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0 votes
2 answers
43 views

Will the frequency change when converting the ESP32 3.3 V logic to 5 V logic using a TXS0108E?

The GPIO on ESP32 (S3) are all 3.3 V logic. I want to control an ESC for a drone. The manufacturer says: The ESC will use a standard 5 V PWM signal at 50 Hz between 1100 µs and 1950 µs. 3.3 V output ...
ferer's user avatar
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1 vote
1 answer
78 views

Single-Digit BCD Adder

I have this code written in SystemVerilog. The module bcdadd1 is supposed to take in two 4-bit inputs A and B and a logic input carryin (...
David's user avatar
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0 votes
1 answer
60 views

A confusion with logic level output description

Following shows the difference between TTL and 5V-CMOS logic: If a device manual states it has TTL input I can say that one can expect 3V pulse can work as input. But my confusion is, what does it ...
cm64's user avatar
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0 votes
0 answers
24 views

203045/break-before-make-spdt-relay-out-of-2-spst-relays

I have question concerning: "make before break" relay instead of the posting "break before make" relay. (see post 203045 originally drawn with IC 74HC02 Quadruple 2-Input Positive-...
Holz1's user avatar
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0 votes
0 answers
61 views

Single Switch with Momentary and Latching/Hold Properties Using CMOS/Logic (no µP/microprocessor)

I am looking for a CMOS/logic based solution (no µP/microprocessor) to a momentary switching scheme I'd like to implement that involves the following scenario: 1: pressing a momentary switch engages ...
paraparabolic's user avatar
0 votes
1 answer
54 views

dual power supply - digital line current limiting

I am connecting the transceiver chip to the PIC16 MCU and is going to power them from different switching power supplies, originating at same power source. Both power supplies output 3.3V, thus ...
Anonymous's user avatar
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0 votes
1 answer
55 views

Power bank 4s voltage monitoring using cd4052

i working on pcb with a 18 volt dc like circuit below . I have a question about driving logic A and B of cd4052 with my esp32 do my circuit is correct. Do I need extra component between Drain of the ...
Khales Naim's user avatar
1 vote
1 answer
50 views

Getting HiZ for my output for a 5 to 1 mux

I'm having trouble with Verilog code for a 5 to 1 MUX. ...
Michael's user avatar
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2 votes
1 answer
68 views

D latch module in VHDL using NAND structure [closed]

What is the difference between a positive-level D latch and a negative-level D latch? How to create positive and negative D latch in VHDL using NAND structure? Can you share some example codes for ...
Serkan Kaya's user avatar
2 votes
1 answer
65 views

IC 74HC08 can the output drive the input without destroying it? [closed]

i made a circuit with a 74HC08 and i wanted that when the output is high(1Y) it would take over contact (1B) with a led between it .and the input B connected to ground with a 20K resistor it works ...
jokertje1's user avatar
0 votes
0 answers
48 views

SLF3S-4000B not recognised by Arduino Uno R3

I have a Sensirion SLF3S-4000B connected to SDA/SCL lines of the Arduino uno through a logic level shifter (connected like in this example: https://learn.sparkfun.com/tutorials/retired---using-the-...
CadeO01's user avatar
0 votes
1 answer
63 views

Why am I getting error C:\Program Files (x86)\iverilog\bin\iverilog.exe: unknown option -- O when trying to run this Verilog code?

On Visual Studio, I run this Verilog simulation command, but I get the error message: ...
Ahmed Sweillam's user avatar
0 votes
0 answers
33 views

Can the SOP expression be the same as POS expression?

I have a function as F(A,B,C,D)=M0+M4+M12+M8 I'm getting the simplified Product of Sum expression as C+D but I'm getting the same expression again as Sum of product
Taiba Sharif's user avatar
2 votes
6 answers
2k views

What can be done with all of the extra address lines in a ROM? Why were they designed to have so few outputs compared to possible inputs?

I am a student in an introductory Digital Logic and Computer Systems course. We have been learning about ROMS, but often we just use them to basically just map truth tables onto them. We have been ...
LeBronJames's user avatar
0 votes
1 answer
37 views

JK flip flop timing diagram

Is this JK flip flop timing diagram for the Q output correct? I just want to make sure I didn't mess anything up.
JP NICOSIA's user avatar
0 votes
1 answer
70 views

AND gate example

When I closed switch 1, I apply 9 V to input 1 of the AND gate, but there is a resistor here. Can I be sure that the total 9 volts does not drop through the resistor? Why is the voltage dropped across ...
Serkan Kaya's user avatar

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