Questions tagged [digital-logic]
Digital electronics treats discrete signals, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.
2
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1answer
54 views
What is the least expensive way to build a three-bit shift register?
I'd like to build a queue of three internal bits as inexpensively as possible. Externally, the queue has two input bits and one output bit. The inputs are (dataIn) and (shift), and the output is (...
0
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2answers
56 views
Storage structure in RAM
Lets say we had to execute an instruction stored in RAM
The instruction stored at address 0000 decodes to LOAD_DATA_15_A
LOAD the data at address 15 in RAM to the register A
Would there be any ...
1
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0answers
39 views
Voltage Across NMOS and PMOS Transistors
So I have the question above concerning an NMOS and PMOS transistor. The goal is to find V1 and V2 in steady state. My understanding is that because the gate voltages of zero and Vdd are there, the ...
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1answer
18 views
how do you use an enabled decoder as a multiplexer?
how do you use an enabled decoder as a multiplexer with an AND gate?
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0answers
26 views
Creating coder of MFM linear code (Miller) using logic gates
I have a problem with the implementation of my MFM encoder using logic gates (in the CEDAR program). It's not working correctly, and I don't know if this is software problem, or if I'm doing something ...
0
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0answers
45 views
Priority Encoder with Memory
I am looking for some kind of pin channel selector design for 16 signals, 0-5V. When a specific signal got high, I should get its number (address) over a 4 pins address. No simultaneous highs will ...
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0answers
25 views
MOD 16 counter with adjustable MOD [on hold]
Is it possible to design a counter where the user can choose the MOD? The maximum that can be selected is 16.
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3answers
78 views
7432 behaves like an AND gate & 7408 behaves like an OR gate
Ok. First of all, I'm an absolute beginner about IC and circuits.
If you will view the pictures, you will notice that the 7432 behaves like an AND gate and the 7408 behaves like an OR gate.
PS. I ...
0
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0answers
22 views
SRAM reading and restoring value [closed]
I have attached an image of a memory array SRAM, during a read operation, the bit lines are pre charged and the wordlines are enabled.
The sensing amplifier calculates difference between bitline and ...
0
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2answers
36 views
Full Adder Circuit
This circuit is based around the SN74HC283 4 bit full adder.
What purpose does the resistor network serve?
Will this circuit work without any resistors, i.e. using raw inputs and outputs?
...
0
votes
1answer
51 views
Does logic shifter works on analog signals?
I am using a 5V sensors (MQX Gas Sensors) that is connected to an RPi. This sensor is then connected to an ADC converter then to a logic level shifter. I just followed the tutorial I saw on the ...
0
votes
1answer
33 views
Reading memory array
im new to memory cells.
I have taken the below image from a video, i wanted to ask in the video he explains that the MUX can select 8 bits, but how is this even possible?
The output of a MUX is always ...
0
votes
0answers
29 views
6 bit subtractor [closed]
So I built a 6 bit to 6 bit subtractor using 7404, 7408, 7432, and 7486 ICs on a breadboard. But my problem is I can't get the right output using the 6 pin dipswitch. I think the problem is with the ...
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0answers
32 views
Can I use OR gate or AND gate in a full adder?
What will happen if I replace AND or OR gate, rather than using an XOR gate? In this picture the solution is the table.
If I change XOR gate and put AND or OR gate, what will be the function for DEC ...
0
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0answers
21 views
Transceiver IC SN74LV245A at different voltage levels pull up resistor require for current improvement
I've gone through datasheet of IC Page number 12 Figure 5 shows typical application of IC which is 5 to 3.3V compatibility.
In my design My sensor Output is 1.5V to 2.2V so we're planning to have ...
0
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0answers
36 views
Sense amplifier in memory [duplicate]
What is the functioning of a sense amplifier?
Does it take 2 inputs and calculate which is higher or lower, then output a signal?
I have come across this in S RAM
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1answer
38 views
Writing and reading from and to SRAM memory [on hold]
im just learning SRAM.
I wanted to ask, consider the 4x4 memory cell array below
If i wanted to select a word line or row, would the row decoder be a 4x1 multiplexer where each wordline is connected ...
0
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0answers
52 views
Is this a specific logic function?
I mean it this fits a logic function or its the way its reduced only.
This is the truth table
\begin{array}{|c|c|c|c|}
\hline
A & B & C & V\\ \hline
\hline
\hline
0 & 0 & 0 & ...
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0answers
39 views
4 bit to 4 bit subtractor logic gates problem
I'm trying to create a 4 bit by 4 bit subtractor here but I get wrong output. In the picture it shows that 0000-1111=10001 which should be 0000-1111=11111. Please help me.
By the way the rightmost IC ...
3
votes
3answers
88 views
Are bipolar logic familes like ECL/CML used currently for radiation hardened computing devices?
According to this
article, even though it's 30 years old, ECL is more radiation resistant than normal CMOS chips by a factor of 1000. It is also less susceptible to DPA side-channel attacks. So in ...
0
votes
2answers
75 views
How can I execute multiple for loops sequentially in Verilog?
I'm trying to turn on the LED lights on my FPGA Spartan board one at a time until all lights are on and then turn them off in the reverse order. I could easily do this in other OOP languages by making ...
0
votes
2answers
35 views
JK flip flop integrated circuit (7473) toggle malfunction
I built a state machine using JK flip flops, I tested it but I kept getting seemingly random results. I decided to test each jk flip flop individually.
Here is the schematic for my testing:
simulate ...
1
vote
2answers
42 views
Spike in RTL Inverter
I do not understand the cause of this spike which can be observed in an RTL inverter (but also in a CMOS inverter). In the following image it is the peak at 10 mS (I have considered as input a signal ...
-1
votes
1answer
24 views
Active SR latch output conditons
For the active high SR latch, is there anyway to predict which combination the outputs will be when S=0 and R=0?
For example,
Q = 1, Q'= 0
OR
Q = 0, Q' = 1
0
votes
1answer
43 views
This SR latch built with 180nm CMOS does not work in ltspice. How do I fix its behavior and parameters?
EDIT: I copied over the latch from another larger model that had Vdd defined, but missed it when copying over the design. However, after adding in Vdd, I still run into this confusing issue where the ...
2
votes
1answer
160 views
Repairing old computer, randomly reboots due to something is wrong with “reset” circuitry
I'm working on a TRS-80 Model 100.
Not long ago, I have done some capacitor repairs after experiencing random reboots. I've skimmed through some online manuals, and it seems that somewhere in the ...
9
votes
4answers
889 views
How is it possible to drive VGA displays at such high pixel clock frequencies?
I'm working on a digital circuit using discrete components to drive a 640x480 VGA display in a 80x30 text mode.
For a 640x480 display, the pixel clock is 25.175MHz, which has a period around 40ns. I ...
0
votes
0answers
34 views
Reading Digital and Analog Signal from Different Sources with Arduino
I am using an Arduino to read signals from 2 different devices. (This is an automotive project so all 3 are powered by the 12v battery of the car).
The signal from one of the devices is a digital ...
0
votes
1answer
31 views
Error with reference to scalar wire 'reset' is not a legal reg or variable lvalue
I'm getting an error in Verilog with an input parameter it's not recognized as a legal reg or a variable lvalue. I had the same problem with the output in the module however it was fixed by labeling ...
0
votes
4answers
76 views
Why logic low Inputs to a logic gate need to be grounded
For example if we take a 2 input AND gate . And want to apply 0 and 1 to the input terminals ..one terminal will be connected to a voltage source . But the other terminal where logic 0 is to be given ,...
0
votes
1answer
63 views
BCD code Detector
So basically I'm trying to design the circuit for a BCD code detector which should have 4 inputs and gives an output of 1 if the equivalent decimal is 0<=input<=9.
Else, it should give zero.
...
0
votes
4answers
85 views
TTL Logic for displaying large 7-segment values [closed]
For fun, I was trying to imagine how I might implement large values in 74 series logic (or any commonly available discrete logic from the 1970s). An example might be displaying prime numbers up to ...
0
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0answers
48 views
Building a 6-inputs XOR gate with only 12 AND/OR gates
I would like to compute a 6-input XOR gate with only 12 AND/OR gates, any number of inverters can be used. I failed to find any optimization with the K-map and so far I can only decompose it with 13 ...
1
vote
0answers
50 views
Laser Tag System Design Review
I have been working on a project to make my own laser tag gins and sensor vests.
I have completed the electrical side of my design but this is the first time I have designed something like this and ...
0
votes
2answers
80 views
How much time does it take to increment one bit in Verilog? [closed]
In my lab I'm supposed to write a program in Verilog that makes a timer which outputs a tick every second. A counter module could be used such that as the counter increments to a specific binary ...
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votes
2answers
52 views
What is the purpose of this statement in Verilog?
I see syntax quit similar to this very frequently:
4'd0
Sometimes it is associated with an assign statement:
assign S0 = 2'b00;
I tried searching online however I could not find any sources.
0
votes
1answer
53 views
Micro controller clock speed requirement for delay measurement
I am trying to measure the absolute time between two 1Hz clocks (GPS PPS events) to within 50 nanoseconds. I do not necessarily care which clock occurs first, I am only looking for the delta T between ...
0
votes
1answer
288 views
Help Me simplify: C*(A+B) + ~A*B
I know the answer is AC + ~AB, but how?
I have tried:
B(~A+C) + AC and stop.
Also, I have tried:
...
0
votes
0answers
61 views
Frequency multiplier from kHz to MHz
I'm not familiar with electronics at all, and would like to get some ideas
to implement frequency multiplication of LVCMOS.
I want to multiply the frequency in the range of 250 kHz by a factor of 10 ...
3
votes
2answers
754 views
Odd 74HCT1G125 behaviour
I am using a 74HCT1G125 buffer as an '5 V output driver', but, in some cases it has a 12 V, low impedance source presented at its output pin (but in these cases its enable is false, i.e the ...
0
votes
1answer
57 views
Two input nand gates and inverters to sum three products
I am trying to draw the logic gate of the following function using only two input nand gates and inverters A'C'D+AC'D'+AB'. So far I am stuck on trying create the AC'D' part. What I have drawn below ...
1
vote
1answer
27 views
Using individually addressable 8806 LED as digital output
I plan to drive 4 relays from an ESP8266, which already have some pins used for temperature and wind sensors, so I'm a little low on pins.
I've been searching for 1-wire digital output (DS2408) as ...
0
votes
0answers
33 views
1-bit maximum selector (iterative design)
I'm trying to create a 1-bit maximum value selector with an iterative design that can solve larger problems. I understand that I go from the most significant bit (MSB) to the least significant (LSB), ...
0
votes
2answers
50 views
percision timing ratio of multiple lights blinking with different durations and intervals
I'm learning a lot of this as I go, my background is mostly in programming. I'm trying to setup a timing circuit for two sets of lights going into a model, and am trying to determine the best way to ...
1
vote
1answer
43 views
Using NMOS or PMOS for voltage controlled switch?
If I want to use an NMOS or PMOS as a voltage controlled switch, when would I know to use one over the other? I know a PMOS activates with a LOW at the gate and for an NMOS when HIGH at the gate, but ...
0
votes
3answers
44 views
TTL square wave inverter adjustable duty cycle
I am an amateur and I don't have experience with logic circuits so please forgive me if this is very simple.
I have a 5V TTL crystal oscillator (4-pin). I need to create a second square wave from it ...
0
votes
1answer
40 views
Is correct to apply the next boolean algebra rule?
Im trying to simplify the next boolean term
\$E(A\bar{B}+C\bar{E})+\bar{E}(\bar{A}B+\bar{C}E)\$
in this way
\$A\bar{B}E+CE\bar{E}+\bar{A}B\bar{E}+\bar{C}E\bar{E}\$
\$A\bar{B}E+\bar{A}B\bar{E}\$
...
0
votes
2answers
67 views
Help with designing falling edge detector using a state machine
Using a state machine, I designed a circuit that detects the falling edge of a signal (working with positive edge clock), but my circuit has one more not gate than the circuit shown in this document:
...
24
votes
5answers
4k views
Why does a single AND gate need 60 transistors?
Looking at the datasheet for the MC74VHC1G08, under the features section, it states Chip Complexity: FETs = 62.
Why does this IC need 62 transistors, while an AND ...
0
votes
1answer
46 views
Circuit MOSFET Pulldown Circuitry
Now, I have already made some progress, I have figured out what the W/L should be and made most of the circuit. Though I am not sure how I should put the MOSFETs ...
