Questions tagged [digital-logic]

Digital electronics treats discrete signals, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.

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Identifying Protocol Using a Logic Analyzer

I used a logic analyzer to read the data line from a small camera battery and would like to understand the authentication my camera is doing to the battery over the one data line. Is there any way to ...
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STM32H7 DMA not transferring correct values into TIM15 CCR1 register, why?

I feel like I am running out of options as to why this is occurring as the RM isn't that accurate to setup DMA + PWM using Timers. The goal is to use TIM15 as a PWM generator running @ 800kHz running ...
1 vote
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CORDIC module for (0, 90)

I found this CORDIC Verilog code online. It calculates sine and cosine from (0, 360). I was thinking if there is a way to modify it to (0, 90) and then use 4 such CORDIC modules in a pipelined ...
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AMI chips S1894 C8873 C1969 C1968

Help appreciated identifying part and finding datasheet inside С1968
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Why my register file operates abnormally

I tried to implement a 32x32 bit register file using Logisim, however once I have finished drawing and proceeded to test it by initializing the content of individuals registers to zero using the reset ...
-3 votes
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Counter - backward and forward [closed]

I have a 4 digit number and want to go through it first from left to right and then from right to left, digit by digit. This is to be solved with logic gates and a circuit. Given for this task are D-...
1 vote
1 answer
385 views

How can I implement this function with JK Flip Flop + NAND Gates

I have a problem about logic design. I need to design MOD 5 Up/Down Counter with control input x, when x=0 it will count down and when x=1 it will count up. I'm allowed to use only JK flip flop and ...
2 votes
1 answer
212 views

Is it possible to use cascaded 1 bit magnitude comparators to create an n bit magnitude comparator?

I know it is possible to use 4 bit comparators to create N bit comparators as shown in this Data Sheet http://www.ti.com/lit/ds/symlink/sn54s85.pdf but is it possible to do it with 1 bit comparators?...
2 votes
1 answer
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create_generated_clock quartus for derived clock

I am working in a design that creates a 1Hz clock from 20MHz PLL out. For that purpose, I have created a counter that switches its out when its value arrives to 10 000 000. That 1Hz clock is used as ...
1 vote
1 answer
38 views

SystemVerilog testbench giving don't care (X)

Can anyone help me figure out as to why I'm getting don't cares? I think it's not reading the signaldata.txt file which is why it prints don't care. ...
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2 answers
280 views

Using synchronous input along with asynchronous input at the same time in a flip flop

For example let us consider an SR flip flop. If the clear input is 0 (active low) and preset is 1 this will force the output to go to reset condition (Q=0 and Q'=1.) But if the clear=0 and Preset =1 ...
1 vote
1 answer
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D flip-flop frequency divider

I'm using a transmission gate base DFF to build a simple frequency divider. It worked, but I'm getting some weird waveform at some intermediate nodes and the power consumption is high too (11 μW). ...
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221 views

Can I implement addition and subtraction in different operations using a MUX?

I'm building a 16-bit ALU that needs to be able to perform logical AND, OR, add, subtract and rotate one bit to the left. I need to have addition and subtraction operate with different op codes ...
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1 answer
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Pseudo dual port RAM in verilog

How does one design a pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ? Clarification on 'pseudo dual port - single port ...
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1 answer
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Understanding the Schmitt trigger circuit using CMOS inverters

This is the circuit I'm trying to understand: What I understand: Clearly, whenever \$V_{out}\$ is low \$M_{3}\$ is off and the strength of \$M_{2}\$ and \$M_{4}\$ surpasses that of \$M_{1}\$ so the ...
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1 answer
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Error (10500): VHDL syntax error at setpoint.vhd(37) near text "when"; expecting ";"

It may be simple but I don`t know what's the error. ...
1 vote
1 answer
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FSM for carpark system with 2 sensors

Basically, I want to design a system where a vehicle goes through one of the sensors, then both, then leaves one, leaves both and finally counter goes up by 1. I've been able to draw the graph below. ...
1 vote
1 answer
384 views

Why input combinations producing output '1' constitute a standard SOP expression and those producing output '0' constitute a standard POS expression?

Why input combinations producing output '1' are picked for forming a standard SOP (Sum of Products) expression and input combinations producing output '0' are picked for forming standard POS (Product ...
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1 answer
488 views

Digital compatibility of logic gates

I started an applied electronics course at my university and my teacher assigned us this assignment after a lecture on how to check the compatibility of two or more gates: Output electrical ...
2 votes
1 answer
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How to achieve signal gating with trigger input

I am currently working on a project that generates enable pulses of extremely diverse lengths from microseconds to days and under normal operation will start execution under a trigger input. However, ...
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1 answer
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Trying to understand how to design properly asynchronous signals in SystemVerilog

I have implemented a serial-in parallel-out register implemented in SystemVerilog: ...
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1 answer
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"Tiny " XOR gate simulation not working

I am trying to implement this below XNOR circuit in Cadence. I am using GPDK 180nm and 1.8 V power supply. Here is the schematic in Cadence. Doing a DC simulation, I am not getting proper voltages at ...
0 votes
2 answers
488 views

Designing of Serial-in/Serial-out Shift Register using RAM

Design a 1024 bit serial-in/serial-out unidirectional shift register using a 1K × 1 bit RAM with a data input Din, data output Dout and control input READ/WRITE'. You may assume the availability of ...
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2 answers
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Write logic gate equation from circuit

Above is the circuit with my attempt and how I viewed it. I'm wondering if there's anyone that can confirm if I got it right? The middle red line that goes through the Not gate confuses me. Any help ...
1 vote
1 answer
1k views

what should be the aspect ratio for 32nm and 45nm technology?

i am designing a combinational circuit and circuit worked well too. but i want to know if i directly write a net list rather than generating it through some schematic what should be the concept behind ...
1 vote
1 answer
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In SystemVerilog, will assign a variable to itself within an always_comb block generate a latch?

In SystemVerilog, always_comb blocks must always specify the value of all the signals within them for all possible case branches ...
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35 views

Strange behaviour AT28C64B

I recently got a bunch of AT2864B EEPROMs that I am using to make multiplexer for a display. I've hooked up all values correctly and looked through my code countless times without any trace of such ...
0 votes
1 answer
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Trigger falling signal on hi/low chatter

I want to use one of those tilt-ball switches on an interrupt with a microcontroller that can only trigger an interrupt on a signal FALLING from high to low, in a low power circuit. The tilt ball ...
2 votes
1 answer
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Is it acceptable to gate an SPI clock (sck) to disable it when ss is high? (in an FPGA)

As far as I know, gating a clock in an FPGA is a very bad design practice because it can lead to clock skew and higher power consumption. This is specially true for the system's main clock, but what ...
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2 answers
159 views

Digital logic/sequential circuit to produce one pulse for every 5 clock pulses

I'm working on a problem where I'm trying to design a digital logic circuit (sequential circuit?) to produce output Y given input A: So the goal is to produce one pulse for every 5 input pulses. What ...
0 votes
2 answers
525 views

Design Counter With Arbitrary Sequence Using Load

I'm trying to design an asynchronous counter with JK flip- flops, with an arbitrary sequence. The sequence is: 0, 1, 2, 3, 4, 5, 2 ? I know how to solve this kind of problems, but in this case how ...
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Which edges (h->l or l->h) does this circuit detect? [closed]

Which edges (h->l or l->h) does this circuit detect? When I simulate it, the output voltage is constant, so it does not seem like it would detect any edges, which I did not expect.
1 vote
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How does a TTL gate input strain an ALS-TTL gate output, and how does it strain a CMOS gate output?

How does a TTL gate input strain an ALS-TTL gate output, and how does it strain a CMOS gate output? Or do you maybe know where I can find resources on the topic?
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3 answers
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Separate two batteries getting charged by one charger with diodes?

I've got a robot that I use two batteries on. One of the batteries power the servos and engines and the other is for the digital boards. The servos need 5 V. The control board and LCD run on 5&...
2 votes
3 answers
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D flip-flop BCD upcounter

I am trying to design BCD upcounter (0~9) using Dff in Pspice. From the state table below, my optimized boolean expression is like this: input D8 = Q4Q2Q1 + Q8Q1’ input D4 = Q4’Q2Q1 + Q4Q2’ + Q4Q1’ ...
2 votes
1 answer
591 views

Johnson counter using structural modelling in verilog

I'm trying to build a 4 bit johnson counter using JK flip flops and structural modelling. For the FF's themselves I'm using behavioral code and then instantiating them inside the counter module which ...
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2 answers
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Can circuit without memory give output depending on the order in which input pins were activated for non-commutative operations?

Going trough making small NAND based computer. I have two input pins zy (zero 16 bit Array y), ny (negate bitwise 16 bit Array y). Implementing each one separately or in connection is no problem but ...
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Manchester encoding where the initial state is low

Is this correct? I thought in Manchester encoding the 0's had to be high-low transition, even if the initial state is assumed to be low and 1's low-high.
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1 answer
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Remake a Circuit using Multiplexers

I made this circuit yesterday using normal logic gates and chips: $$(AB)+(A\bar BC)+(\bar AC)$$ Now I have to remake it using only MUX but Im having some trouble. From my understanding I should use ...
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1 answer
3k views

Boolean majority function

In this picture is an example of a boolean majority function (may be a bad example) So the rule says that the result or an output of a majority logic function would be a selection of majority inputs, ...
4 votes
7 answers
3k views

Is Ethernet synchronous or asynchronous serial?

I already tried googling but I cannot find an exact answer. Some say it is synchronous, some say asynchronous. For example, see these links: https://www.quora.com/Is-Ethernet-synchronous-or-...
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3 answers
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Does VGA (video graphics array) carry an analog-modulated digital video signal?

If VGA (video graphics array) is analog, then how is it compatible with a digital monitor? When I say "digital monitor", I am referring to TFT LCD display monitor. My guess is that maybe it ...
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How to design, build and test synchronous sequential circuits using T-Flip Flops?

I want to Use T flip-flops to design the circuit specified by the state diagram of following figure. Zi represents the output of the circuit. This is my school project. I did everything. But I cannot ...
3 votes
2 answers
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Constraining combinatorial path delays in Intel Cyclone-V FPGA

I am working on a design with a Cyclone-V FPGA. I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother. 4 DFFs running on each of these respective ...
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Simplifying Boolean Expression AB'C⋅(BD+CDE)+AC'

I'm currently stuck on the expression listed below. I applied almost all the Boolean algebra rules trying to figure it out, but no luck Here is the expression $$\boxed{\mathtt{AB'C\cdot(BD+CDE)+AC'}}$$...
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How to determine the flip-flops input in truth table

I've only one simple problem about JK flip-flops. The last columns in the following table (Flip-flop inputs). How were they genereted from the other parts on the left? Does this has a relationship ...
0 votes
1 answer
557 views

Building a D flip-flop with two D inputs using 3 S-R latches

"Use three clocked SR latches to build a D flip-flop with two D inputs (D1 and D2 ) and two clock inputs C1 and C2 . Clock C1 takes data D1 and clock C2 takes data D2 ." Any hints how to start?
1 vote
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Why is order of bits not getting reversed?

In this code, while declaring in and out, the seventh bit of input is MSB, while the zeroth bit of output is MSB. So, why is the ...
1 vote
2 answers
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(7,4) cyclic code encoder in VHDL

I am trying to write code for a cyclic code encoder in VHDL, but I am not able to visualize how to approach the problem. Right now all I have is an entity and a few diagrams showing my approach as to ...
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3 answers
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Transistor Not Entering in Cutoff region

I have made these circuits (DTL or TTL). And I want to enter these transistors (T1, T2, T3) in the cutoff region. But I am not able to do so. Which parameter I have to change so these transistors ...

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