Stack Exchange Network

Stack Exchange network consists of 175 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange

Questions tagged [digital-logic]

Digital electronics treats discrete signals, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.

2
votes
0answers
68 views

I’m having trouble solving this digital circuit. Help!

I need to design sequential logic circuit from this state diagram using only 2 D-latches. And this is my attempt: If I put it in the simulator it just gives me error and wont count. I assumed that ...
2
votes
0answers
159 views
2
votes
0answers
89 views

How to properly constrain ethernet phy

I am trying to use the ethernet PHY on my Nexys4-DDR. The manual for the phy gives the following timing constraints for the RMII ports. I am getting confused as to what exactly the constraints for ...
2
votes
0answers
189 views

Digital Comparator from LSB to MSB using Lookahead

This is homework to be upfront, but I'm really stuck on it and just need some kind of direction. I've been assigned to create a 16-bit lookahead comparator going from LSB to MSB using no more than 4-...
2
votes
0answers
214 views

Two different ways of writing the same thing but generating different behaviours in Verilog

I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it. The first way being : ...
2
votes
0answers
198 views

How to add two output expressions to calculate the third expression in Cadence icfb 5?

I am trying to calculate the average propagation time carry_TP from carry_TPHL and carry_TPLH which I already got the expression from the calculator tool and works well. Now how do I make the third ...
2
votes
0answers
360 views

Digital dice counting from 1 to 6

check it out guys ]3]3 the circuits above are both for an electronic dice that is supposed to count from 1 to 6 but none of the LEDS are turning on for the one that is far below, can anyone tell me ...
2
votes
0answers
969 views

What is bit-true implementation

What is bit-true implementation (with an example if possible)? I was reading a paper and it was stated "a bit-true implementation of the algorithm on a FPGA was performed." So what exactly is bit-...
2
votes
0answers
556 views

Which serial protocol or encoding scheme does this scoreboard use?

I am trying to decode a signal stream coming from a Nevco scoreboard controller: Packets like this are sent every ~2.7 ms. I suspect it is some sort of UART signal because it is on the RX line of a ...
2
votes
0answers
3k views

Constructing Excess 3 BCD to 7 segment decoder - circuit hints needed

I am currently trying to construct a circut for an Excess 3 BCD to 7 Segment decoder. Therefore the input range ranges from 0011 to 1100 in binary inclusive with the rest of the inputs being don't ...
2
votes
0answers
1k views

How to compare carry-lookahead and ripple-carry adders?

I am a bit stuck with the concept of carry-lookahead adder so I'd like to compare it with another concept I'm more familiar with: the ripple-carry adder. I'm trying to make some basic math comparison ...
1
vote
0answers
49 views

1.5 bit pipeline ADC

How do we combine bits obtained from different stages of 1.5 bit pipeline ADC. Can it be generalised for k bit pipeline ADC ? each stage has three region - 00 , 01 ,11 in 1.5 bit pipeline adc
1
vote
0answers
33 views

Will this attempt at building a four transistor multiplexer work?

Ordinarily I think most people would build a multiplexer out of a NOT gate, two AND gates, and an OR gate, which would involve seven transistors, wouldn't it? I want to see if I can do a multiplexer ...
1
vote
0answers
48 views

Voltage Across NMOS and PMOS Transistors

So I have the question above concerning an NMOS and PMOS transistor. The goal is to find V1 and V2 in steady state. My understanding is that because the gate voltages of zero and Vdd are there, the ...
1
vote
0answers
56 views

Laser Tag System Design Review

I have been working on a project to make my own laser tag gins and sensor vests. I have completed the electrical side of my design but this is the first time I have designed something like this and ...
1
vote
0answers
45 views

Implementing a circuit that takes a 3-bit number and multiplies it by 8 using only 1 4-bit adder

I was solving a past exam and this question popped up and nobody seemed to agree on an answer. Someone suggested this solution which is just hacking your way to the required result. That suggested ...
1
vote
0answers
57 views

Derivation of stability criterion for type 3 digital PLL

Could anyone help to derive the following expression (4.23) which is the stability criterion for type 3 digital PLL ? Note: Screenshots are taken from Floyd Gardner's book : Phaselock Techniques 3rd ...
1
vote
0answers
40 views

Problem based on Latches (Sequential Circuits)

I am trying to solve the following question: I want to know: If the truth table for \$ Q_{n+1}\$ and \$\bar Q_{n+1}\$ is correct. I have found out the Reset and \$Q_{n}\$ conditions. However, I see ...
1
vote
0answers
70 views

Make a double-tapping button (ideally without ICs or keeping ICs to a minimum) for a small “tiny cell” powered device

Conditions: small device, extremely space constrained (large caps are a no-go) Powered by a small battery (something like under 120 mah) Thus, adding a few more ICs like the 555 or "TimeBlox ...
1
vote
0answers
76 views

Boolean Algebra Equivalent

I am having a little trouble knowing what theorem to use to solve the following problem. Express the given equation without using OR gates. Hint: the expression two NANDed literals looks like this: (...
1
vote
0answers
66 views

Jellybean Radio Button logic Chip

Below is an LTSpice simulation of a 'radio button' circuilt. Ignore the bottom button, I am working on a 'reset' mechanism to unlatch any of the other buttons. The idea is that the button you push, ...
1
vote
0answers
53 views

How do I get the FSM table from the given diagram?

Given one is question and another solution. I cant come to this solution. can anyone help here
1
vote
0answers
50 views

Can we apply state reduction to a state table having more than 1 input?

Consider the following state diagram: I assigned states as follows: a=00 b=01 c=10 d=11 But when I attempted to reduce the table, I realized that: Some present states do have the same next state ...
1
vote
0answers
234 views

SLT in Logisim help

I have designed an ALU in logisim that can do arithmetics like add, sub, and/or. I am also trying to design the slt function. Basically when F is 111, if A < B then the ALU should output value 1, ...
1
vote
0answers
97 views

Can someone please help me with this pipelining question

A pipelined implementation of the circuit shown below is to be designed. The delays of the building blocks are indicated inside circles. You are given buffers with a delay of 0.5 ns, and flip-flops ...
1
vote
0answers
218 views

Transistor logic to drive h-bridge with negative voltage source

Shown below is a H-Bridge circuit I have used to drive the cathode of a VFD display with a source voltage of +2.4V with a +3.3V digital logic level. I have decided to switch the cathode source ...
1
vote
0answers
141 views

Proper SPDT switch wiring

Apologies in advance if this has been asked before, but I haven't been able to find anything like it. Please let me know if it has. I'm curious about the proper/standard way to connect a SPDT switch ...
1
vote
0answers
91 views

Converting BCD Truth Table to Output Functions Using K-Maps

To be honest, I'm just looking to see if I'm on the right track with a certain question. This here would be my answer for the K-Map for the "H" output function and im just curious if im on the right ...
1
vote
0answers
593 views

Worst case delay for a CMOS gate

I want to determine the input pattern for the worst case tpHL of this CMOS gate. I think there may be more than one input pattern that give worst case tpHL. The following is my reasoning: The ...
1
vote
0answers
474 views

State machines and control signals in a simple CPU

Having built the CPU specified in "The Elements of Computing Systems", I thought I'd try to design a simple 8-bit CPU myself as a fun challenge, with a view to implementing it on an FPGA. However, the ...
1
vote
0answers
64 views

Wiring Organ; Electrical Interference?

General Description (A rough block diagram is linked below.) I rewired my organ with digital electronics. I have a microcontroller (Teensy LC) that is used to scan the keys (pressed or not). It ...
1
vote
0answers
369 views

V+, V- and GND - Getting started with virtual grounds

I've been happily playing around with TTL logic but have recently come across an Analog / Digital converter TSC7106 whilst tearing apart an old thermostat which has demanded V+, GND and ... V- :o I ...
1
vote
0answers
88 views

Glitch on 7490 driving a 7441

Edit 1/1/17: I was going to take a picture of my NI Elvis breadboard as the first fee suggestions didnt work. I removed several ICs (counters) that I was going to use for the other digits and some ...
1
vote
0answers
104 views

VHDL bizarre behavior

I am facing a very strange situation: I have one VHDL entity and two associated architecture. When I test the entity with one single architecture the output is right and clear. But when I add the ...
1
vote
0answers
2k views

Implement a 3-input function using only two 2-input LUTs

This is my homework: "Given the function \$f(x_1, x_2,x_3) = \sum (2,3,4,6,7)\$ Show how it can be realized using two 2-input LUTs. Give the truth table implemented in each LUT." At the beginning it ...
1
vote
0answers
185 views

Composite video out from 74AHCxx gates with 16MHz clock. Insane?

just for fun and while waiting for other components to arrive I want to build a composite video out from available hardware. So please no suggestions to just by a propeller. Available hardware: ...
1
vote
0answers
330 views

How to make QAM (quadrature amplitude modulation) of a square or sinc wave signal?

I found this discussion of QAM in a communications text book and internet. "...load it into Matlab using imread(), which will give you an array of ...
1
vote
0answers
165 views

How to control chip select and Load DAC signals for a DAC chip?

I have a DAC7643 (Texas Instruments) - 16-Bit, Dual Voltage Output DIGITAL-TO-ANALOG CONVERTER I have been mostly unsuccessful with controlling the CS and LDAC signals. I have simulated a circuit ...
1
vote
0answers
129 views

How do I get a clean PWM (Modulation) signal to my RF supply/control for my laser?

I connected a PWM signal to the MOD input for the RF power supply. On the scope, it changed from a relatively clean signal to a very noisy signal. The laser head did turn on and fire, however, the ...
1
vote
0answers
127 views

74F86PC XOR does not work in 4 bit adder

I made a 4 bit adder where one input is from user and the other from a gated master-slave R S Nor. It seems that the XOR gates (note, not just one) always give a floating output. I have pulled all ...
1
vote
0answers
426 views

Rotation Detector Sequential Circuit

o I have tried tackling this problem, but I cant seem to get anywhere. I dont know if I am making things too complex. I came up with this state diagram and state table. But I dont know if this is too ...
1
vote
0answers
237 views

What is the significance of sensitivity list?

I implemented BCD counter using JK Flip_Flop. While implementing I missed to add "reset" to the sensitivity list of JK-FlipFlop. Because of that my simulation result appeared like this. Later I ...
1
vote
0answers
74 views

Semiconductor Level Genetic Programming

I was reading a most likely old article about, Adrian Thompsons work on using genetic programming to generate circuit solutions for simple tasks such as frequency differentiation. This got me ...
1
vote
0answers
416 views

555 to debounce comparator output for PIR circuit

I'm trying to create a circuit that takes an input from a PIR and outputs a high signal when movement is detected. My circuit currently looks like the schematic below (VCC is 5V). The circuit works ...
1
vote
0answers
300 views

find cache hit rate for direct mapped cache memory

I have this practice exam problem which I am having trouble with. I have gone over many slides but haven't been able to really get it. The question is I currently have an 8 block main memory with 2 ...
1
vote
0answers
377 views

Discrete logic multiplexer

I posted a more in-depth outline of what I'm doing here, but basically I'm building this circuit (for n=3): The circuit displays an output based on the combination of three three-input DIP switches. ...
1
vote
0answers
68 views

Digital to analoge voltage regulator

I am a complete beginner on electronics. I am trying to make device to control the voltage output according to a digital input. So basically what I need to make is to continuously increase the ...
1
vote
0answers
89 views

Designing 1-to-2 demultiplexing circuit with a custom truth table

I'm trying to build a circuit with following truth table with CMOS logic. Pins are: I and A are inputs ...
1
vote
0answers
2k views

SAP-1 (Simple as Possible) W Bus

I'm currently investigating the SAP-1 to build in order to grasp a really good understanding of simple 8 bit computers. There are a few questions that I would like clearing up. What exactly is the ...
1
vote
0answers
2k views

Error-Detection Circuit — How does this work?

I'm currently studying for finals (I have the solutions here already, so this isn't helping me bypass doing homework or anything like that.) My professor has done an unsatisfactory job explaining ...