Questions tagged [digital-logic]

Digital electronics treats discrete signals, unlike analog electronics which treats continuous signals. Digital logic is used to perform arithmetic operations with electric signals and constitutes the base for building CPUs.

Filter by
Sorted by
Tagged with
0 votes
2 answers
31 views

3 Phase Pulse Generator

I cobbled together a simple 3 phase pulse generator for a project I am working on. I've attached a picture of the circuit. I need to get a quick (~50ns) pulse on each phase. I have concerns about the ...
Brian's user avatar
  • 173
2 votes
2 answers
318 views

Can I cascade two different shift register?

I would like to drive multiple nixie tubes using shift register. I wonder that can I cascade two different shift registers to control them using arduino or another MCU? My plan is to connect DATA OUT ...
enis's user avatar
  • 73
0 votes
2 answers
39 views

Will the frequency change when converting the ESP32 3.3 V logic to 5 V logic using a TXS0108E?

The GPIO on ESP32 (S3) are all 3.3 V logic. I want to control an ESC for a drone. The manufacturer says: The ESC will use a standard 5 V PWM signal at 50 Hz between 1100 µs and 1950 µs. 3.3 V output ...
ferer's user avatar
  • 1
0 votes
1 answer
43 views

Arduino pro mini 3.3v where are the digital pins 0 and 1 [closed]

I am using an Arduino Pro Mini, 3.3V, 8MHz board. Now I need to use the digital pins 0 and 1 as I have already used pins 2-12. I am not sure where the digital pins 0 and 1 are located on the board. ...
Fredi's user avatar
  • 19
1 vote
1 answer
60 views

Single-Digit BCD Adder

I have this code written in SystemVerilog. The module bcdadd1 is supposed to take in two 4-bit inputs A and B and a logic input carryin (...
David's user avatar
  • 23
0 votes
1 answer
57 views

A confusion with logic level output description

Following shows the difference between TTL and 5V-CMOS logic: If a device manual states it has TTL input I can say that one can expect 3V pulse can work as input. But my confusion is, what does it ...
cm64's user avatar
  • 2,141
0 votes
0 answers
22 views

203045/break-before-make-spdt-relay-out-of-2-spst-relays

I have question concerning: "make before break" relay instead of the posting "break before make" relay. (see post 203045 originally drawn with IC 74HC02 Quadruple 2-Input Positive-...
Holz1's user avatar
  • 1
0 votes
0 answers
51 views

Single Switch with Momentary and Latching/Hold Properties Using CMOS/Logic (no µP/microprocessor)

I am looking for a CMOS/logic based solution (no µP/microprocessor) to a momentary switching scheme I'd like to implement that involves the following scenario: 1: pressing a momentary switch engages ...
paraparabolic's user avatar
0 votes
1 answer
42 views

dual power supply - digital line current limiting

I am connecting the transceiver chip to the PIC16 MCU and is going to power them from different switching power supplies, originating at same power source. Both power supplies output 3.3V, thus ...
Anonymous's user avatar
  • 7,078
0 votes
1 answer
45 views

Power bank 4s voltage monitoring using cd4052

i working on pcb with a 18 volt dc like circuit below . I have a question about driving logic A and B of cd4052 with my esp32 do my circuit is correct. Do I need extra component between Drain of the ...
Khales Naim's user avatar
-1 votes
0 answers
44 views

Design a signed fixed point multiplier Verilog? [closed]

I need to design a fixed point multiplier in Verilog that takes in 16 bits, formatted as 1 sign bit, 6 integer bits and 7 fractional bits. I just can't figure out which bits to extract to ensure an ...
Random person's user avatar
1 vote
1 answer
42 views

Getting HiZ for my output for a 5 to 1 mux

I'm having trouble with Verilog code for a 5 to 1 MUX. ...
Michael's user avatar
  • 13
2 votes
1 answer
53 views

D latch module in VHDL using NAND structure [closed]

What is the difference between a positive-level D latch and a negative-level D latch? How to create positive and negative D latch in VHDL using NAND structure? Can you share some example codes for ...
Serkan Kaya's user avatar
2 votes
1 answer
63 views

IC 74HC08 can the output drive the input without destroying it? [closed]

i made a circuit with a 74HC08 and i wanted that when the output is high(1Y) it would take over contact (1B) with a led between it .and the input B connected to ground with a 20K resistor it works ...
jokertje1's user avatar
0 votes
0 answers
44 views

SLF3S-4000B not recognised by Arduino Uno R3

I have a Sensirion SLF3S-4000B connected to SDA/SCL lines of the Arduino uno through a logic level shifter (connected like in this example: https://learn.sparkfun.com/tutorials/retired---using-the-...
CadeO01's user avatar
0 votes
1 answer
58 views

Why am I getting error C:\Program Files (x86)\iverilog\bin\iverilog.exe: unknown option -- O when trying to run this Verilog code?

On Visual Studio, I run this Verilog simulation command, but I get the error message: ...
Ahmed Sweillam's user avatar
0 votes
0 answers
32 views

Can the SOP expression be the same as POS expression?

I have a function as F(A,B,C,D)=M0+M4+M12+M8 I'm getting the simplified Product of Sum expression as C+D but I'm getting the same expression again as Sum of product
Taiba Sharif's user avatar
2 votes
6 answers
2k views

What can be done with all of the extra address lines in a ROM? Why were they designed to have so few outputs compared to possible inputs?

I am a student in an introductory Digital Logic and Computer Systems course. We have been learning about ROMS, but often we just use them to basically just map truth tables onto them. We have been ...
LeBronJames's user avatar
0 votes
1 answer
30 views

JK flip flop timing diagram

Is this JK flip flop timing diagram for the Q output correct? I just want to make sure I didn't mess anything up.
JP NICOSIA's user avatar
0 votes
1 answer
67 views

AND gate example

When I closed switch 1, I apply 9 V to input 1 of the AND gate, but there is a resistor here. Can I be sure that the total 9 volts does not drop through the resistor? Why is the voltage dropped across ...
Serkan Kaya's user avatar
0 votes
3 answers
94 views

Clarification about leakage current in IC

Datasheets usually specific pin leakage current for digital inputs in the Electrical Characteristics, which is generally in microamperes (µA) range. I understood from different SE posts that the ...
LoveEnigma's user avatar
-1 votes
0 answers
36 views

Calculating the Depth of Asynchronous FIF0

Let us say module A wants to send data to module B Writing Parameter of Module A: Width of Variable: 32-bit (the variable where data is written) Frequency : 20 MHz Reading Parameter of Module ...
Adam01's user avatar
  • 1
1 vote
1 answer
43 views

Why does passing the subrange of a bitvector to a module in Verilog produce an unexpected result?

To better understand what it is that I'm asking about, please compare "Code A" to "Code B" below. Code B is more compact, but unfortunately does not produce what I would consider ...
phil1008's user avatar
  • 432
1 vote
1 answer
32 views

Stateful logic synchronization clock with memory read/writes

I am working on a hobby project using Verilog and iCEstick evaluation board. I have a stateful logic (FSM) which needs to read and write to the on-chip block RAM. Now I am a little bit confused, it is ...
Alexandr Savochkin's user avatar
0 votes
0 answers
72 views

Transmission of signal power in the RF for relays

I'm trying to solve one problem for transmitting a signal to the outputs of the chips. I need to transmit digital signals with an amplitude of 20 V and a maximum current of 500 mA, at a frequency up ...
Marl0s's user avatar
  • 1
1 vote
1 answer
35 views

Error: near "end": (vcom-1576) expecting == or '+' or '-' or '&'

It may be a simple fix, but I do not understand the error: Error: near "end": (vcom-1576) expecting == or '+' or '-' or '&' ...
Anne van der Doelen's user avatar
1 vote
2 answers
52 views

How are event-controlled events scheduled in Verilog?

Consider the following snippet (please let me know if you need me to include more): ...
EE18's user avatar
  • 1,131
1 vote
1 answer
38 views

Moore Detector -1011, non-overlapping case

I am not able to figure out why the output goes low when I have done it properly. I used the similar logic for Mealy. It worked, but here it's not proper. ...
Ojas Kudari's user avatar
0 votes
2 answers
58 views

Can inputs be at the source/drain of MOSFETs for digital logic circuits?

There is a question in my University exam requiring us to design a logic circuit for the following logic using the smallest number of transistors: I was trying to optimise at the gate level by using ...
ZHZ's user avatar
  • 13
0 votes
0 answers
46 views

Using a 4-Pole Relay to trigger a switch for a detection circuit

sorry not super hot on electronics and hope I can explain myself. I am building a model railway and use a device from a company called NCE called a BD20. It is a simple induction switch - when there ...
trevleyb's user avatar
0 votes
2 answers
86 views

Is the communication between memory controller and RAM serial?

I used to think that the communication between memory controller and RAM is parallel since we know that a RAM stick has multiple pins, just like this: But then, from Wikipedia article on memory ...
Noob_Guy's user avatar
  • 433
0 votes
1 answer
39 views

Are these valid logic circuits?

This [Circuit A] is allowed in Digital: This [Circuit B] is also allowed: Until I turn off one of the inputs: This [Circuit C] causes a different error, depending on whether the input is on or off. ...
obe's user avatar
  • 119
1 vote
2 answers
62 views

UART Transmitter implementation using Verilog

I am trying to implement the UART transmitter FSM using Verilog, but the FSM is stuck at IDLE state. Can someone tell what mistakes am I making? The code is as ...
Kartikey's user avatar
1 vote
2 answers
45 views

Why am I getting ZZZ output for my Verilog cordic code?

...
user avatar
1 vote
0 answers
59 views

3m unshielded 3V3 UART

I have a product that probably uses the wrong digital interface, but I'm trying to make it work anyway. Differential signalling, a better cable and other things would be desirable, but that is outside ...
Alexander Ohm's user avatar
0 votes
1 answer
42 views

Defining arbitrary length bit-string literals for constant std_ulogic_vector in VHDL

I want to be able to define a simple constant for DEFAULT_BUS as all Z, or some other std_ulogic value, but its length should depend upon another generic value as per instantiation and it'd be nice to ...
David H Parry's user avatar
0 votes
0 answers
30 views

ZYBO Z7 ADC XAdcPs_GetAdcData send just initial data

Even though I'm resetting the variable my_raw_data , the program continues to return the initial data instead of the current data. I use a potentiometer on aux14 port but ı can't take anything but ...
Emre YILDIZ's user avatar
1 vote
1 answer
95 views

Verilog synthesize FIR filter coefficients in correct representation

For an implemented FIR filter in Verilog, I generate filter coefficients using Python's scypi. Using its firwin-function, I receive 64-bit floating-point coefficients like: ...
Alex's user avatar
  • 13
0 votes
2 answers
70 views

Low drive strength of level shifter

What part of a level shifter datasheet indicates drive strength? I have an MCU and sensor connected over UART (115200 baud). The MCU is 3.3V and the sensor is 1.8 V, so I'm using a level shifter in ...
Alexander Ohm's user avatar
0 votes
2 answers
102 views

Why can't software capture PCIE packets?

I found this question in Stackoverflow and the answers say: I don't believe so -- from a software viewpoint, PCI-E is quite well disguised to look like (fast) PCI. As far as I know, nearly the only ...
user1783484's user avatar
-2 votes
1 answer
33 views

TinkerCAD Digital Logic LED [duplicate]

I finished building this circuit in TinkerCAD, but for some reason the AND gate won't behave like it's supposed to. Shouldn't the LED turn ON when both 1 and 2 are ON? Instead, it turns ON when both 1 ...
user367142's user avatar
-1 votes
1 answer
39 views

TinkerCAD Digital Logic

Everything here seems to be right, like the gates and resistors, but the gate seems to be the issue; the LED is off when the switch is on. What is the issue? I have also included the schematic.
user367142's user avatar
0 votes
1 answer
22 views

connecting sensirion SLF3S-4000B flow sensors to arduino uno r3 via I2C bus

I bought the following sensors for my project: https://www.farnell.com/datasheets/3730435.pdf I am using two and they operate on 3.3V logic. They use a standard 6 pin picoblade 150mm connection. I am ...
CadeO01's user avatar
1 vote
2 answers
91 views

Verilog sum problem

I have an array named mixed_signal, and I need to sum of its elements in a register but it cannot be sequential. Can you help me? ...
Emre YILDIZ's user avatar
1 vote
1 answer
60 views

Functions in Verilog for combinational logic

I encountered something weird in a Verilog code, and I have doubts about it. Someone used a function in Verilog in the following way: ...
Michael Rahav's user avatar
0 votes
1 answer
30 views

Led blanking while the DIO_Read is LOW and work well while DIO_Read is HIGH

I'm trying to read digital 24v in MCU so I used a voltage regulator to step it down to 5v then I got the 5v to pull down resistor with a transistor like that then I get the V out to the MCU pin which ...
abdalla zakaria's user avatar
0 votes
1 answer
39 views

Why is this extra MUX here when shifting mantissa as part of a FP add?

My textbook (Harris and Harris, Digital Design and Computer Architecture) asks us to design a simplified (in that only positive numbers be considered, with NaN and infinities ignored) FP adder block. ...
EE18's user avatar
  • 1,131
0 votes
1 answer
64 views

Millivolt logger with high sampling rate [closed]

I'm trying to find modern components for a design that would be able to record millivolt range samples at a high sampling rate (~30 kHz) for ~1 hr interval. Key components I can think of thus far are ...
Keiland Cooper's user avatar
0 votes
1 answer
43 views

LS19-S, what to do with unused inputs>

I am using a LS19-s switch debouncing IC, and the datasheet does not specify what to do with unused inputs. I know for CMOS chips it standard to ground unused inputs and for TTL chips the unused ...
Zackery Fleming's user avatar
0 votes
1 answer
63 views

Does this design cause floating input?

I started investigating this circuit. The circuit is used to detect another PCBA when it is plugged in as the signal IN# and sends the signal IN#_BUF to the microcontroller. The issue is sometimes the ...
WUP's user avatar
  • 1

1
2 3 4 5
94