Questions tagged [digital-logic]

Digital electronics treats discrete signals, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.

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Multiple switches to independently control the counters

I just started studying electrical engineering this semester, and I'm currently working on the following counter to count the vacancy and occupied bed counts in a hospital for my school project: The ...
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Subtraction using 2's complement, why 4, 8 or 16 bit are required

During subtraction using 2's complement, why it is important to decide on the number of bits we are going to use, (e.g. 4 bit, 8 bit, 16 bit etc) and use the same number of bits to write each number. ...
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What happens when there are multiple Read requests to the same address in AXI3/4? Does RVALID assert each time?

Basically the title. I am trying to do a verification on an AXI4Lite protocol. If I try to send a read request to the same address multiple times the RVALID is not re-asserted. Correct data just ...
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Why is my Logisim circuit output xxxx?

The picture below is a Logisim circuit output. As you see, each output bit is an x, not a 1 or a 0. Is there something I should change to make the output show 0 or 1?
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Can I use logic inputs higher than Vcc but still in the operating voltage range of the IC?

I'm trying to create a battery-backed-up non-volatile RAM using an SRAM IC (AS6C1008 from Alliance Memory, datasheet). My idea for separating the backup battery from the main voltage source is to use ...
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Any experience on the 2N7002 MOSFET for logic level working at 3.3 V?

I know that the 2N7002 is nominally a 5V MOSFET (probably it was designed at 10V and then rated at 5V?). Also Nexperia is cheating and has 'variants' on the 7002 (better VGSth on some) However with ...
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Is this a Moore or a Mealy machine?

I'm learning circuit design for the first time and I've designed this circuit. I am having a hard time deciding if it's a Moore or Mealy machine from my current understanding. The yellow "logic ...
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How important is it to register signals at both input and also output in digital design?

In digital design, the output signals may have source in register or perhaps some combinatorial logic which is directly connected to an output port. This raises these questions: How important is it ...
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Will a synchronous circuit have a race condition if not all inputs arrive before the clock rising edge?

Suppose that the circuit has several inputs from an external circuit which do not have an effect until the clock next rise edge due to using synchronous flip-flops. If the external circuit sends ...
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Will a shift register cause metastability?

The graph above shows the output of a shift register. The output of Qa is sampled at the first rising edge on data input. the voltage is building up during that time. Will it cause metastability ...
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Is there an electromechanical equivalent of an SPDT switch? [closed]

I want to control 2 outputs with a single input. SPDT switches are mechanical from what I understand, is there an equivalent of electromechanical switches like SSR for SPDT for example?
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How do you make a three two-input and gates function as four-input and gate

I'm having a hard time trying to recreate this logic. I used the output of my two and gates connected to another AND gate will that work? or is there any better solution to this problem?
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Frequency of a sequential circuit

I'm reading the book Digital Design and Computer Architecture. I came across this exercise: From what I've learned so far, the frequency of a circuit is the reciprocal of the clock period. Since we ...
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7 answers
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What is the simplest way to invert a signal with just one jumper?

I need to pass the signal from an end stop (limit switch) to an MCU and I'd like to make it flexible (to make it possible to work with both types of limit switch: normally-open and normally-closed) as ...
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-8 votes
4 answers
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Does this combinational lock circuit contain any memory?

Consider a simple lock circuit built using a 4-bit, active HIGH digital comparator. The first input is variable; it is the input that unlocks the lock. All the bits of the second input are tied to ...
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Array of genvar in SystemVerilog

I'm trying to implement a Dadda tree multiplier in SystemVerilog using generate blocks. However, the algorithm I'm using to instantiate the logic requires arrays, ...
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Making a 12 hour digital circuit in MULTISIM

I saw a video for building a digital circuit but he uses a different decoder and counter. Can anyone help me understand how these work and give sources to read more about them? the decoder: (...
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Is a combinational logic circuit a Finite State Machine? [closed]

Is a combinational logic circuit a Finite State Machine? In other words, is the class of combinational circuits a subset of the class of Finite state machines?
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We want numbers that lie between 1 and 10 inclusive, why should I use OR gate instead of AND?

I know the answer, I need to use an OR gate because that is how the code works. I want to learn the problem solving part of this. The code that works is: ...
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How often does one have to design low level adders or multipliers in digital hardware?

There are a few different techniques to implement adders like ripple adder, carry look ahead adder etc. Similarly there are different techniques to implement multipliers as well which include Booth ...
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Verilog code shows unknown results (X) for some reason

I wrote this code, and it doesn't give a value for the sum. Why is that? design: ...
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1 answer
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Can FPGA logic be represented by a matrix/sequence/chain/expression? [closed]

There is an interesting paper from our chemistry peers, where they achieve to represent molecules into a sequence of characters. This obviously inspired me to think that there must be something ...
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2 votes
1 answer
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Where is the shift register used?

I have just studied digital logic material about shift registers, but I don't know what shift register models in the picture above are used in everyday life? What is an example of a product?
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6 votes
3 answers
829 views

Does the 1x oscilloscope probe setting slow down MHz digital signals?

I was debugging what I thought was a weak LVDS driver fed with a 10MHz clock for hours when, out of other options, I've set my scope probes to x10 and although the signals were showing some ringing ...
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2 votes
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What is the invisible layer between Boolean algebra and the physical circuit of a computer, and how to understand it?

How is Boolean algebra implemented through a circuit ? Is it just a way of thinking about a circuit? You don't need Boolean algebra to think about a circuit since it is made of physical components, ...
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Logic state explanation

If the start push button is pressed, is the logic level at RA5 1 or 0?
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I need some clarification/explanation on how this digital oscillator works

Linked here contains the diagrams of the oscillator I'm referring to. I'm confused about a few things: In the section showing the diagram with the freq register bits, this says "The input is ...
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Single Diode Mixer Port Isolation

I am an amateur radio enthusiast that would like to build an FM superhet receiver. I am stuck on a mixer design. Each block of my diagram is functional when running independently. However, once I ...
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1 vote
1 answer
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How can I multiplex the outputs of an XBEE and a MAX485's?

I have a microcontroller that gets fed with 8-bit commands that either come through wires (using the RS-485 standard) or by the RX pin of an XBEE (without using actual switches) I want to multiplex ...
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Minimizing delay of Full Adder

It is said that by exploiting the inverting property we can "reduce one inverter delay in each full adder". Why is that? Clearly, we can reduce one for the input of the first adder, but we ...
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1 vote
1 answer
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Full adder Cout expression issue

The truth table of a full adder is as below. Cout is given as Cout = AB + Cin(A XOR B). not sure why is that because when I do my k-map on the Cout, I get Cout = AB + Cin(A+B). does anyone know why is ...
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How to Setup the following Finite State Machine

The question goes as follows: Design a finite state machine (FSM) with two inputs (x and y) with an output z, which is asserted every time x and y change state to opposing values at the same time. A ...
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2 votes
2 answers
157 views

Can't provide an input clock signal to an SPI slave implemented in an FPGA through a PMOD pin

I have implemented a dummy SPI slave device within an FPGA (Basys 3). The master device is in an MCU. I'm trying to connect the clock signal generated by the master (MCU) to the slave clock pin (a ...
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Is more clock speed means higher risk to circuit can have race condition

It is a very simple question but it made me think. I have been working on finite state machines. I came to topic of finite state machines from combination circuits. In the book it says that sequential ...
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0 votes
2 answers
117 views

How to make transistor operate in active or saturation-and-cutoff region

There are plenty of quotes on the internet like this one: "There is nothing like 'analog transistor' and 'digital transistor'. A transistor is a transistor! Simple. One can make either analog ...
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How will supply voltage affect propagation delay?

Here is my circuit: I want to measure the propagation delay between the input D and output Y. As I understand it, the higher the supply voltage VDD is, the faster the propagation is. When I measure ...
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5 votes
3 answers
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How is clock gating physically achieved inside an FPGA or ASIC?

It is bad idea to add logic gates in clock signal path. How is clock gating achieve in FPGA and ASIC designs and how does it prevent glitch in the output signal i.e the gated clock as it is enabled or ...
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7 votes
1 answer
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Why is BMC/k-induction used in RTL formal verification?

One popular approach for proving safety properties in formal verification of RTL designs is a combination of BMC and \$k\$-induction, which appears to stem from "Checking safety properties using ...
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1 answer
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Connecting multiplexer/demultiplexer input to Vcc of the same chip. Will this cause any performance issues?

In one of my circuits, I am connecting the I/P pin of multiplexer/demultiplexer to Vcc (5V) as shown below. I have 2 questions. When switching, will the current draw cause performance deviations in ...
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4 votes
2 answers
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0110 moore overlapping in verilog

I am designing "0110" overlapping sequence detector using moore model in verilog verilog code: ...
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1 vote
1 answer
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finding inverting vs non inverting functions

So Im learning cmos systems and Im struggling with the pmos and nmos part of it. So for example given F=minterms(m0,m1,m2...) I can do the kmap and get the function no problem but how do I know if ...
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3 votes
2 answers
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Constraining combinatorial path delays in Intel Cyclone-V FPGA

I am working on a design with a Cyclone-V FPGA. I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother. 4 DFFs running on each of these respective ...
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2 answers
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VHDL - Adding two std_logic_vectors, issue

I'm having an issue when trying to add two std_logic_vectors. The two vectors are reg_A and ...
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0 answers
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In bit-pair recoding of multiplier, why is the pair (0 +2) used in place of (+1 0)?

I was going through the text "Computer Organization" by Hamacher et. al. Where I came across the following section about bit-pair recoding technique of multipliers: A technique called bit-...
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3 votes
1 answer
415 views

Difficulty in understanding the analysis of worst-case signal propagation delay in an array multiplier

I was going through the text "Computer Organization" by Hamacher et. al. where I came across the concept of array multiplier. The design of 4 x 4 array ...
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0 votes
2 answers
159 views

Divided vs Multiplied clock

I heard someone saying that for example for FPGA design, it is better to multiply the input clock in the PLL and then use the result as my main clock instead of divide my clock in the PLL, for reasons ...
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1 vote
1 answer
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Why is quantization defined in powers of integer multiples of two in digital image processing?

I have been studying quantization in the context of digital image processing. I referred to the 4th edition of the book titled Digital Image Processing by Rafael C. Gonzalez and Richard E. Woods. In ...
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2 votes
1 answer
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Design a circuit with relays or switches that has 10 connected devices that can only be powered one at a time

This is my first post here and i was wondering if anyone could help me. I am trying to create a system that will enable me to connect nine or ten 240v devices but only run one at a time. if one in the ...
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1 answer
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Need help shrinking a 4-bit binary Adder/Subtractor/Multiplier calculator circuit

Project Description: A mini-calculator that performs addition, subtraction, and multiplication on two 4-bit inputs (0-9) and displays the inputs and resulting numbers in 7 segment displays. Aside from ...
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3 votes
1 answer
125 views

Digitally tunable gain, low-noise instrumentation amplifier

I want to make a digitally-tunable gain (~1 to 1000x), low-noise instrumentation amplifier. There are integrated ones (e.g. AD8557) but the input noise is too high. My current plan is to use an ultra-...
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