# Questions tagged [digital-logic]

Digital electronics treats discrete signals, unlike analog electronics that treats continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.

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### Reading a file in Verilog

I want to read a file in Verilog that contains both positive and negative numbers. For example, the file contents are: -4 20 28 -52 and so on. Also, after reading ...
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### Source of noise

The picture shows the circuit I am working on. A sinusoidal burst of 4 MHz (24 cycles) is generated from a waveform generator. This sinusoidal input is connected to a comparator IC through an SMB jack ...
253 views

### Create a logic circuit only using AND & OR gates

yesterday I had an exam, in which I still don't know how to resolve the problem. The question of the exam was: Create a logic circuit with 4 inputs (A,B,C,D) using ONLY AND & OR with 2 INPUTS ...
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### Can a reset level from a voltage supervisor be controlled for power-on transitions?

This question is related to another circuit about I have talked in an previous post. But I think by the nature of the question, this must be treated apart, in a new post. I need to keep a signal from ...
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### Correcting the lower output level of a square wave generator

I have assembled a square wave generator following this schematic from an old book. R1 and R2 are both 1 kohm, C1 is 68 pF, and C2 is 2.2 nF. The author of the book claims that this combination is ...
163 views

### How can I design a digital circuit where the output is 5 times the input? [closed]

I tried to solve this challenge by enhancing my skills in digital circuits, but could not solve it. How can I design a digital circuit where the input is only 2 bits and the output equals 5 times the ...
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### Identifying Protocol Using a Logic Analyzer

I used a logic analyzer to read the data line from a small camera battery and would like to understand the authentication my camera is doing to the battery over the one data line. Is there any way to ...
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### CORDIC module for (0, 90)

I found this CORDIC Verilog code online. It calculates sine and cosine from (0, 360). I was thinking if there is a way to modify it to (0, 90) and then use 4 such CORDIC modules in a pipelined ...
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### STM32H7 DMA not transferring correct values into TIM15 CCR1 register, why?

I feel like I am running out of options as to why this is occurring as the RM isn't that accurate to setup DMA + PWM using Timers. The goal is to use TIM15 as a PWM generator running @ 800kHz running ...
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### SystemVerilog testbench giving don't care (X)

Can anyone help me figure out as to why I'm getting don't cares? I think it's not reading the signaldata.txt file which is why it prints don't care. ...
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### D flip-flop frequency divider

I'm using a transmission gate base DFF to build a simple frequency divider. It worked, but I'm getting some weird waveform at some intermediate nodes and the power consumption is high too (11 μW). ...
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### FSM for carpark system with 2 sensors

Basically, I want to design a system where a vehicle goes through one of the sensors, then both, then leaves one, leaves both and finally counter goes up by 1. I've been able to draw the graph below. ...
97 views

### Error (10500): VHDL syntax error at setpoint.vhd(37) near text "when"; expecting ";"

It may be simple but I don`t know what's the error. ...
111 views

### How to achieve signal gating with trigger input

I am currently working on a project that generates enable pulses of extremely diverse lengths from microseconds to days and under normal operation will start execution under a trigger input. However, ...
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### Trying to understand how to design properly asynchronous signals in SystemVerilog

I have implemented a serial-in parallel-out register implemented in SystemVerilog: ...
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### "Tiny " XOR gate simulation not working

I am trying to implement this below XNOR circuit in Cadence. I am using GPDK 180nm and 1.8 V power supply. Here is the schematic in Cadence. Doing a DC simulation, I am not getting proper voltages at ...
1 vote
277 views

### In SystemVerilog, will assign a variable to itself within an always_comb block generate a latch?

In SystemVerilog, always_comb blocks must always specify the value of all the signals within them for all possible case branches ...
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### Strange behaviour AT28C64B

I recently got a bunch of AT2864B EEPROMs that I am using to make multiplexer for a display. I've hooked up all values correctly and looked through my code countless times without any trace of such ...
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### Trigger falling signal on hi/low chatter

I want to use one of those tilt-ball switches on an interrupt with a microcontroller that can only trigger an interrupt on a signal FALLING from high to low, in a low power circuit. The tilt ball ...
139 views

### Is it acceptable to gate an SPI clock (sck) to disable it when ss is high? (in an FPGA)

As far as I know, gating a clock in an FPGA is a very bad design practice because it can lead to clock skew and higher power consumption. This is specially true for the system's main clock, but what ...
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73 views

### Which edges (h->l or l->h) does this circuit detect? [closed]

Which edges (h->l or l->h) does this circuit detect? When I simulate it, the output voltage is constant, so it does not seem like it would detect any edges, which I did not expect.
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### How does a TTL gate input strain an ALS-TTL gate output, and how does it strain a CMOS gate output?

How does a TTL gate input strain an ALS-TTL gate output, and how does it strain a CMOS gate output? Or do you maybe know where I can find resources on the topic?
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### D flip-flop BCD upcounter

I am trying to design BCD upcounter (0~9) using Dff in Pspice. From the state table below, my optimized boolean expression is like this: input D8 = Q4Q2Q1 + Q8Q1’ input D4 = Q4’Q2Q1 + Q4Q2’ + Q4Q1’ ...
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### Can circuit without memory give output depending on the order in which input pins were activated for non-commutative operations?

Going trough making small NAND based computer. I have two input pins zy (zero 16 bit Array y), ny (negate bitwise 16 bit Array y). Implementing each one separately or in connection is no problem but ...
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### Manchester encoding where the initial state is low

Is this correct? I thought in Manchester encoding the 0's had to be high-low transition, even if the initial state is assumed to be low and 1's low-high.
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### How to design, build and test synchronous sequential circuits using T-Flip Flops?

I want to Use T flip-flops to design the circuit specified by the state diagram of following figure. Zi represents the output of the circuit. This is my school project. I did everything. But I cannot ...
181 views

### Does VGA (video graphics array) carry an analog-modulated digital video signal?

If VGA (video graphics array) is analog, then how is it compatible with a digital monitor? When I say "digital monitor", I am referring to TFT LCD display monitor. My guess is that maybe it ...
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### Does synthesis/ PnR tool need create_generated_clock constraint for clock MUX output?

Does Synthesis/PnR tool need a create_generated_clock constraint for clock MUX output ? If yes, why does the tool need such constraint? My previous understanding is that we only need ...
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### Why is order of bits not getting reversed?

In this code, while declaring in and out, the seventh bit of input is MSB, while the zeroth bit of output is MSB. So, why is the ...
78 views

### Transistor Not Entering in Cutoff region

I have made these circuits (DTL or TTL). And I want to enter these transistors (T1, T2, T3) in the cutoff region. But I am not able to do so. Which parameter I have to change so these transistors ...
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### Thermocouple actuated switch

So first of all, I'm a mechanical engineer and a terrible electrical engineer. I'm trying to build a failsafe for a heating element. This heater has an integrated k-type thermocouple and is limited to ...
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### voltage keeper digital circuit

How do I create a digital circuit that does the following. The output voltage Vout is at 0V originally. If the input voltage Vin changes from 0V to 1V, the Vout should also goes to 1V and will keep as ...
1 vote
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### Is this a correct FSM graph?

This is question from H.ROOTH book Fundamentals of Logic Design. A sequential circuit has one input (X) and one output (Z). The circuit examines groups of four consecutive inputs and produces an ...
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In one of the interviews that I attended, I was asked the following question: Design a circuit that we can use to add two 128-bit numbers, you have only one 4-bit adder and no other adder IC. You are ...
1 vote
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### FPGA blocking assignments in always block not working properly

In the following setup I have created a custom clock through switch on Spartan 3E FPGA to toggle the LED states one by one. I have connected 8 registers with 8 LEDs. By triggering the clock through ...
311 views

### Why is the voltage measurement across this resistor 0V? (TinkerCad) What's wrong with the circuit?

Please help me understand why the voltage measurement across the Zener diode and resistor is 0V. How should I go about getting a 4V reading there? If you notice other problems, or have some ...
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### Need help regarding BCD to 7-segment decoder

I am fairly new to digital logic designing and I need some help in regards to finding a BCD to 7 segment decoder on software. I am using proteus for my counter, and for some reason I am unable to make ...
1 vote
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### How is sll implemented in MIPS?

I don't understand how MIPS would implement the sll (shift left logical) instruction using the hardware present in its ALU as shown in the diagrams below. Would ...
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### RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?

Given the below scenario, which is a reset-domain-crossing violation : Can it be resolved using some reset synchronization strategy? Is such design considered bad to begin with, i.e. need to avoid ...
210 views

### What can procedural statements do that assignment statements cannot do in Verilog?

It seems to me that for combinational circuits assignment statements are much better and for sequential as well we can use if(clk) to run programs up to an extent, so what significant advantage does ...
1 vote
93 views

### Confusion In Fanout of Logic Circuit and Transistor

Fanout:-Maximum Gate we connect to output of any Logic gate. so there is limited number of gate we connect the output of Logic Gate.hence there is some minimum condition required for operation of ...
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### Automotive wiring OR logic gate

I am wiring up taillights for my car and need to implement a OR logic gate, I understand how to do this using two diodes and a resistor, I don't know what spec components I will need. The circuit I'm ...
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### How worried should I be about a short circuit lasting a couple nanoseconds? [duplicate]

Say I have two driver gates hooked up to each other in the following arrangement: In theory when A goes low, for a brief amount of time B will be shorted while the 7404 inverter gate switches. Around ...
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### Is this single transistor interface good enough for this relay-control?

I need to turn ON/OFF an 12V 10A SMPS supply by a relay. I want to switch the SMPS via its line input using a microcontroller. I need a normally open non-latching magnetic relay such that the SMPS ...
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### How to complete the truth table for a JK flip flop? And why?

I saw this question, but am unsure how to solve it. I have tried various approaches and get some of the answers correct, but never all of them...so my method is obviously wrong For example, what ...
138 views

### Voltage controlled 555 bistable operation

[Updated with working schematic!!!] I have a circuit which I tried to adapt from the 555 bistable configuration to have the 555 states controlled by input A and B; B always goes high before A. I am ...
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### An over- and under-voltage protection system

How can the block diagram below operate as an over and under voltage protection system? I thought it will work as follows: A step-down transformer is used to bring down the alternating current supply ...
88 views

### Logic analyzer gives me much more pulses than expected

Let me start the question by saying that I am using a logic analyzer for the first time, so I am probably doing something wrong. I sniffed the signal that goes to a speaker. The signal is probably PWM....
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