Questions tagged [divider]
The divider tag has no usage guidance.
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Unexpected voltage shift on analog input
I have a resistor divider analog input circuit that has an off-board resistance applied in the form of a sensor. The off-board sensor/resistance can be anywhere from 300 Ω to 12 kΩ.
I see strange ...
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SRT division: correcting BSD quotient
I have been reading a lot about the SRT division algorithm lately and I understand that the main idea is that it allows us to skip over addition/subtraction, unlike non-restoring division where we ...
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Please fix my broken understanding of this simple thermocouple circuit
Here's my qualm:
As per the diagram, I can't understand how the trim probe (resistor) affects the meter reading for this thermocouple circuit.
If I understand the diagram correctly, everything is ...
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Voltage divider for 14.4 V automotive signal - how can I achieve the same 5 V protection without a 5 V reference?
The atShiftSwitch signal is 12-14.4 V. I am looking to step this down to 5 V to use as an Arduino input atShiftSwitchSignal
What I don't understand is what actually happens in this schematic if the ...
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3
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71
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Configuring regulator shut-off
I'm building a regulator based on the TPS63020 buck/boost converter, and I'd like to program a low-voltage shut-off. If I'm understanding it correctly, when VINA sees a falling voltage and it crosses ...
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Circuit diagram to convert instrument level to mic level
I have a wireless mic transmitter/receiver system that I would like to use to connect to an acoustic electric guitar instead of a microphone.
This isn’t part of the problem but will describe the setup....
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2
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110
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1/60 Hz Counter/Divider
I have a fairly precise 1 Hz square wave that I would like to divide down to 1/60 Hz (1 pulse per minute). I want a one-chip solution and I am not having a lot of luck with this. I do not want a ...
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Power divider coefficients
I'm new to power dividers component and I'm facing some doubts.
I should simulate a power divider in ADS of which I can consult the datasheet.
In ADS the power divider has the following parameters:
...
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109
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Voltage divider and ADC
I have been designing an adjustable voltage regulator using an LT1965 and DAC signal from a microcontroller as shown in the following picture. The output voltage is regulated between 1.8 and 5V using ...
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What is the function of a forward inverter and an inverted inverter in parallel in a digital circuit?
When I was simulating a divider using two D-latch as shown below (two D-latches in series,) I found that the circuit in the red rectangular is key to the differential D-latch.
In fact, the circuit in ...
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253
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Voltage divider formula
How to find value for both R1 and R2 for Vout=1.23 volts, where Pot=5K, Vin=4.5 - 12 volts?
simulate this circuit – Schematic created using CircuitLab
In reality, I want to adjust lm2596 buck ...
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119
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Power Supply of op-amp [duplicate]
Is there any problem if I supply an op-amp with a voltage divider?
I tried to supply an INA 128 op-amp with 15 V coming from a voltage divider. INA 128 used to do a substraction between 2 signals but ...
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3
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138
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Position of voltage divider relative to measured voltage and analog input
I am designing a PCB that includes a resistor voltage divider to measure the output voltage of a regulator. I am aware, that position of some components on the PCB may affect the performance and ...
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225
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Resistive divider as resistors approach 0 ohms
Resistive divider when R1 = R2, split voltage in half because V = IR, and resistors in series add as Rtot = R1 + R2. It seems like this must break down as R1/2 approach 0 ohms. Anyone have a good ...
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Capacitive voltage divider question
I see a few discussions on this but cannot really find the "definitive" answer.
I am building an audio amp and have two modules, one requires 18-0-18V AC and the other 12-0V AC, the 12V ...
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346
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ESP32 Input Voltage Divider, Concept
Thank you for reading. I have read many other voltage divider explanations and calculators on this site as well as the web.
My application is using a voltage divider to lower a possible 5 V signal (...
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behavior of a pipelined divider
Divider can be made combinational, which uses more logic gates..
Divider can be made sequential, the throughput may stay the same, i.e. use as many stages
as the width of the dividend (assuming width ...
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Warning: Gated clock check: Net ... is a gated clock net sourced by a combinatorial pin... using clock divider with Basys3 FPGA
I am trying to use a divider in order to make a modulus 10 counter on a Basys3 FPGA. The frequency of the FPGA's clock is 100 Mhz.
I am getting the following warning when I try to use the clock ...
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3
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744
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Clock Divider in VHDL Code
I have a question about the process that I wrote to divider a 1MHz clock down to a 10kHz clock.
I don't know why my code always splits up like it does below, if someone can edit it to look better and ...
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