Questions tagged [dll]

A Delay Locked Loop, a circuit that uses a voltage controlled delay chain in a feedback loop. The control circuit compares the delayed version of one signal with another signal and attempts to match the edges to make the two signal line up temporally.

Filter by
Sorted by
Tagged with
0
votes
0answers
17 views

How is the DLL used in MIPI C-PHY or D-PHY?

I guess the title says it all. I can't seem to find how exactly the Delay Locked Loop (DLL) is used inside in one of the MIPI PHYs. Thanks.
0
votes
1answer
82 views

Remove time gaps before chip select disabled on FTDI

When using FTDI FT2232H in SPI mode, there are relative short time gaps (~2 ms) between positions where clocks are stopped and chip select is disabled. But if data transmission have high speed rate, ...
0
votes
1answer
3k views

How to create variable clock frequency source in Cadence Virtuoso?

I am working on Delay Locked loop Project. I want to check the lock range of the dll. I am using vpulse for clock but by giving parameters clock period, clock width, rising time, falling time. It ...
1
vote
1answer
636 views

How the delay locked loop (DLL) align the clock?

The delay locked loop is used for align the clock in integrated circuits. In the IC there are no of flip flops and other devices. I want to know that how the DLL align the no of clocks going to ...
2
votes
0answers
71 views

Intermittent control signal injection clock sync

I have a big challenge in my design to overcome: I need clock frequency accuracy of <0.2ppm with incredibly low power consumption. What we are doing currently is, using a 3G transceiver' baseband ...
25
votes
3answers
20k views

What is the difference between a PLL and a DLL?

Phase Locked Loops (PLL's) and Delay Locked Loops (DLL) are used in various applications but there isn't yet a salient discussion of the key aspects of these circuits, how they operate, in what ...