Questions tagged [dram]
The dram tag has no usage guidance.
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STM32 RAM memory write HARD FAULT
I'm using STM32H755ZIT6 and I do have a global array in main.c file of CortexM7 :
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Counting up/shifting right, counting down/shifting left 4164 DRAM addresses using TTL/CMOS
I'm working on a design that uses 4164 (64kb x 1 bit) DRAM with 8 addresses (0-7), and I would like to be able to utilize a TTL/CMOS counter or shift register to make the data output count down/go in ...
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Interpreting RAM diagnostic results (E-mu Emax 2 digital sampling keyboard)
I have a broken E-mu Emax 2 digital sampling keyboard (1989). I ran the unit's internal diagnostic but need help interpreting the results, which indicate a faulty DRAM chip (KM44C256BP-8, of which ...
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DRAM destructive read
As far as I understand, i can describe the DRAM read sequence as follows:
Precharge the bitline (BL) to 0.5VDD
Turn on the access transistor
The BL voltage changes to 0.5VDD ± ε
The voltage level at ...
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Why does this vintage DRAM chip enable circuit require such a beefy resistor?
This is a small part of a mid-1970s chip enable circuit for a set of DRAMs. The DRAMs are TI's TMS4060 part (aka the Intel 2107 aka several others), and are 4096x1. So a typical bank requires 8 of ...
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How do I use ideal MOSFET model in LTspice? or How do I set voltage in node without voltage source?
I want to simulate the principle of 1T1C DRAM cell. But if I model voltage source in Bit line, bit-line voltage is set by its input signal. So I want to seperate bit line, using ideal MOSFET component,...
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Identify 64k x 8 bit DRAM in DIP-24N from the pinout
Unfortunately, I don't have the photo of the IC or any reference to it. All I have is a high-resolution photo of a PCB with unpopulated footprint where this IC should fit. It is wired in parallel to a ...
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Modern DDR4 memory access latency system analysis
The memory access latency for the Intel Core i7-11800H (source: chipsandcheese, cpu latency for Intel Core i7-11800H), using DDR4-3200, reveals specific timings: 1 ns for L1, 3 ns for L2, and 13 ns ...
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Memory Capacity and Memory Addresses
According to this site, in Table2, HBM(HBM2e) has a capacity of 8Gb = 2^33 bits per channel. Here, it has a 24-bit address consisting of 4 bits from the Bank address BA[3:0], 15 bits from the Row ...
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Why CPU DDR Memory Controller Has 2 Clock Outputs?
I'm trying to understand the ddr structure for the iMX6 Rex Module .
The cpu used is the MCIMX6Q5EYM10AC model from the NXP i.mx quad series.
MCIMX6Q5EYM10AC Datasheet
iMX6 Rex Module Shematics
A ...
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DRAM Memory : How is data stored from the HDD to DRAM? [closed]
When storing data from HDD to DRAM, is one large data block (e.g., 8 bytes) stored in one chip? Or is it distributed among multiple chips in a DIMM? If it is distributed, how many bytes of consecutive ...
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Why are the challenges in using SRAM over DRAM for main memory?
Historically, when compared to DRAM (dynamic ram), SRAM (static ram) is more expensive with a lower density, but it's much faster and more efficient. As a result, SRAM is reserved for devices, such as ...
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"32 bit memory" meaning
While looking at a datasheet about an NXP ARM CPU, I saw that the DRAM controller could support this
Memory types: LPDDR4
• Two channels of 32-bit memory:
• LPDDR4 up to 1.6 GHz
When it says two ...
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What percentage of a DRAM cell size is occupied by the transistor and/or the capacitor?
Assuming that we have a 1T1C DRAM cell manufactured at 22nm process. Based on this we can have an idea about the cell area (0.026 um^2 in this case). However, I could not find specific information ...
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NMOS is high when gate is low
I’m trying to simulate DRAM with N-MOSFETs with row and column selecting logic. When I select my column, which is connected to the source of an N-MOSFET, the N-MOSFETs in that column all turn on, even ...
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Why is the burst order of DDR3 DRAM not sequential?
Based on the JEDEC DDR3 documentation as shown below, when we are reading with burst length of 8 and starting column address of 010 (0x2), the burst order will be <...
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In DRAM, why does the precharge operation come after the activate operation and not vice-versa?
Precharging sets the bit line voltage is set to Vdd/2. To read from a dynamic memory cell, the bit line voltage must be near Vdd/2 for the sense amplifier to amplify the data value correctly. Since ...
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Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?
Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-...
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Why hasn't DRAM speed kept up with CPU speed as technology improves?
In 1976, the Z80 processor ran at 2.5 MHz and a typical DRAM access time was 500 ns. Now, processors run at 4 GHz and DRAM access time is 50 ns. Thus, processors are over three orders of magnitude ...
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Why the current DRAM architecture synchronizes its timing in multiple banks?
While I'm studying the DRAM architecture for my processing-in-memory research, the current architecture groups multiple banks into a DRAM controller, and synchronizes the timing between these banks.
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What is DRAM Precharge?
I dont understand what is DRAM Precharge.
Is DRAM precharge used for reading the memory, is it applied before reading the row? or is it used closing the row access?
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DRAM Refresh Time
I am trying to understand, how can I calculate the refresh time of DRAM, if I consider that as my memory requirement, that I need is 32 DRAM chip of 1M * 1bit each to get 4MB Memory capacity. Each ...
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Instrumentation Tools for Collecting Data in DRAM accesses
We can use instrumentation tools, such as Pin tool, to collect memory accesses of an application running on a system. The type (read or write) and memory address can be collected. How about data? Can ...
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Calculation of capacitor of deep trench DRAM
If I know the depth of the trench L, the size of the DRAM node D and the thickness of oxide (say HfO2) T. How can I calculate the capacitor of a trench?
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Why do these resistors decouple the two databuses?
The ZX Spectrum is a computer with a Z80 accessing ROM and two separate areas of RAM, one of which is also accessed by a ULA which generates video. If the Z80 wants to access the video RAM, it may be ...
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What is the definition of power down in HBM memory?
Reading the datasheets, it says data still needs to be maintained during power down and thus controller can't keep a channel in power down longer than the defined refresh requirement of the DRAM.
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How to calculate the GDDR5 Capacity from this table?
How to get 4Gb capacity from this table?
I understand it this way:
(1) total address is 14 + 6 + 4 = 24. each address (atom) is 32bit. So total capacity = 2^24 * 32bits = 512 Mbit.
I am not sure where ...
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Additive latency for DRAM READ and WRITE commands [closed]
In TN-47-10 – DDR2 Posted CAS# Additive Latency Technical Note , what does it exactly mean by Additive latency (AL = 1) is only used for READ commands and will not affect WRITE command timing ?
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What are technical challenges of implementing DRAM memory modules on SBC like Raspberry PI?
I'm surprised to see no Single-Board Computer including Raspberry PI has memory modules for allow for flexible amount of memory (e.g. this review). And I have not found such discussions via web search,...
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How does Asynchronous DRAM perform self-timing
The original question was deemed lack of focus. This post is specifically about dram chip.
When DRAM controller talks to an asynchronous DRAM, how does DRAM itself know when a write is completed and ...
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DRAM RAS and CAS timing
Why RAS is still active when the column address is on the address bus?
I don't understand why RAS & CAS both should be active when column address in provided in address bus?
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Why for DDR3 driver with a low-impedance output undesirable?
I was reading Micron's TN-41-13 DDR3 Point-to-Point Design Support technical note. It says the following on page 7:
In point-to-point designs, the memory’s position is typically quite close to the ...
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Why is CAS latency mostly recognized in DRAM timing?
From what I know, it takes roughly these steps to read DRAM data:
Enable RAS signal, send the row address
Wait for some Time(tRCD), then enable CAS signal, send ...
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HyperRAM Linear Burst size throughput
Turned out to be a lengthy question, please feel free to skip and go directly to the questions
Intro
I am considering utilizing a HyperRAM in the next design, and studying the datasheet has lead me to ...
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How does radiation produce transient bit errors in DRAM?
Ionizing radiation can produce transient bit errors in volatile RAM. What is the exact mechanism by which this occurs?
E.g., is there a threshold energy level for a single photon or neutron to ...
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DDRx JEDEC Standard: Retention Time
Different scientific publications [1,2] mention that DDRx memory has a (data) retention time of 64 ms while on average each cell is refreshed every 7.8 us (tREFI). I want to know where this ...
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DRAM cells capacitor operation
I have a question about reading and writing operations.
Say if i wanted to read or write the column WL0, i would enable the WL0 lines.
For either a read of a write i would drive the bit lines to ...
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Why are DRAM cells laid out in a square with regards to demux size?
I'm reading the chapter about DRAM access (2.1.3) of the paper "What Every Programmer Should Know About Memory - Ulrich Drepper" and there's a certain snippet that I just can't make sense of....
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Why are SDRAM CAS latencies so high?
I don't understand why the CAS latency of modern DDR4 memory is so high. I have no trouble understanding why the RAS latency is as high as it is -- given the small amount of charge stored in each ...
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SDR over DDR memory in FPGA based design
I am designing a new project which demands the usage of DRAM. I have never interfaced with one before, so my knowledge is rather limited. By analyzing the requirements, it would be sufficient to go ...
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How is 1 bit transfered from RAM to a 1 bit register?
I've been reading on computer RAM and CPUs. I came to the conclusion that most RAM today use arrays of DRAM while CPU registers and caches use SRAM. 1 bit DRAM is a circuit with one capacitor and 1 ...
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DRAM Rank-Level Allocations
I want to do allocations on a specific DRAM rank. The smallest allocation unit in an OS such as Linux is at the page size ...
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Termination Requirements for DRAM
I am curious about how to wire DRAM to an SoC. What is required for optimal usage other than the net itself? I have seen conflicting information on if you should or should not use a termination ...
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Can i make dram using bjt transistors? [closed]
Is it possible to make dram using bjt's or is it only possible with mosfet's? If not why not? Is there an advantage in using mosfets instead of something like a bjt ?
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DDR: Is the real maximum speed half of what is advertised in datasheets?
Let's take a single 8-bit 200MHz DDR chip. All datasheets state that bandwidth is "up to" 400MB/s.
Because it's dual, data is read/written on both edges so yes, theoretical, it's 400MB/s.
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ddr: Is there any significant delta between the different strobes?
In a DDR memory, during a read, output data from the DDR is aligned on the strobe. There is one strobe per 8-bit:
UDQS/LDQS for a 16-bit-wide DDR
DQS[0-3] for a 32-bit-wide DDR
Is there any ...
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No terminations on point to point DDR3?
Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ...
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DRAM Self-Refresh not the Lowest Power Mode
I have a DDR3L Samsung DRAM on my Laptop. Based on page 23 of its datasheet, IDD6 or the ...
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Is an even number of DRAM chips required?
I want to design a microprocessor based board (NXP imx 8m). All the boards I've seen so far have an even number of DRAM chips. If I want 4GB of RAM, do I have to use two 2GB DRAM chips or can I use ...
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Can you get "raw" TFT display panels where you drive the gate and drain lines directly?
I am learning about different display types and how I might interface them with raw electronic components, e.g., TTL chips, op amps, function generators for scan line sawtooth, etc. CRT raster is ...
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