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DRAM destructive read

As far as I understand, i can describe the DRAM read sequence as follows: Precharge the bitline (BL) to 0.5VDD Turn on the access transistor The BL voltage changes to 0.5VDD ± ε The voltage level at ...
lemoncake's user avatar
24 votes
4 answers
4k views

Why does this vintage DRAM chip enable circuit require such a beefy resistor?

This is a small part of a mid-1970s chip enable circuit for a set of DRAMs. The DRAMs are TI's TMS4060 part (aka the Intel 2107 aka several others), and are 4096x1. So a typical bank requires 8 of ...
BZo's user avatar
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Analog DFE equalization circuit for LPDDR5

I have to design a DFE circuit for the LPDDR5 receiver. I have created a simple 1-tap DFE circuit that is shown in Razavi's article (link: https://ieeexplore.ieee.org/document/9694443 , figure 9), and ...
Kamal's user avatar
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1 vote
0 answers
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How do I use ideal MOSFET model in LTspice? or How do I set voltage in node without voltage source?

I want to simulate the principle of 1T1C DRAM cell. But if I model voltage source in Bit line, bit-line voltage is set by its input signal. So I want to seperate bit line, using ideal MOSFET component,...
Jungwan Noh's user avatar
1 vote
0 answers
41 views

Identify 64k x 8 bit DRAM in DIP-24N from the pinout

Unfortunately, I don't have the photo of the IC or any reference to it. All I have is a high-resolution photo of a PCB with unpopulated footprint where this IC should fit. It is wired in parallel to a ...
tpimh's user avatar
  • 513
0 votes
0 answers
172 views

Modern DDR4 memory access latency system analysis

The memory access latency for the Intel Core i7-11800H (source: chipsandcheese, cpu latency for Intel Core i7-11800H), using DDR4-3200, reveals specific timings: 1 ns for L1, 3 ns for L2, and 13 ns ...
Prajwal Rathnakar Hegde's user avatar
3 votes
1 answer
80 views

Memory Capacity and Memory Addresses

According to this site, in Table2, HBM(HBM2e) has a capacity of 8Gb = 2^33 bits per channel. Here, it has a 24-bit address consisting of 4 bits from the Bank address BA[3:0], 15 bits from the Row ...
cashew_nuts's user avatar
1 vote
0 answers
71 views

Why CPU DDR Memory Controller Has 2 Clock Outputs?

I'm trying to understand the ddr structure for the iMX6 Rex Module . The cpu used is the MCIMX6Q5EYM10AC model from the NXP i.mx quad series. MCIMX6Q5EYM10AC Datasheet iMX6 Rex Module Shematics A ...
Electronx's user avatar
  • 719
0 votes
2 answers
111 views

DRAM Memory : How is data stored from the HDD to DRAM? [closed]

When storing data from HDD to DRAM, is one large data block (e.g., 8 bytes) stored in one chip? Or is it distributed among multiple chips in a DIMM? If it is distributed, how many bytes of consecutive ...
C.Ky's user avatar
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7 votes
2 answers
937 views

Why are the challenges in using SRAM over DRAM for main memory?

Historically, when compared to DRAM (dynamic ram), SRAM (static ram) is more expensive with a lower density, but it's much faster and more efficient. As a result, SRAM is reserved for devices, such as ...
user148298's user avatar
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2 answers
83 views

"32 bit memory" meaning

While looking at a datasheet about an NXP ARM CPU, I saw that the DRAM controller could support this Memory types: LPDDR4 • Two channels of 32-bit memory: • LPDDR4 up to 1.6 GHz When it says two ...
Nathan Jiang's user avatar
4 votes
1 answer
483 views

What percentage of a DRAM cell size is occupied by the transistor and/or the capacitor?

Assuming that we have a 1T1C DRAM cell manufactured at 22nm process. Based on this we can have an idea about the cell area (0.026 um^2 in this case). However, I could not find specific information ...
Arkoudinos's user avatar
1 vote
1 answer
80 views

NMOS is high when gate is low

I’m trying to simulate DRAM with N-MOSFETs with row and column selecting logic. When I select my column, which is connected to the source of an N-MOSFET, the N-MOSFETs in that column all turn on, even ...
Sss's user avatar
  • 11
3 votes
1 answer
560 views

Why is the burst order of DDR3 DRAM not sequential?

Based on the JEDEC DDR3 documentation as shown below, when we are reading with burst length of 8 and starting column address of 010 (0x2), the burst order will be <...
hontou_'s user avatar
  • 1,074
3 votes
1 answer
547 views

In DRAM, why does the precharge operation come after the activate operation and not vice-versa?

Precharging sets the bit line voltage is set to Vdd/2. To read from a dynamic memory cell, the bit line voltage must be near Vdd/2 for the sense amplifier to amplify the data value correctly. Since ...
jayded-bee's user avatar
5 votes
1 answer
1k views

Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?

Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-...
jayded-bee's user avatar
4 votes
1 answer
306 views

Why hasn't DRAM speed kept up with CPU speed as technology improves?

In 1976, the Z80 processor ran at 2.5 MHz and a typical DRAM access time was 500 ns. Now, processors run at 4 GHz and DRAM access time is 50 ns. Thus, processors are over three orders of magnitude ...
Ken Shirriff's user avatar
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1 vote
1 answer
79 views

Why the current DRAM architecture synchronizes its timing in multiple banks?

While I'm studying the DRAM architecture for my processing-in-memory research, the current architecture groups multiple banks into a DRAM controller, and synchronizes the timing between these banks. ...
bdh0404's user avatar
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5 votes
1 answer
2k views

What is DRAM Precharge?

I dont understand what is DRAM Precharge. Is DRAM precharge used for reading the memory, is it applied before reading the row? or is it used closing the row access?
Aakash's user avatar
  • 59
1 vote
1 answer
504 views

DRAM Refresh Time

I am trying to understand, how can I calculate the refresh time of DRAM, if I consider that as my memory requirement, that I need is 32 DRAM chip of 1M * 1bit each to get 4MB Memory capacity. Each ...
Niraj Jain's user avatar
-1 votes
1 answer
66 views

Instrumentation Tools for Collecting Data in DRAM accesses

We can use instrumentation tools, such as Pin tool, to collect memory accesses of an application running on a system. The type (read or write) and memory address can be collected. How about data? Can ...
Arghavan Mohammadhassani's user avatar
0 votes
1 answer
553 views

Calculation of capacitor of deep trench DRAM

If I know the depth of the trench L, the size of the DRAM node D and the thickness of oxide (say HfO2) T. How can I calculate the capacitor of a trench?
dickdou's user avatar
  • 11
4 votes
1 answer
336 views

Why do these resistors decouple the two databuses?

The ZX Spectrum is a computer with a Z80 accessing ROM and two separate areas of RAM, one of which is also accessed by a ULA which generates video. If the Z80 wants to access the video RAM, it may be ...
Omar and Lorraine's user avatar
0 votes
1 answer
121 views

What is the definition of power down in HBM memory?

Reading the datasheets, it says data still needs to be maintained during power down and thus controller can't keep a channel in power down longer than the defined refresh requirement of the DRAM. ...
neoserdes's user avatar
0 votes
1 answer
281 views

How to calculate the GDDR5 Capacity from this table?

How to get 4Gb capacity from this table? I understand it this way: (1) total address is 14 + 6 + 4 = 24. each address (atom) is 32bit. So total capacity = 2^24 * 32bits = 512 Mbit. I am not sure where ...
neoserdes's user avatar
-2 votes
1 answer
330 views

Additive latency for DRAM READ and WRITE commands [closed]

In TN-47-10 – DDR2 Posted CAS# Additive Latency Technical Note , what does it exactly mean by Additive latency (AL = 1) is only used for READ commands and will not affect WRITE command timing ?
kevin998x's user avatar
  • 413
1 vote
4 answers
247 views

What are technical challenges of implementing DRAM memory modules on SBC like Raspberry PI?

I'm surprised to see no Single-Board Computer including Raspberry PI has memory modules for allow for flexible amount of memory (e.g. this review). And I have not found such discussions via web search,...
Martian2020's user avatar
2 votes
1 answer
202 views

How does Asynchronous DRAM perform self-timing

The original question was deemed lack of focus. This post is specifically about dram chip. When DRAM controller talks to an asynchronous DRAM, how does DRAM itself know when a write is completed and ...
Oliver Young's user avatar
0 votes
2 answers
685 views

DRAM RAS and CAS timing

Why RAS is still active when the column address is on the address bus? I don't understand why RAS & CAS both should be active when column address in provided in address bus?
akan's user avatar
  • 1
0 votes
1 answer
213 views

Why for DDR3 driver with a low-impedance output undesirable?

I was reading Micron's TN-41-13 DDR3 Point-to-Point Design Support technical note. It says the following on page 7: In point-to-point designs, the memory’s position is typically quite close to the ...
soul z's user avatar
  • 29
0 votes
1 answer
185 views

Why is CAS latency mostly recognized in DRAM timing?

From what I know, it takes roughly these steps to read DRAM data: Enable RAS signal, send the row address Wait for some Time(tRCD), then enable CAS signal, send ...
user239216's user avatar
0 votes
0 answers
301 views

HyperRAM Linear Burst size throughput

Turned out to be a lengthy question, please feel free to skip and go directly to the questions Intro I am considering utilizing a HyperRAM in the next design, and studying the datasheet has lead me to ...
Mr.Y's user avatar
  • 143
0 votes
1 answer
427 views

How does radiation produce transient bit errors in DRAM?

Ionizing radiation can produce transient bit errors in volatile RAM. What is the exact mechanism by which this occurs? E.g., is there a threshold energy level for a single photon or neutron to ...
feetwet's user avatar
  • 2,402
1 vote
1 answer
185 views

DDRx JEDEC Standard: Retention Time

Different scientific publications [1,2] mention that DDRx memory has a (data) retention time of 64 ms while on average each cell is refreshed every 7.8 us (tREFI). I want to know where this ...
Patrick's user avatar
  • 121
0 votes
1 answer
203 views

DRAM cells capacitor operation

I have a question about reading and writing operations. Say if i wanted to read or write the column WL0, i would enable the WL0 lines. For either a read of a write i would drive the bit lines to ...
Tech Visionary's user avatar
2 votes
2 answers
902 views

Why are DRAM cells laid out in a square with regards to demux size?

I'm reading the chapter about DRAM access (2.1.3) of the paper "What Every Programmer Should Know About Memory - Ulrich Drepper" and there's a certain snippet that I just can't make sense of....
AMVaddictionist's user avatar
7 votes
1 answer
635 views

Why are SDRAM CAS latencies so high?

I don't understand why the CAS latency of modern DDR4 memory is so high. I have no trouble understanding why the RAS latency is as high as it is -- given the small amount of charge stored in each ...
Dolda2000's user avatar
  • 965
2 votes
1 answer
170 views

SDR over DDR memory in FPGA based design

I am designing a new project which demands the usage of DRAM. I have never interfaced with one before, so my knowledge is rather limited. By analyzing the requirements, it would be sufficient to go ...
Mr.Y's user avatar
  • 143
2 votes
2 answers
313 views

How is 1 bit transfered from RAM to a 1 bit register?

I've been reading on computer RAM and CPUs. I came to the conclusion that most RAM today use arrays of DRAM while CPU registers and caches use SRAM. 1 bit DRAM is a circuit with one capacitor and 1 ...
user123's user avatar
  • 121
1 vote
1 answer
326 views

DRAM Rank-Level Allocations

I want to do allocations on a specific DRAM rank. The smallest allocation unit in an OS such as Linux is at the page size ...
TheAhmad's user avatar
  • 121
0 votes
0 answers
88 views

Termination Requirements for DRAM

I am curious about how to wire DRAM to an SoC. What is required for optimal usage other than the net itself? I have seen conflicting information on if you should or should not use a termination ...
solarmainframe's user avatar
2 votes
1 answer
397 views

Can i make dram using bjt transistors? [closed]

Is it possible to make dram using bjt's or is it only possible with mosfet's? If not why not? Is there an advantage in using mosfets instead of something like a bjt ?
greatisgreat's user avatar
1 vote
3 answers
300 views

DDR: Is the real maximum speed half of what is advertised in datasheets?

Let's take a single 8-bit 200MHz DDR chip. All datasheets state that bandwidth is "up to" 400MB/s. Because it's dual, data is read/written on both edges so yes, theoretical, it's 400MB/s. ...
gregoiregentil's user avatar
0 votes
1 answer
104 views

ddr: Is there any significant delta between the different strobes?

In a DDR memory, during a read, output data from the DDR is aligned on the strobe. There is one strobe per 8-bit: UDQS/LDQS for a 16-bit-wide DDR DQS[0-3] for a 32-bit-wide DDR Is there any ...
gregoiregentil's user avatar
4 votes
1 answer
678 views

No terminations on point to point DDR3?

Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ...
pcbguy's user avatar
  • 83
1 vote
0 answers
1k views

DRAM Self-Refresh not the Lowest Power Mode

I have a DDR3L Samsung DRAM on my Laptop. Based on page 23 of its datasheet, IDD6 or the ...
TheAhmad's user avatar
  • 121
0 votes
1 answer
73 views

Is an even number of DRAM chips required?

I want to design a microprocessor based board (NXP imx 8m). All the boards I've seen so far have an even number of DRAM chips. If I want 4GB of RAM, do I have to use two 2GB DRAM chips or can I use ...
kadhem Alabdulmuhsin's user avatar
2 votes
2 answers
421 views

Can you get "raw" TFT display panels where you drive the gate and drain lines directly?

I am learning about different display types and how I might interface them with raw electronic components, e.g., TTL chips, op amps, function generators for scan line sawtooth, etc. CRT raster is ...
Gunther Schadow's user avatar
2 votes
2 answers
622 views

Is DRAM burst mode compatible with bank interleaving?

I am trying to understand how DRAM burst mode is compatible with bank interleaving. Once a row within a DRAM memory array has been activated, sensed and buffered, according to the strobed row address,...
Drummy's user avatar
  • 559
-2 votes
1 answer
95 views

EEPROM converted to DRAM?

Can we use a EEPROM cell for DRAM ? simulate this circuit – Schematic created using CircuitLab This is an EEPROM cell. Can we use multiple cells of this type to create a DRAM?
Jelly Strawberry's user avatar