Questions tagged [dram]

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What is the definition of power down in HBM memory?

Reading the datasheets, it says data still needs to be maintained during power down and thus controller can't keep a channel in power down longer than the defined refresh requirement of the DRAM. ...
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29 views

Why High Bandwidth Memory RDQS and WDQS need both preamble and postamble?

RDQS is the strobe for Data pin (DQ) in read mode. WDQS is the strobe for data pin (DQ) in write mode. I am curious why the system needs either one of them? the preamble of RDQS/WDQS can be used for ...
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38 views

How to calculate the GDDR5 Capacity from this table?

How to get 4Gb capacity from this table? I understand it this way: (1) total address is 14 + 6 + 4 = 24. each address (atom) is 32bit. So total capacity = 2^24 * 32bits = 512 Mbit. I am not sure where ...
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1answer
37 views

Additive latency for DRAM READ and WRITE commands [closed]

In TN-47-10 – DDR2 Posted CAS# Additive Latency Technical Note , what does it exactly mean by Additive latency (AL = 1) is only used for READ commands and will not affect WRITE command timing ?
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4answers
118 views

What are technical challenges of implementing DRAM memory modules on SBC like Raspberry PI?

I'm surprised to see no Single-Board Computer including Raspberry PI has memory modules for allow for flexible amount of memory (e.g. this review). And I have not found such discussions via web search,...
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1answer
76 views

How does Asynchronous DRAM perform self-timing

The original question was deemed lack of focus. This post is specifically about dram chip. When DRAM controller talks to an asynchronous DRAM, how does DRAM itself know when a write is completed and ...
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2answers
54 views

DRAM RAS and CAS timing

Why RAS is still active when the column address is on the address bus? I don't understand why RAS & CAS both should be active when column address in provided in address bus?
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1answer
45 views

Why for DDR3 driver with a low-impedance output undesirable?

I was reading Micron Point to point DDR3 technical note. It says as follows: In point-to-point designs, the memory’s position is typically quite close to the controller, which results in short data ...
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1answer
67 views

Why is CAS latency mostly recognized in DRAM timing?

From what I know, it takes roughly these steps to read DRAM data: Enable RAS signal, send the row address Wait for some Time(tRCD), then enable CAS signal, send ...
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80 views

HyperRAM Linear Burst size throughput

Turned out to be a lengthy question, please feel free to skip and go directly to the questions Intro I am considering utilizing a HyperRAM in the next design, and studying the datasheet has lead me to ...
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1answer
171 views

How does radiation produce transient bit errors in DRAM?

Ionizing radiation can produce transient bit errors in volatile RAM. What is the exact mechanism by which this occurs? E.g., is there a threshold energy level for a single photon or neutron to ...
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1answer
54 views

DDRx JEDEC Standard: Retention Time

Different scientific publications [1,2] mention that DDRx memory has a (data) retention time of 64 ms while on average each cell is refreshed every 7.8 us (tREFI). I want to know where this ...
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1answer
91 views

DRAM cells capacitor operation

I have a question about reading and writing operations. Say if i wanted to read or write the column WL0, i would enable the WL0 lines. For either a read of a write i would drive the bit lines to ...
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55 views

DRAM, multi-channel, memory access

I'm looking for a way, under any configuration/OS(windows or linux)/programming language you suggest to simultaneously access memory addresses, that are under different channels, meaning the access ...
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2answers
162 views

Why are DRAM cells laid out in a square with regards to demux size?

I'm reading the chapter about DRAM access (2.1.3) of the paper "What Every Programmer Should Know About Memory - Ulrich Drepper" and there's a certain snippet that I just can't make sense of....
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1answer
282 views

Why are SDRAM CAS latencies so high?

I don't understand why the CAS latency of modern DDR4 memory is so high. I have no trouble understanding why the RAS latency is as high as it is -- given the small amount of charge stored in each ...
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1answer
100 views

SDR over DDR memory in FPGA based design

I am designing a new project which demands the usage of DRAM. I have never interfaced with one before, so my knowledge is rather limited. By analyzing the requirements, it would be sufficient to go ...
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2answers
167 views

How is 1 bit transfered from RAM to a 1 bit register?

I've been reading on computer RAM and CPUs. I came to the conclusion that most RAM today use arrays of DRAM while CPU registers and caches use SRAM. 1 bit DRAM is a circuit with one capacitor and 1 ...
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1answer
165 views

DRAM Rank-Level Allocations

I want to do allocations on a specific DRAM rank. The smallest allocation unit in an OS such as Linux is at the page size ...
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49 views

Termination Requirements for DRAM

I am curious about how to wire DRAM to an SoC. What is required for optimal usage other than the net itself? I have seen conflicting information on if you should or should not use a termination ...
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1answer
195 views

Can i make dram using bjt transistors? [closed]

Is it possible to make dram using bjt's or is it only possible with mosfet's? If not why not? Is there an advantage in using mosfets instead of something like a bjt ?
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3answers
168 views

DDR: Is the real maximum speed half of what is advertised in datasheets?

Let's take a single 8-bit 200MHz DDR chip. All datasheets state that bandwidth is "up to" 400MB/s. Because it's dual, data is read/written on both edges so yes, theoretical, it's 400MB/s. ...
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1answer
50 views

ddr: Is there any significant delta between the different strobes?

In a DDR memory, during a read, output data from the DDR is aligned on the strobe. There is one strobe per 8-bit: UDQS/LDQS for a 16-bit-wide DDR DQS[0-3] for a 32-bit-wide DDR Is there any ...
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1answer
247 views

No terminations on point to point DDR3?

Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ...
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229 views

DRAM Self-Refresh not the Lowest Power Mode

I have a DDR3L Samsung DRAM on my Laptop. Based on page 23 of its datasheet, IDD6 or the ...
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1answer
61 views

Is an even number of DRAM chips required?

I want to design a microprocessor based board (NXP imx 8m). All the boards I've seen so far have an even number of DRAM chips. If I want 4GB of RAM, do I have to use two 2GB DRAM chips or can I use ...
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2answers
211 views

Can you get "raw" TFT display panels where you drive the gate and drain lines directly?

I am learning about different display types and how I might interface them with raw electronic components, e.g., TTL chips, op amps, function generators for scan line sawtooth, etc. CRT raster is ...
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2answers
196 views

Is DRAM burst mode compatible with bank interleaving?

I am trying to understand how DRAM burst mode is compatible with bank interleaving. Once a row within a DRAM memory array has been activated, sensed and buffered, according to the strobed row address,...
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1answer
58 views

EEPROM converted to DRAM?

Can we use a EEPROM cell for DRAM ? simulate this circuit – Schematic created using CircuitLab This is an EEPROM cell. Can we use multiple cells of this type to create a DRAM?
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1answer
657 views

Why cant clock be directly used instead of DQS in DDR during read and write

I have been reading about DDR lately and I am not able to understand the exact use of the DQS signal. The timing diagrams show dqs in phase with clock so why cant the clock only be used for the write ...
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74 views

open source SATA to DDR2 SDRAM adater

I want to learn how computer memory sticks can be used as secondary storage using some intermediate FPGA for data processing. Actually I want to design a PCB myself. I'm good with PCB designing but I ...
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2answers
190 views

How to reset flip flop in ATF16V8?

I'm designing a Z80 microcomputer with dynamic memory (DRAM), and I want to control the memory with 3 chips; an ATF16V8 Generic-Array Logic, and 2 74LS157 quad 2:1 multiplexers. The logic diagram of ...
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1answer
243 views

Why do we need interleaved memory?

I am trying to understand the DRAM working paradigm. I just read this article about interleaved memory. It says: Interleaved memory results in contiguous reads (which are common both in ...
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1answer
263 views

The detailed working steps of the DRAM 3T1C cell?

This question is related to this one. But the focus is a little different so I put it here. I tried to understand the detailed working steps of below circuit. It is an old 3T1C DRAM cell circuit. ...
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196 views

Why is reading the 3T1C DRAM cell not destructive?

Could anyone help explain how the above 3T1C DRAM cell works? T means transistor and C means capacitor. Why is reading it not destructive?
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1answer
167 views

DDR4 board bringup issue

I am struggling with a DDR4 related board bringup issue. Can anyone out there recognise what the problem is by studying the attached memory dumps? The memory dump is from Preboot loader PB31 area of ...
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1answer
41 views

Can I use IS42SM16160K DRAM instead of IS42S16400 DRAM?

I have designed a custom board based on the STM32F4 controller and IS42S16400 DRAM. For some reason, I want to use IS42SM16160K mobile DRAM instead. Should there be a change in programming and ...
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1answer
119 views

DRAM late and early read and write

For read operation in DRAM, perform early read mean OE low before CAS is low so doesn't this mean that you just read in junk data ? For write operation, i don't think there any problem with early ...
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58 views

DRAM Memory Lines

I have been trying to understand DDR and DRAM memories and stumbled upon this video In this video, from 20:00 to 23:00 he tells that the 8kb row buffer lines, actually come out as 64b and this 64b ...
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2answers
4k views

What is the difference between DRAM channel and DRAM Rank?

Can someone explain me the terms : DRAM Rank and a DRAM Channel is simple terms. I went through this PDF and I was not able to understand the DRAM Organisation/architecture on page 3 and page 11. Can ...
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2answers
121 views

Running code from different storage

So i know this question is being asked almost everyday on thousands of forums, but i am still going to ask that same question but with a different intent. Question #1: As an example lets use linux ...
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1answer
250 views

LPDDR4 pre-fetch

In the JEDEC LPDDR4 spec it is mentioned that LPDDR4 DRAM can support burst length 32(BL32) and also the LPDDR4 DRAM architecture is 16n prefetch. I want to know how burst length 32 be possible with ...
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1answer
192 views

Latch-based sense amplifier design using CADENCE Virtuoso 65 nm technology

I am trying to design a latch-based sense amplifier to sense about 55mV voltage difference using 65nm technolgy, it takes differential input, and should get from it differential output too where it ...
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1answer
47 views

Where the appropriate word size is selected for the operand?

This question is about a 32 bit Intel Chip using x86 assembly. My question specifically is what happens when you do the mov reg, mem instruction where the memory operand is a word (16 bits) from DRAM. ...
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1answer
2k views

RAM Row and Column Decoders

I keep seeing similar diagrams of RAM like this abstract picture of a simplified RAM Layout. So I just arbitrarily selected this picture but my question is about this layout in general. My ...
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2answers
369 views

What design differences make ram faster than ssd for read/write [closed]

I understand that RAM is connected directly to the CPU via a high bandwidth bus, and SSD is a peripheral, but my assumption is that there are also electrical design differences (e.g. memory cell ...
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1answer
126 views

DRAM in a FPGA - Image Sensor design

I am designing the simplest form of a camera: an FPGA that interfaces an image sensor and sends the acquired data to the host device via USB 3.0. There is no processing on the FPGA, it is used for ...
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0answers
54 views

When do we actually need bank interleaving?

Since common DRAM chips support burst transfer and hardware page size (row size) in a bank is quite large, we can amortize the charging & activating time over bytes in a long burst transfer. I ...
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2answers
1k views

GPU vs CPU on chip memory

There has been a fairly wide ranging discussion as to why it is difficult to combine memory / CPU logic on the same die (yield issue compounding, different processes, different clock-frequency, ...
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1answer
6k views

What is the difference between BRAM and distributed RAM [closed]

I am doing a project on BRAM implementation. What is the difference between Block RAM and Distributed RAM on FPGA in terms of implementation, area, speed etc? Which is better?