Questions tagged [dram]

The tag has no usage guidance.

Filter by
Sorted by
Tagged with
0
votes
0answers
39 views

DRAM Self-Refresh not the Lowest Power Mode

I have a DDR3L Samsung DRAM on my Laptop. Based on page 23 of its datasheet, IDD6 or the ...
0
votes
0answers
26 views

DDR3 AC characteristics

What is the meaning behind different AC input levels such as AC120, AC135, AC175 etc? I understand that AC_X means the level is Vref + X mV. And I also understand that the setup time is defined with ...
0
votes
1answer
52 views

Is an even number of DRAM chips required?

I want to design a microprocessor based board (NXP imx 8m). All the boards I've seen so far have an even number of DRAM chips. If I want 4GB of RAM, do I have to use two 2GB DRAM chips or can I use ...
1
vote
1answer
59 views

Can you get “raw” TFT display panels where you drive the gate and drain lines directly?

I am learning about different display types and how I might interface them with raw electronic components, e.g., TTL chips, op amps, function generators for scan line sawtooth, etc. CRT raster is ...
1
vote
2answers
35 views

Is DRAM burst mode compatible with bank interleaving?

I am trying to understand how DRAM burst mode is compatible with bank interleaving. Once a row within a DRAM memory array has been activated, sensed and buffered, according to the strobed row address,...
-2
votes
1answer
48 views

EEPROM converted to DRAM?

Can we use a EEPROM cell for DRAM ? simulate this circuit – Schematic created using CircuitLab This is an EEPROM cell. Can we use multiple cells of this type to create a DRAM?
0
votes
1answer
26 views

How to design 1T-1C DRAM circuit in spice design tools, such as LTSPICE?

I have been trying to design a DRAM cell using the LTSPICE MODEL tool. The DRAM that I want to design is of 2nd GENERATION, i.e, 1t-1c dram cell. But whenever I design digit line it states the line is ...
0
votes
0answers
42 views

On DRAM timing, why tWTR is larger than tRTW?

If I understand correctly, tWTR includes both bus turnaround time (between memory controller and DIMM) and safety margin to make sure that data are written to target row buffer before read operation ...
0
votes
1answer
95 views

Why cant clock be directly used instead of DQS in DDR during read and write

I have been reading about DDR lately and I am not able to understand the exact use of the DQS signal. The timing diagrams show dqs in phase with clock so why cant the clock only be used for the write ...
0
votes
0answers
56 views

open source SATA to DDR2 SDRAM adater

I want to learn how computer memory sticks can be used as secondary storage using some intermediate FPGA for data processing. Actually I want to design a PCB myself. I'm good with PCB designing but I ...
1
vote
2answers
45 views

How to reset flip flop in ATF16V8?

I'm designing a Z80 microcomputer with dynamic memory (DRAM), and I want to control the memory with 3 chips; an ATF16V8 Generic-Array Logic, and 2 74LS157 quad 2:1 multiplexers. The logic diagram of ...
0
votes
0answers
34 views

Find capacitor voltage for dram cell!

I have a mosfet with Vin connected to drain e constant voltage applied on Gate and a capacitor between the source and ground. I believe this is a dram cell. Vo=0 for t<0,Vg=Vstep(constant) and Vth=...
0
votes
1answer
90 views

Why do we need interleaved memory?

I am trying to understand the DRAM working paradigm. I just read this article about interleaved memory. It says: Interleaved memory results in contiguous reads (which are common both in ...
1
vote
1answer
106 views

The detailed working steps of the DRAM 3T1C cell?

This question is related to this one. But the focus is a little different so I put it here. I tried to understand the detailed working steps of below circuit. It is an old 3T1C DRAM cell circuit. ...
0
votes
2answers
85 views

Why is reading the 3T1C DRAM cell not destructive?

Could anyone help explain how the above 3T1C DRAM cell works? T means transistor and C means capacitor. Why is reading it not destructive?
2
votes
1answer
111 views

DDR4 board bringup issue

I am struggling with a DDR4 related board bringup issue. Can anyone out there recognise what the problem is by studying the attached memory dumps? The memory dump is from Preboot loader PB31 area of ...
0
votes
0answers
30 views

DRAM inspired edge-triggered D-type flip-flop

I was thinking about using DRAM cells as edge-triggered D-type flip-flop, I put the elements in falstad circuit simulator and it worked, but I am not sure on how would this translate to an actual ...
0
votes
1answer
32 views

Can I use IS42SM16160K DRAM instead of IS42S16400 DRAM?

I have designed a custom board based on the STM32F4 controller and IS42S16400 DRAM. For some reason, I want to use IS42SM16160K mobile DRAM instead. Should there be a change in programming and ...
-1
votes
1answer
59 views

DRAM late and early read and write

For read operation in DRAM, perform early read mean OE low before CAS is low so doesn't this mean that you just read in junk data ? For write operation, i don't think there any problem with early ...
0
votes
0answers
51 views

DRAM Memory Lines

I have been trying to understand DDR and DRAM memories and stumbled upon this video In this video, from 20:00 to 23:00 he tells that the 8kb row buffer lines, actually come out as 64b and this 64b ...
0
votes
2answers
654 views

What is the difference between DRAM channel and DRAM Rank?

Can someone explain me the terms : DRAM Rank and a DRAM Channel is simple terms. I went through this PDF and I was not able to understand the DRAM Organisation/architecture on page 3 and page 11. Can ...
0
votes
2answers
59 views

Running code from different storage

So i know this question is being asked almost everyday on thousands of forums, but i am still going to ask that same question but with a different intent. Question #1: As an example lets use linux ...
0
votes
1answer
99 views

LPDDR4 pre-fetch

In the JEDEC LPDDR4 spec it is mentioned that LPDDR4 DRAM can support burst length 32(BL32) and also the LPDDR4 DRAM architecture is 16n prefetch. I want to know how burst length 32 be possible with ...
0
votes
1answer
124 views

Latch-based sense amplifier design using CADENCE Virtuoso 65 nm technology

I am trying to design a latch-based sense amplifier to sense about 55mV voltage difference using 65nm technolgy, it takes differential input, and should get from it differential output too where it ...
0
votes
1answer
46 views

Where the appropriate word size is selected for the operand?

This question is about a 32 bit Intel Chip using x86 assembly. My question specifically is what happens when you do the mov reg, mem instruction where the memory operand is a word (16 bits) from DRAM. ...
2
votes
1answer
902 views

RAM Row and Column Decoders

I keep seeing similar diagrams of RAM like this abstract picture of a simplified RAM Layout. So I just arbitrarily selected this picture but my question is about this layout in general. My ...
0
votes
2answers
99 views

What design differences make ram faster than ssd for read/write [closed]

I understand that RAM is connected directly to the CPU via a high bandwidth bus, and SSD is a peripheral, but my assumption is that there are also electrical design differences (e.g. memory cell ...
0
votes
1answer
106 views

DRAM in a FPGA - Image Sensor design

I am designing the simplest form of a camera: an FPGA that interfaces an image sensor and sends the acquired data to the host device via USB 3.0. There is no processing on the FPGA, it is used for ...
1
vote
0answers
46 views

When do we actually need bank interleaving?

Since common DRAM chips support burst transfer and hardware page size (row size) in a bank is quite large, we can amortize the charging & activating time over bytes in a long burst transfer. I ...
0
votes
2answers
782 views

GPU vs CPU on chip memory

There has been a fairly wide ranging discussion as to why it is difficult to combine memory / CPU logic on the same die (yield issue compounding, different processes, different clock-frequency, ...
1
vote
1answer
3k views

What is the difference between BRAM and distributed RAM [closed]

I am doing a project on BRAM implementation. What is the difference between Block RAM and Distributed RAM on FPGA in terms of implementation, area, speed etc? Which is better?
0
votes
1answer
69 views

How to find a design house with dynamic memory device support? [closed]

I am looking for a design house with dynamic memory device support. Design houses, I found on the web, support only analog, mixed-signal, high-voltage designs and so. I found no design house with ...
1
vote
1answer
112 views

DRAM memory organisation

I've been trying to understand the working of DRAM chips but apparently in a lot of confusion. Suppose there are 8 banks in a single chip on a module. Is it only one bit that comes out of a single ...
7
votes
1answer
500 views

What determines the ground state of a computers dram?

I have read a paper about the cold-boot attack led by J. Alex Halderman. Full pdf: https://jhalderm.com/pub/papers/coldboot-sec08.pdf The paper shows the decay of a data in memory without power. They ...
0
votes
1answer
506 views

FPGA - What is the maximum allowed DRAM capacity on an XUPV5-LX110T Development Board?

I have purchased an XUPV5LX110T FPGA Development board and am unclear as to the size of the DRAM that can be upgraded. Currently I have a SODIMM 256MB that I am looking to increase for the ...
1
vote
1answer
462 views

Number of bits Per Column in DRAM

In DDR3, DDR4 DRAM ,I don't get the point that each column gives more than one bits?? Column decoder is also a mux which selects one of the bits in row buffer, and DRAM array is a crossed structure ...
9
votes
1answer
1k views

How is a DRAM volatile with capacitors?

There are a few things I understand: DRAM stores each bit of data to a tiny capacitor with some potential difference. Unless the capacitor is connected to low voltage end, the potential difference ...
9
votes
3answers
1k views

How can I implement a very simple asynchronous DRAM controller?

I'd like to know how to build a bare bones asynchronous DRAM controller. I have some 30-pin 1MB SIMM 70ns DRAM (1Mx9 with parity) modules that I'd like to use in a homebrew retro computer project. ...
0
votes
3answers
681 views

Structure of Larger Memory Modules by using different Size Blocks

I want to design a memory module that includes 2 types of memory cells. I know how to design the memory by using 1 type of memory cells like shown in the picture. But how about designing a memory ...
1
vote
2answers
579 views

CAS Latency and static RAM (SRAM)

Every time I read something about RAS e CAS there are mentions to the "DRAM" word. The only difference that comes in mind is the presence of a latch/counter and registers in case of the DRAM. However ...
-2
votes
2answers
1k views

Using a single transistor & capacitor (DRAM) vs a flip-flop(SRAM) to store a single bit of data

I'm a beginner trying to understand the working of SRAM and DRAM. According to sources, DRAMs use a single transistor along with a capacitor(1T1C) to store a single bit, where the capacitor holds ...
0
votes
0answers
161 views

Calculate DRAM latency

I am trying to make some performance on a memory centric network which has one cpu and multiple memory cubes.(HMC) I want to calculate the intra HMC latency which means the latency between sending a ...
0
votes
3answers
2k views

How many capacitors in single RAM?

Just a simple question, In https://en.wikipedia.org/wiki/Random-access_memory says that each bit of data in RAM/DRAM stored in a single pair of transistor and capacitor in memory cell. So let's ...
0
votes
1answer
60 views

DRAM3 memory fetch time

I am trying to understand how much time required in fpga time slots to fetch 128 bite value from DRAM3. I have a fpga board with 100 Mhz chip that talks with DRAM3 1600 Mhz. Thanks
2
votes
1answer
924 views

SRAM vs SDRAM as display buffer

I'm in a bit of a dilemma and I'm wondering if anybody here can help me. For a display application in need to use a framebuffer which is at least 2Mbytes.This framebuffer is used to drive a 800x480 ...
1
vote
2answers
189 views

What limits the lower bound of DRAM CAS latency

When a dram module receives a read/write command (while a row is active) it needs to: decode the command along with bank and column. multiplex the bank and send command along. (when reading) move ...
2
votes
1answer
116 views

Is the footprint or ball/land pattern for DDR1/2/3/4 IC's a standard?

I have looked across a few DDR3 IC's from different companies and different densities with the same data bus width, and they all seem to have the same packages (dimensions, ball pitch, etc) including ...
1
vote
1answer
176 views

Why is the WL charged at Vccp for DRAM cell?

Qouting from Dynamic random-access memory - Wikipedia Reading or writing a logic one requires the wordline is driven to a voltage greater than the sum of VCC and the access transistor's threshold ...
0
votes
1answer
609 views

How to estimate the peak current of DDR3L DRAM and design a power supply

I am designing a board which will have 5x DRAM DDR3L Micron MT41K512M8DA-107XIT:P (\$V_{DDQ}=1.35V\$). The question is, how to estimate the peak current consumption of the DRAM and then design a power ...
4
votes
2answers
4k views

Why does a DRAM cell necessarily contain a capacitor?

From some other dynamic logic structures I know that the parasitic capacitances at the nodes(gate to drain/source, drain/source to bulk capacitors) can be used to keep charge on them. Why is there an ...