Questions tagged [dram]
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Latch-based sense amplifier design using CADENCE Virtuoso 65 nm technology
I am trying to design a latch-based sense amplifier to sense about 55mV voltage difference using 65nm technolgy, it takes differential input, and should get from it differential output too where it ...
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1answer
39 views
Where the appropriate word size is selected for the operand?
This question is about a 32 bit Intel Chip using x86 assembly. My question specifically is what happens when you do the mov reg, mem instruction where the memory operand is a word (16 bits) from DRAM. ...
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1answer
31 views
RAM Row and Column Decoders
I keep seeing similar diagrams of RAM like this abstract picture of a simplified RAM Layout. So I just arbitrarily selected this picture but my question is about this layout in general. My ...
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77 views
What is the maximum voltage the capacitor can be charged in this circuit?
This is a single transistor DRAM circuit. We drive the WL and BL voltage to 5 volts. What is the maximum voltage the capacitor Cs can be charged? Is the dependency of Vth on source voltage important ...
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2answers
71 views
What design differences make ram faster than ssd for read/write [closed]
I understand that RAM is connected directly to the CPU via a high bandwidth bus, and SSD is a peripheral, but my assumption is that there are also electrical design differences (e.g. memory cell ...
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how to know how many Transistors are needed for column demultiplexing in different memory type arrays?
How many transistors are needed (if any) for the column demultiplexing in the following types of memory:
NOR ROM Mask Programable (row x column = 2000 x 256 )
Dual Ported SRAM Reg File (1 read, 1 ...
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1answer
78 views
DRAM in a FPGA - Image Sensor design
I am designing the simplest form of a camera: an FPGA that interfaces an image sensor and sends the acquired data to the host device via USB 3.0. There is no processing on the FPGA, it is used for ...
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32 views
When do we actually need bank interleaving?
Since common DRAM chips support burst transfer and hardware page size (row size) in a bank is quite large, we can amortize the charging & activating time over bytes in a long burst transfer.
I ...
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2answers
225 views
GPU vs CPU on chip memory
There has been a fairly wide ranging discussion as to why it is difficult to combine memory / CPU logic on the same die (yield issue compounding, different processes, different clock-frequency, ...
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1answer
661 views
What is the difference between BRAM and distributed RAM [closed]
I am doing a project on BRAM implementation. What is the difference between Block RAM and Distributed RAM on FPGA in terms of implementation, area, speed etc? Which is better?
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40 views
DRAM write operation
In a typical read operation from a dram chip, all the banks are equipped with sense amplifiers which select one bit from each bank using column multiplexer. But how does write operation takes place? ...
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1answer
66 views
How to find a design house with dynamic memory device support? [closed]
I am looking for a design house with dynamic memory device support. Design houses, I found on the web, support only analog, mixed-signal, high-voltage designs and so. I found no design house with ...
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1answer
62 views
DRAM memory organisation
I've been trying to understand the working of DRAM chips but apparently in a lot of confusion.
Suppose there are 8 banks in a single chip on a module. Is it only one bit that comes out of a single ...
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1answer
485 views
What determines the ground state of a computers dram?
I have read a paper about the cold-boot attack led by J. Alex Halderman.
Full pdf: https://jhalderm.com/pub/papers/coldboot-sec08.pdf
The paper shows the decay of a data in memory without power. They ...
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1answer
497 views
FPGA - What is the maximum allowed DRAM capacity on an XUPV5-LX110T Development Board?
I have purchased an XUPV5LX110T FPGA Development board and am unclear as to the size of the DRAM that can be upgraded.
Currently I have a SODIMM 256MB that I am looking to increase for the ...
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1answer
204 views
Number of bits Per Column in DRAM
In DDR3, DDR4 DRAM ,I don't get the point that each column gives more than one bits?? Column decoder is also a mux which selects one of the bits in row buffer, and DRAM array is a crossed structure ...
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1answer
1k views
How is a DRAM volatile with capacitors?
There are a few things I understand:
DRAM stores each bit of data to a tiny capacitor with some potential difference.
Unless the capacitor is connected to low voltage end, the potential difference ...
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3answers
480 views
How can I implement a very simple asynchronous DRAM controller?
I'd like to know how to build a bare bones asynchronous DRAM controller.
I have some 30-pin 1MB SIMM 70ns DRAM (1Mx9 with parity) modules that I'd like to use in a homebrew retro computer project. ...
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3answers
247 views
Structure of Larger Memory Modules by using different Size Blocks
I want to design a memory module that includes 2 types of memory cells. I know how to design the memory by using 1 type of memory cells like shown in the picture.
But how about designing a memory ...
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0answers
78 views
In a DRAM 1T1C cell, what are the typical values observed for caps?
So, I want to simulate a 1T1C DRAM cell. I have come across a wide variety of numbers for the storage cell capacitance in literature, ranging from as low as 13.8fF to as high as 150ff. but I haven't ...
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2answers
367 views
CAS Latency and static RAM (SRAM)
Every time I read something about RAS e CAS there are mentions to the "DRAM" word.
The only difference that comes in mind is the presence of a latch/counter and registers in case of the DRAM. However ...
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2answers
583 views
Using a single transistor & capacitor (DRAM) vs a flip-flop(SRAM) to store a single bit of data
I'm a beginner trying to understand the working of SRAM and DRAM.
According to sources, DRAMs use a single transistor along with a capacitor(1T1C) to store a single bit, where the capacitor holds ...
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0answers
71 views
Calculate DRAM latency
I am trying to make some performance on a memory centric network which has one cpu and multiple memory cubes.(HMC)
I want to calculate the intra HMC latency which means the latency between sending a ...
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3answers
1k views
How many capacitors in single RAM?
Just a simple question,
In https://en.wikipedia.org/wiki/Random-access_memory says that each bit of data in RAM/DRAM stored in a single pair of transistor and capacitor in memory cell.
So let's ...
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1answer
50 views
DRAM3 memory fetch time
I am trying to understand how much time required in fpga time slots to fetch 128 bite value from DRAM3. I have a fpga board with 100 Mhz chip that talks with DRAM3 1600 Mhz. Thanks
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1answer
564 views
SRAM vs SDRAM as display buffer
I'm in a bit of a dilemma and I'm wondering if anybody here can help me.
For a display application in need to use a framebuffer which is at least 2Mbytes.This framebuffer is used to drive a 800x480 ...
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2answers
156 views
What limits the lower bound of DRAM CAS latency
When a dram module receives a read/write command (while a row is active) it needs to:
decode the command along with bank and column.
multiplex the bank and send command along.
(when reading) move ...
2
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1answer
98 views
Is the footprint or ball/land pattern for DDR1/2/3/4 IC's a standard?
I have looked across a few DDR3 IC's from different companies and different densities with the same data bus width, and they all seem to have the same packages (dimensions, ball pitch, etc) including ...
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1answer
103 views
Why is the WL charged at Vccp for DRAM cell?
Qouting from Dynamic random-access memory - Wikipedia
Reading or writing a logic one requires the wordline is driven to a voltage greater than the sum of VCC and the access transistor's threshold ...
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1answer
313 views
How to estimate the peak current of DDR3L DRAM and design a power supply
I am designing a board which will have 5x DRAM DDR3L Micron MT41K512M8DA-107XIT:P (\$V_{DDQ}=1.35V\$). The question is, how to estimate the peak current consumption of the DRAM and then design a power ...
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2answers
2k views
Why does a DRAM cell necessarily contain a capacitor?
From some other dynamic logic structures I know that the parasitic capacitances at the nodes(gate to drain/source, drain/source to bulk capacitors) can be used to keep charge on them. Why is there an ...
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2answers
80 views
Is a PIC32 suitable for accessing SIMM-modules?
I have loads of SIMM-modules laying around and I have no clue whether they work or not, so I got the idea of tailoring some electronics to test them out. The easiest way would be to find some old 386-...
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1answer
68 views
Cost of expandable memory [closed]
Given two computers:
Has X gigabytes of RAM, that's the amount it ships with and that's all it will ever have, it can be designed around that number in whatever way is most efficient, solder chips ...
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1answer
113 views
Which fab for DRAM device? (ASIC design at Europractice)
I would like to ask for advice.
Europractice supports many fabs and technologies for custom asic design (fab list). Lib support list of those technologies are public (for example UMC 130 nm LL). I ...
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1answer
69 views
Electrical principle of row hammer glitch
There is a fairly new and exploitable bug happening in some DDR3 DRAMs called the "row hammer" in which it's possible to bit flip memory cells. I understand how the exploit works, but not the ...
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1answer
212 views
How many bits are addressed through one CAS command in DRAM?
From what I understand one column and row pairing corresponds to 64 bits from the DRAM chip, but this makes me think that one would then incur the CAS Latency (~18 clock cycles in DDR4) for EVERY ...
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0answers
202 views
How can I use an ARM chip to read & write 4164 DRAM?
I have an idea I'd like to pursue and partly because of their speed and partly because I'd like to begin ARM development I think a Cortex based board might be a good fit. I'm quite a proficient ...
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2answers
740 views
Rams and DQ lines
I'm studying DRams and SRams at university and on the slides the lines where a data is read or written is called DQ. But whats does it means? Maybe D is for Data, ...
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3answers
3k views
How DRAM refresh cycles work?
Nano capacitors in RAM act as leak bucket and continuously lose charge. For this RAM has to be refreshed periodically in order to charge those nano-capacitors again. "During the refresh cycles memory ...
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4answers
7k views
What is the need for precharging in SRAM/ DRAM memory cell?
Why is precharging so necessary while preforming read operation on SRAM/ DRAM cells?
For example in the SRAM 6T cell shown below,
Reading 0 requires bit line to discharge to 0;
Reading 1 requires ...
2
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1answer
105 views
Is the bulk output deliberately used in DRAM cells?
Regarding the structure of a DRAM cell with a MOSFET and a capacity, why does activating the word-line make the transistor connect through?
As I learnt, the MOSFET becomes conducting if UGS >> ...
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2answers
1k views
What is the precise use of a memory controller and RAM latency?
I'm learning about synchronous DRAM and it often mentioned a memory controller. What exactly is the point of this? Couldn't the cpu just take the job of requesting and receiving data with its own ...
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0answers
152 views
GDDR Power Calculation
I'm wondering if there is any publicly available documents or research papers that cover GDDR power estimation?
Micron provides very nice documentation and calculators for DDR up to DDR4, however I ...
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1answer
378 views
Why do DRAMs retain their state better when they are cold (when powered off)?
I'm sorry if this is off-topic. It may be better suited for a computer hardware forum, but I couldn't find anything appropriate.
I've been reading about the cold boot method, which can be used in ...
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1answer
81 views
Is memory bandwidth advertised for DRAM (like 12800 MB/s for PC-12800) ever achievable?
Memory bandwidth for DRAM like DDR3-1600 / PC-12800 is a function (product) of memory frequency (1600 MHz) and memory bus characteristics (width and number of channels). But memory also has timings (...
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1answer
166 views
DRAM timing with row and column decoders
Consider a 64Kx1 DRAM memory which means the number of rows is 256 and the number of columns is 256. In other words, two 8x256 decoders are needed for selecting the right row and column.
Since, each ...
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1answer
2k views
Modern replacements for old DRAM memory chips
I have an old video card for a computer from the 1980s era, but unfortunately the memory chips on it have gone bad. As it's quite a rare device today, I would like to repair it.
Unfortunately I can'...
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1answer
2k views
Can this SDRAM be used with STM32F7?
I have STM32F7 (which has a Flexible Memory Controller capable of interfacing SDRAMs) and I want someone to check if it is able to interface this SDRAM - IS42S32800D (http://www.farnell.com/datasheets/...
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0answers
495 views
SPICE model for DRAM transistor
My research group wants to investigate how powder delivery network (PDN) noise (such as ground bounce) can affect the retention time of DRAM cells. The idea is that the power noise increases the ...
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2answers
242 views
Size of DRAM logic designs
I am a beginner with FPGAs and EE in general, so please bear with me!
It is my understanding that many modern FPGAs are SRAM-based, and for good reason: SRAM can handle higher clock speeds and has ...
