Newest 'dram' Questions

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HyperRAM Linear Burst size throughput

Turned out to be a lengthy question, please feel free to skip and go directly to the questions Intro I am considering utilizing a HyperRAM in the next design, and studying the datasheet has lead me to ...

memory dram

asked Apr 16 at 2:01

Mr.Y

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How does radiation produce transient bit errors in DRAM?

Ionizing radiation can produce transient bit errors in volatile RAM. What is the exact mechanism by which this occurs? E.g., is there a threshold energy level for a single photon or neutron to ...

ram dram bit-error

asked Mar 24 at 17:58

feetwet

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vote

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DDRx JEDEC Standard: Retention Time

Different scientific publications [1,2] mention that DDRx memory has a (data) retention time of 64 ms while on average each cell is refreshed every 7.8 us (tREFI). I want to know where this ...

sdram dram ddr4

asked Feb 9 at 16:04

Patrick

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DRAM cells capacitor operation

I have a question about reading and writing operations. Say if i wanted to read or write the column WL0, i would enable the WL0 lines. For either a read of a write i would drive the bit lines to ...

memory dram

asked Dec 16 '20 at 21:50

Tech Visionary

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DRAM, multi-channel, memory access

I'm looking for a way, under any configuration/OS(windows or linux)/programming language you suggest to simultaneously access memory addresses, that are under different channels, meaning the access ...

memory ram dram

asked Dec 16 '20 at 6:54

Aviel Fedida

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2answers

91 views

Why are DRAM cells laid out in a square with regards to demux size?

I'm reading the chapter about DRAM access (2.1.3) of the paper "What Every Programmer Should Know About Memory - Ulrich Drepper" and there's a certain snippet that I just can't make sense of....

memory dram

asked Nov 21 '20 at 13:01

AMVaddictionist

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votes

1answer

219 views

Why are SDRAM CAS latencies so high?

I don't understand why the CAS latency of modern DDR4 memory is so high. I have no trouble understanding why the RAS latency is as high as it is -- given the small amount of charge stored in each ...

timing dram

asked Nov 8 '20 at 15:28

Dolda2000

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votes

1answer

75 views

SDR over DDR memory in FPGA based design

I am designing a new project which demands the usage of DRAM. I have never interfaced with one before, so my knowledge is rather limited. By analyzing the requirements, it would be sufficient to go ...

fpga dram

asked Oct 19 '20 at 20:17

Mr.Y

756 bronze badges

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2answers

131 views

How is 1 bit transfered from RAM to a 1 bit register?

I've been reading on computer RAM and CPUs. I came to the conclusion that most RAM today use arrays of DRAM while CPU registers and caches use SRAM. 1 bit DRAM is a circuit with one capacitor and 1 ...

transistors memory ram dram

asked Oct 8 '20 at 19:44

user123

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DRAM Rank-Level Allocations

I want to do allocations on a specific DRAM rank. The smallest allocation unit in an OS such as Linux is at the page size ...

memory computer-architecture dram physical-design

asked Sep 2 '20 at 11:52

TheAhmad

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Termination Requirements for DRAM

I am curious about how to wire DRAM to an SoC. What is required for optimal usage other than the net itself? I have seen conflicting information on if you should or should not use a termination ...

memory dram

asked Aug 18 '20 at 16:39

solarmainframe

687 bronze badges

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votes

1answer

131 views

Can i make dram using bjt transistors? [closed]

Is it possible to make dram using bjt's or is it only possible with mosfet's? If not why not? Is there an advantage in using mosfets instead of something like a bjt ?

bjt dram

asked Aug 10 '20 at 15:39

greatisgreat

213 bronze badges

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vote

3answers

114 views

DDR: Is the real maximum speed half of what is advertised in datasheets?

Let's take a single 8-bit 200MHz DDR chip. All datasheets state that bandwidth is "up to" 400MB/s. Because it's dual, data is read/written on both edges so yes, theoretical, it's 400MB/s. ...

sdram ddr dram

asked Aug 4 '20 at 6:26

gregoiregentil

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41 views

ddr: Is there any significant delta between the different strobes?

In a DDR memory, during a read, output data from the DDR is aligned on the strobe. There is one strobe per 8-bit: UDQS/LDQS for a 16-bit-wide DDR DQS[0-3] for a 32-bit-wide DDR Is there any ...

sdram ddr dram

asked Jul 25 '20 at 8:33

gregoiregentil

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151 views

No terminations on point to point DDR3?

Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ...

termination ddr dram ddr3

asked Jul 13 '20 at 19:39

pcbguy

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DRAM Self-Refresh not the Lowest Power Mode

I have a DDR3L Samsung DRAM on my Laptop. Based on page 23 of its datasheet, IDD6 or the ...

power current-measurement computer-architecture dram ddr3

asked Jul 5 '20 at 14:25

TheAhmad

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58 views

DDR3 AC characteristics

What is the meaning behind different AC input levels such as AC120, AC135, AC175 etc? I understand that AC_X means the level is Vref + X mV. And I also understand that the setup time is defined with ...

ddr dram ddr3

asked Jun 30 '20 at 19:15

pcbguy

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61 views

Is an even number of DRAM chips required?

I want to design a microprocessor based board (NXP imx 8m). All the boards I've seen so far have an even number of DRAM chips. If I want 4GB of RAM, do I have to use two 2GB DRAM chips or can I use ...

memory microprocessor nxp dram

asked Jun 5 '20 at 20:10

kadhem Alabdulmuhsin

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2answers

161 views

Can you get “raw” TFT display panels where you drive the gate and drain lines directly?

I am learning about different display types and how I might interface them with raw electronic components, e.g., TTL chips, op amps, function generators for scan line sawtooth, etc. CRT raster is ...

lcd display fet tft dram

asked May 9 '20 at 21:23

Gunther Schadow

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Is DRAM burst mode compatible with bank interleaving?

I am trying to understand how DRAM burst mode is compatible with bank interleaving. Once a row within a DRAM memory array has been activated, sensed and buffered, according to the strobed row address,...

dram

asked May 2 '20 at 12:06

Drummy

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54 views

EEPROM converted to DRAM?

Can we use a EEPROM cell for DRAM ? simulate this circuit – Schematic created using CircuitLab This is an EEPROM cell. Can we use multiple cells of this type to create a DRAM?

memory eeprom dram

asked Apr 5 '20 at 19:22

Jelly Strawberry

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110 views

How to design 1T-1C DRAM circuit in spice design tools, such as LTSPICE?

I have been trying to design a DRAM cell using the LTSPICE MODEL tool. The DRAM that I want to design is of 2nd GENERATION, i.e, 1t-1c dram cell. But whenever I design digit line it states the line is ...

ltspice vlsi sram non-volatile-memory dram

asked Apr 4 '20 at 14:28

Prasanna Shanbhogue

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1answer

377 views

Why cant clock be directly used instead of DQS in DDR during read and write

I have been reading about DDR lately and I am not able to understand the exact use of the DQS signal. The timing diagrams show dqs in phase with clock so why cant the clock only be used for the write ...

memory ram ddr dram

asked Mar 6 '20 at 6:17

Yohan0022

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70 views

open source SATA to DDR2 SDRAM adater

I want to learn how computer memory sticks can be used as secondary storage using some intermediate FPGA for data processing. Actually I want to design a PCB myself. I'm good with PCB designing but I ...

pcb fpga sdram dram sata

asked Feb 18 '20 at 8:45

Zeeshan Dhillon

337 bronze badges

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vote

2answers

137 views

How to reset flip flop in ATF16V8?

I'm designing a Z80 microcomputer with dynamic memory (DRAM), and I want to control the memory with 3 chips; an ATF16V8 Generic-Array Logic, and 2 74LS157 quad 2:1 multiplexers. The logic diagram of ...

dram z80

asked Feb 9 '20 at 0:21

Wesley Mays

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1answer

197 views

Why do we need interleaved memory?

I am trying to understand the DRAM working paradigm. I just read this article about interleaved memory. It says: Interleaved memory results in contiguous reads (which are common both in ...

memory ram dram

asked Jan 22 '20 at 6:09

smwikipedia

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217 views

The detailed working steps of the DRAM 3T1C cell?

This question is related to this one. But the focus is a little different so I put it here. I tried to understand the detailed working steps of below circuit. It is an old 3T1C DRAM cell circuit. ...

transistors mosfet dram

asked Jan 21 '20 at 7:31

smwikipedia

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2answers

165 views

Why is reading the 3T1C DRAM cell not destructive?

Could anyone help explain how the above 3T1C DRAM cell works? T means transistor and C means capacitor. Why is reading it not destructive?

transistors dram

asked Jan 20 '20 at 14:28

smwikipedia

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146 views

DDR4 board bringup issue

I am struggling with a DDR4 related board bringup issue. Can anyone out there recognise what the problem is by studying the attached memory dumps? The memory dump is from Preboot loader PB31 area of ...

ddr ddr3 dram

asked Jan 11 '20 at 10:54

Rolf Peder Klemetsen

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Can I use IS42SM16160K DRAM instead of IS42S16400 DRAM?

I have designed a custom board based on the STM32F4 controller and IS42S16400 DRAM. For some reason, I want to use IS42SM16160K mobile DRAM instead. Should there be a change in programming and ...

dram

asked Nov 3 '19 at 7:39

MS GH

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1answer

88 views

DRAM late and early read and write

For read operation in DRAM, perform early read mean OE low before CAS is low so doesn't this mean that you just read in junk data ? For write operation, i don't think there any problem with early ...

memory dram

asked Oct 30 '19 at 22:15

Carlos Frank

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DRAM Memory Lines

I have been trying to understand DDR and DRAM memories and stumbled upon this video In this video, from 20:00 to 23:00 he tells that the 8kb row buffer lines, actually come out as 64b and this 64b ...

memory ddr dram

asked Oct 23 '19 at 18:16

Newbie

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What is the difference between DRAM channel and DRAM Rank?

Can someone explain me the terms : DRAM Rank and a DRAM Channel is simple terms. I went through this PDF and I was not able to understand the DRAM Organisation/architecture on page 3 and page 11. Can ...

ddr dram

asked Aug 26 '19 at 14:17

Newbie

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Running code from different storage

So i know this question is being asked almost everyday on thousands of forums, but i am still going to ask that same question but with a different intent. Question #1: As an example lets use linux ...

arduino ram sram dram cortex

asked May 29 '19 at 14:25

Anton Stafeyev

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LPDDR4 pre-fetch

In the JEDEC LPDDR4 spec it is mentioned that LPDDR4 DRAM can support burst length 32(BL32) and also the LPDDR4 DRAM architecture is 16n prefetch. I want to know how burst length 32 be possible with ...

dram

asked Apr 22 '19 at 12:50

venkatesh

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1answer

170 views

Latch-based sense amplifier design using CADENCE Virtuoso 65 nm technology

I am trying to design a latch-based sense amplifier to sense about 55mV voltage difference using 65nm technolgy, it takes differential input, and should get from it differential output too where it ...

amplifier latch cadence dram

asked Feb 27 '19 at 15:36

Passant M.Ali

112 bronze badges

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1answer

46 views

Where the appropriate word size is selected for the operand?

This question is about a 32 bit Intel Chip using x86 assembly. My question specifically is what happens when you do the mov reg, mem instruction where the memory operand is a word (16 bits) from DRAM. ...

register intel dram x86

asked Feb 24 '19 at 1:42

Jaull

253 bronze badges

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votes

1answer

2k views

RAM Row and Column Decoders

I keep seeing similar diagrams of RAM like this abstract picture of a simplified RAM Layout. So I just arbitrarily selected this picture but my question is about this layout in general. My ...

ram sram dram

asked Feb 21 '19 at 20:42

Jaull

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2answers

271 views

What design differences make ram faster than ssd for read/write [closed]

I understand that RAM is connected directly to the CPU via a high bandwidth bus, and SSD is a peripheral, but my assumption is that there are also electrical design differences (e.g. memory cell ...

memory ram dram ssd

asked Dec 19 '18 at 16:35

JBaczuk

1197 bronze badges

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DRAM in a FPGA - Image Sensor design

I am designing the simplest form of a camera: an FPGA that interfaces an image sensor and sends the acquired data to the host device via USB 3.0. There is no processing on the FPGA, it is used for ...

fpga sdram image-sensor dram

asked Oct 19 '18 at 14:28

Manos

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When do we actually need bank interleaving?

Since common DRAM chips support burst transfer and hardware page size (row size) in a bank is quite large, we can amortize the charging & activating time over bytes in a long burst transfer. I ...

sdram dram

asked Oct 11 '18 at 7:41

SaltedFishLZ

112 bronze badges

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2answers

1k views

GPU vs CPU on chip memory

There has been a fairly wide ranging discussion as to why it is difficult to combine memory / CPU logic on the same die (yield issue compounding, different processes, different clock-frequency, ...

cpu sram dram gpu

asked Aug 20 '18 at 19:13

Daniel P

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1answer

5k views

What is the difference between BRAM and distributed RAM [closed]

I am doing a project on BRAM implementation. What is the difference between Block RAM and Distributed RAM on FPGA in terms of implementation, area, speed etc? Which is better?

fpga ram dram bram

asked Jul 2 '18 at 9:54

Student

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1answer

71 views

How to find a design house with dynamic memory device support? [closed]

I am looking for a design house with dynamic memory device support. Design houses, I found on the web, support only analog, mixed-signal, high-voltage designs and so. I found no design house with ...

asic sdram dram

asked Jun 11 '18 at 22:26

cocox

356 bronze badges

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208 views

DRAM memory organisation

I've been trying to understand the working of DRAM chips but apparently in a lot of confusion. Suppose there are 8 banks in a single chip on a module. Is it only one bit that comes out of a single ...

memory sdram ddr dram

asked Jun 10 '18 at 19:13

Rajat

211 bronze badge

8

votes

1answer

511 views

What determines the ground state of a computers dram?

I have read a paper about the cold-boot attack led by J. Alex Halderman. Full pdf: https://jhalderm.com/pub/papers/coldboot-sec08.pdf The paper shows the decay of a data in memory without power. They ...

memory dram

asked Jun 3 '18 at 18:41

dead_values

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515 views

FPGA - What is the maximum allowed DRAM capacity on an XUPV5-LX110T Development Board?

I have purchased an XUPV5LX110T FPGA Development board and am unclear as to the size of the DRAM that can be upgraded. Currently I have a SODIMM 256MB that I am looking to increase for the ...

fpga xilinx dram

asked May 30 '18 at 18:08

Vahe

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618 views

Number of bits Per Column in DRAM

In DDR3, DDR4 DRAM ,I don't get the point that each column gives more than one bits?? Column decoder is also a mux which selects one of the bits in row buffer, and DRAM array is a crossed structure ...

dram

asked May 24 '18 at 14:09

Mirza Qasim

112 bronze badges

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votes

1answer

1k views

How is a DRAM volatile with capacitors?

There are a few things I understand: DRAM stores each bit of data to a tiny capacitor with some potential difference. Unless the capacitor is connected to low voltage end, the potential difference ...

voltage capacitor memory non-volatile-memory dram

asked Mar 31 '18 at 10:13

GypsyCosmonaut

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3answers

2k views

How can I implement a very simple asynchronous DRAM controller?

I'd like to know how to build a bare bones asynchronous DRAM controller. I have some 30-pin 1MB SIMM 70ns DRAM (1Mx9 with parity) modules that I'd like to use in a homebrew retro computer project. ...

memory timing dram 7400

asked Feb 14 '18 at 22:53

Anthony

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