Questions tagged [drc]
Design Rule Check(s): a checking procedure that PCB CAD software does against a design rule file.
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Altium Designer 23 DRC Rule Creation: How do I set a special clearance rule for a TH Pad to SMD pad?
My issue: Because of wave and selective soldering techniques, I need an 8mm clearance for an SMD pad to a TH pad that is on the opposite side of a placed TH part.
Here is the scenario to better ...
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1
answer
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Ground Relief Gap Design Rule -- Altium
Does anyone know of a way to implement a design rule in altium to check for instances where signals cross over a via relief ground plane gap? Example shown below.
Thanks!
- 172
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2
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39
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Clearance error on pin header solder pads in Eagle
I am getting a clearance error on the Sullins connector PPTC191LFBN-RC. I got the EDA models from Octopart. On including this model in my design I am getting a solder pad clearance error on both the ...
2
votes
2
answers
132
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Kicad DRC Error "Footprint has no courtyard defined"
At the final stage of the PCB design, I performed an ERC check.
I got the message:
Footprint has no courtyard defined
@(156,718mm, 78,296mm): Footprint RV1 on Front
...
- 1,339
0
votes
1
answer
36
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DRC errors in Eagle design
I am a new Eagle user. While trying to create a simple adapter between two connectors, I receive many DRC errors (overlaps, clearance, dimensions. The libraries of the connectors were downloaded ...
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2
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219
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Altium wants to attach nets to NC pins of same IC
In Altium, it seems no connect (NC) pins in a given IC create a net that wants to connect them all together. I've been looking for some parameter we may have set when the part was created that ...
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1
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702
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Verilog in Vivado - DRC MDRV-1 Multiple Driver Nets Error
I am writing code that behaves as a rudimentary register file. I have created the register file as a module reg_file.v. The code instantiates a module, describing a register with loading capabilities, ...
1
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1
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69
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Manufacturing Design Rule Check in Altium
I have experience in schematic design but am new to PCB layer design. When I run a design rule check without Manufacturing and Testpoint rules, I get no rule warnings or violations. But when I include ...
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1
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Violations on USB connector in Altium
I am designing a PCB and in the design, I am using a USB micro-B connector. I have experience in designing schematics but have recently started designing PCB layouts. I got this component from the ...
- 153
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3
answers
744
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What are good values for standard design rules (like clearance, trace width, etc.) in PCB design?
I am working on a project for LED control with MCU and LED drivers. I have an input voltage of 24 V and a DCDC converter to 3.3 V for the MCU. Each LED controller will have an output current of 1 A.
I ...
- 153
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2
answers
787
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Altium Online DRC not working
I always route with Online DRC on so that I can realise when I've done a mistake, although this suddenly stopped working during my last PCB design and its been very frustrating to have to perform a ...
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3
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Altium designer PCB - Strange and confusing symbols everywhere (From DRC - Design Rule Checker)
I'm starting to learn Altium Designer, and I have this on my PCB screen:
I've tried several things, but nothing works. Here is the same image, I just moved the components away:
Can someone explain ...
- 63
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1
answer
196
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Run DRC within a given area only
Background
I often design PCBs by pre-placing certain hierarchical blocks first. I pre-place multiple ones of these then choose one of them and start wiring things up inside it, adding the necessary ...
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70
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Altium: Design rule to highlight a plane that is not assigned to a net
In Altium Designer 20.1.14.287 I tried to create a design rule that would highlight that a plane is not assigned to any net after running the DRC. But in the PCB Rules and Constraints Editor I only ...
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How can I find the errors on my layout?
I am losing my mind not being able to find the error on my layout. I feel like I am looking for a nail in the mud.
I am getting the DRC error
: MET1 pin outside met1
But I look and look and LOOK and ...
- 1,403
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1
answer
454
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What is this error on DRC Cadence layout
I'm doing the layout of an amplifier on Cadence. I've run the DRC error checker and I don't understand what message is this, can someone help me?
- 1,403
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How can I limit design rules check on some components and its connected tracks in Altium?
My design is using an isolator between low voltage and main supply.
I'm using a design rule to set clearance beetween planes and tracks with this kind of query:
...
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2
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0
answers
924
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Altium - Hole to hole clearance rule that only applies when nets are not the same
Our PCB manufacturer specifies that there should be a minimum clearance between holes of 0.5mm when nets are different.
I am getting a lot of errors when I have thermal pads with embedded vias closer ...
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2
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1
answer
1k
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How can I prevent the DRC in KiCAD from checking my silkscreen layers?
I am currently working on a PCB with a lot of components which are very close to one another. For this PCB I do not want to manufacture the silkscreen layers and I do not want the DRC to check for ...
- 211
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1
answer
315
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Altium: Component Clearance constraint won't go away after setting rule
I am using Altium 18. I ran a DRC check and got the following error:
This is saying i don't have clearance between J2 and MH2. This can be seen in the PCB:
However, i have set the following rule:
...
- 737
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1
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70
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Altium 21 - how to configure multiple layers in schematic
While setting up some rules for a netclass, I wanted to prevent routing on top and bottom copper while allowing it on Inner1 and Inner2.
However, the rule dialog only has two layers available: top and ...
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2
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1k
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KiCAD: "Footprint has no courtyard defined" using Arduino shield template
I made an Arduino shield with KiCAD.
When I finished the board in PCBnew, I ran a design rules check.
I got "Footprint has no courtyard defined" on all the mounting holes in the shield ...
- 1,339
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0
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131
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KiCAD 5 ‒ Is ist possible for a footprint to have multiple courtyards?
One of the components I am using is really a daughterboard that plugs into two rows of pin headers. Under the daughterboards, between the pin headers, there is space for a additional components. I ...
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2
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Do PCB routing vias require soldermask expansion?
Most recommendations I've come across regarding solder mask expansion state that it is required so that misalignment between the copper pad and the solder mask opening do not interfere with the solder ...
- 418
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3
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3k
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Altium Collision DRC error? Cant figure out why
i have finished my PCB design with Altium. I ran the DRC, to check if there are any errors. Strangely i got like hundreds of errors. First i couldn't find out why, but i managed to narrow it down to ...
- 328
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4
answers
625
views
Vias in a the layout of a CMOS Integrated Circuit
Is there a downside to using maximum possible VIAs (adhering to DRC rules) to connect two very long metals (ex. Power rails in Mx and Mx+1) running in parallel at block level? I know that multiple ...
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1
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166
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Altium 20 Deleting Rules
I have Altium 20.0.11.
My rules keep getting deleted when I update from the schematic.
Any rule I set in the PCB gets removed when I perform an update from the schematic.
This the only project I ...
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1
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604
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What factors do I need to consider when selecting an inductor to use in a circuit with the MT3608?
I am trying to use the MT3608 chip to boost the power output of a 3.7V lipo battery from 3.7V to 5V, which will ultimately power an ATMEGA32U4 chip. Below is a picture of my circuit where I have ...
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1k
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Altium rules help: keepout region around mounting point throws collision errors for the mounting point itself
I'm working on an Altium footprint for a plated mounting hole with embedded vias arranged around the hole. I have the copper the way I want, but Altium is now throwing DRC errors at me that I'd like ...
- 1,316
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578
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Eagle PCB- DRC Errors: Drill distance and size
I am new to Eagle, so please be polite if I am in the wrong area.
I added two mounting holes and had to move some components for clearance. I also extended the board size slightly to accommodate the ...
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1
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118
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EAGLE - StopMask DRC Error
I cant understand what this DRC error means.
Especially I do not understand this box. Does it mean that the Soldermask will cover part of the pad? How to correct it?
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3
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1k
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Altium - broken unconnected nets
I am having trouble figuring out what is wrong with these nets?
"Design -> Netlist -> Clear all nets" will delete only the functional ones and these unconnected ones remain.
Can anyone tell me what ...
- 3
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1
answer
207
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PCB design rule errors, but can't understand why
I am trying to create a PCB using NI Ultiboard. My circuit is a SECPIC DC-DC converter and controlling the L1 current. This is my circuit:
and I get this error:
...
- 21
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1
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341
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Altium - design rule check does not match with signal integrity for impedance
I have designed a 2-layer PCB with Altium Designer. I placed an impedance rule of 50 Ohm in trace width rule section. When I run the design rule check, there is no impedance error.
However, when I ...
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0
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567
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UnRouted Net Constraint in Altium after Via Stitching
I am just wrapping up my Design of one of my project in Altium 17. I was done with adding ...
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68
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Altium DRC to catch via on plane split
I had a recent design flagged from the PCB house because of a via that almost didn't connect to the power plane it should have, due to its placement on a split line (see below).
I want to add a ...
- 1,601
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votes
3
answers
817
views
Altium track width DRC error on corners
I just ran the DRC check in Altium for my PCB and I get errors on trace width for every trace segments on the board.
What is the reason for this ? It generated thousands of errors even tho all the ...
- 574
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2
answers
3k
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Altium doesn't show any violation
My Altium Designer does not show any violation, even if I place 2 components right above each other.
Im quite the beginner at PCB Design, but does someone know the answer to my problem?
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1
answer
521
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Altium Designer 17 DRC taking for ever
Intro: My Colleague and I have been using altium Designer for Sometime now . Currently AD 17.1.6 (build 538) . The PCB we draw are 3d 4 layer maximum . the only difference between us is that the ...
- 3,189
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0
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49
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Cadance Error, PCB desining
I am trying to design a simple PCB, using Cadance 17.02 , after importing schematic to PCB designer all footprint pin have DRC Error. the Error is :
"Thru pin to shape spacing" with both actual and ...
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1
vote
2
answers
169
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stop mask error remains after deleting offending text in eagle
I ran the DRC for dirty pcbs, and it's giving me these stop mask errors for values assigned.
In this particular example, It's D1 with a 4148 label. In the first image, you can see the 4148 value ...
- 523
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0
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2k
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what is parallel run length in DRC check
What exactly is parallel run length in DRC check. I understand that there should be a minimum spacing between two metals depeding upon their parallel run length.
In the above figure R1 is the ...
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2
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Room Definition error in Altium
I have placed my first BGA on a PCB. I have followed the instructions from this video:
How to fanout a BGA - Altium Designer 16.1 - Joao Beck
The overall footprint of the BGA is much larger than ...
- 671
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2
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387
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75 Ohm trace with error markers in Altium
I am designing an RF PCB in Altium and I have set rules for 75 ohm as well as 50 ohm impedance traces. The picture attached shows a particular 75 ohm traces with error markers. The trace width is as ...
0
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1
answer
1k
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How to disable/overwrite tStop overlap/conflicts detection in eagle's DRC?
please refer to the image below for the overall idea:
In eagle, there is a layer called "tStop" and with its counterpart for bottom layer being "bStop". As I manage to gather, it's some sort of mask ...
- 371
2
votes
2
answers
86
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Eagle insists on marking up spaces which are larger than the minimum specified in the DRC rule
This is what my clearance rule looks like:
My grid distance looks like this:
And the final result, after DRC, looks like this:
As you can see, although not by a very large margin, the distance is ...
- 371
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votes
1
answer
445
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Errors in EAGLE layout
I am designing a multi-layered layout in EAGLE for the first time. I have already moved all the parts inside the board area. And instead of starting to route I checked for errors. I got some 1500 ...
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1
vote
1
answer
212
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Clearance DRC capacitor
I'm getting a clearance error in Eagle, as I understanded, the error comes from the distance between two signals. As you can see in this image there is this pointy thing between pads. What is this ?
...
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2
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2k
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Altium: how to display all DRC errors?
I've routed my PCB but had to change the minimum keepout rules which means I'll now have a lot of DRC errors - most tracks are too closely placed together and that would violate the new keepout rule.
...
- 47
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votes
3
answers
5k
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How can I allow shorts between the same net in Altium?
I have some pads and tracks that are different primitives but are the same net in an Altium layout.
Altium keeps flagging these as ShortCircuit DRC violations, but they're the same net, so I don't ...
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