Questions tagged [drc]

Design Rule Check(s). Is a checkinng procedure that the PCB cad software does against a design rule file.

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Eagle insists on marking up spaces which are larger than the minimum specified in the DRC rule

This is what my clearance rule looks like: My grid distance looks like this: And the final result, after DRC, looks like this: As you can see, although not by a very large margin, the distance is ...
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Eagle keepout: ignore Restrict layer violations within a footprint

I am working on an Eagle PCB footprint for this TagConnect TC2030-IDC-NL connector. The footprint specifies a keepout restriction between the pads: However, when I implement this footprint in Eagle, ...
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KiCAD 5 ‒ Is ist possible for a footprint to have multiple courtyards?

One of the components I am using is really a daughterboard that plugs into two rows of pin headers. Under the daughterboards, between the pin headers, there is space for a additional components. I ...
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Analog CMOS IC layout: DRC, DFM, DFR

Regarding CMOS analog IC layout, what are differences between DRC, DFM and DFR? What I understood during research: DRC (Design Rule Check) - checks if a laid out block follows technology rules what ...
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Altium's 'Ignore pad to pad clearances within a footprint' inside CircuitMaker?

This is a related question to Autoroute or not? I have an option enabled in the Autorouter of CircuitMaker (Rip-up Violations After Routing), to prevent getting illegal routings. See below. As you ...
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Altium 20 Deleting Rules

I have Altium 20.0.11. My rules keep getting deleted when I update from the schematic. Any rule I set in the PCB gets removed when I perform an update from the schematic. This the only project I ...
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276 views

Altium rules help: keepout region around mounting point throws collision errors for the mounting point itself

I'm working on an Altium footprint for a plated mounting hole with embedded vias arranged around the hole. I have the copper the way I want, but Altium is now throwing DRC errors at me that I'd like ...
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UnRouted Net Constraint in Altium after Via Stitching

I am just wrapping up my Design of one of my project in Altium 17. I was done with adding ...
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Altium DRC to catch via on plane split

I had a recent design flagged from the PCB house because of a via that almost didn't connect to the power plane it should have, due to its placement on a split line (see below). I want to add a ...
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Cadance Error, PCB desining

I am trying to design a simple PCB, using Cadance 17.02 , after importing schematic to PCB designer all footprint pin have DRC Error. the Error is : "Thru pin to shape spacing" with both actual and ...
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what is parallel run length in DRC check

What exactly is parallel run length in DRC check. I understand that there should be a minimum spacing between two metals depeding upon their parallel run length. In the above figure R1 is the ...
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75 Ohm trace with error markers in Altium

I am designing an RF PCB in Altium and I have set rules for 75 ohm as well as 50 ohm impedance traces. The picture attached shows a particular 75 ohm traces with error markers. The trace width is as ...
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Errors in EAGLE layout

I am designing a multi-layered layout in EAGLE for the first time. I have already moved all the parts inside the board area. And instead of starting to route I checked for errors. I got some 1500 ...