Questions tagged [edge]
The edge tag has no usage guidance.
55 questions
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Struggling to understand how a JK flip flop can behave contrary to understanding
I have tried to understand how the JK flip flop in the image below (U3B) is behaving, and I am at a loss.
For context, I've included related parts of the circuit. However, to avoid muddling my issue, ...
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Troubleshooting a Positive Rising Edge Trigger Monostable Circuit with 555 IC
I've been working on designing a positive rising edge trigger monostable circuit using a 555 IC, aiming for a pulse duration of around 5 seconds. However, my simulation attempts have been unsuccessful ...
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Kicad 7 - Resize a board
I created a board in Kicad, but doing more work on it, I managed to shrink its size.
All this is unused space.
Is there a way to shrink the board. It is easy to move the edge cuts, but the unused ...
- 1,399
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SCLK : 50 [MHz] Rising Edge vs 25 [MHz] Dual Edge : Tradeoffs
TI manufacturers two near-identical drivers for matrixed LEDs, LP5890 and TLC6983. I was only able to determine the following ...
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SIMCOM SIM7000G power supply design testing LTspice
According to the datasheet SIM7000 _Hardware Design_V1.05 in section 3.1 Power Supply,
On VBAT pads, when module works on EDGE or GPRS mode, the ripple current is up to 2A typically. For steady ...
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Confusion about edge/level triggering interrupt
I have read this answer.
My understanding is, there are actually 2 lines logically:
clock/gating line
event/interrupt line
And the clock/gating line can make the circuit take event input at an ...
- 1,212
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How to check for immutability the simulated signal after edge coming in SystemVerilog?
Suppose that we have some module (which simulates FPGA external environment) with an input line (from a FPGA). When an edge (rising/falling) comes from this line the module must test that the logic ...
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Weird waveform of a digital latch
I am simulating on ADS.
As you can see, the V1 goes high at 9n sec.The clk has first rising edge at 10n sec.
Why does output V2 not go up at the 10n seconds? It goes up at 20n seconds at the second ...
user314455
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Not being able to detect falling clock edges on SPI
I am trying to establish an SPI Connection between a microcontroller (STM32 dev board, master) and a CPLD (slave). For a simple demo to test the connection, I was just trying to toggle the MISO pin ...
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The datasheet says that USB operates on 1.8v instead of 3.3v, do I need some sort of logic level shifter in my circuit?
I'm trying to design a breakout board and connect the Google coral chip to my Toradex Colibri imx6 SoC via usb. I'm assuming that the imx6 is using 3v3 logic because it doesn't indicate otherwise, and ...
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Is there a component that will provide an elevated SMD pad?
Is there a surface-mount component I can put on a pad, that simply has another pad on top that I can solder something on to?
Here is a side view showing pins above the pads that would need bent down ...
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825
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Minimizing signal delay when debouncing
I have a mechanical switch that I'd like to use as a signal source for a digital input of a microcontroller. The switch is normally closed, and I'd like to detect the switch being opened as quickly as ...
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Rising Edge vs Falling Edge D Flip-Flops
Is there any difference between a rising edge and a falling edge triggered D flip flop? For example, a falling edge flip flop will be faster or if there will be any change in result.
Is it correct for ...
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Why do some PCBs have exposed copper along the edge even when mounted in plastic enclosure? [closed]
I've already read about reasons for exposing copper at the perimeter of a PCB (i.e. Why do some PCBs have exposed plated perimeters?).
It seems that the main reason to completely expose the copper ...
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How to latch a signal rise and low on the next signal rise
My input signal is a pulsing 35Hz with a top at 5 volts. The pulses itself are short.
The first pulse (5v) should trigger a latch at 5v high. And the next pulse should reset the latch to low.
Added a ...
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Is there a component that will OR the last 1-2ms of its input?
I need a component/circuit which will output 1 if a 1 has been input at any time in the last 1-2ms.
I could make such a circuit out of several shift registers, an oscillator and several OR gates, or ...
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Confusion about when a JK flip flop is triggered
I started learning about latches and flip flops recently, and my understanding is that edge-triggered devices like flip flops ignore their inputs until the clock signal transitions from low to high or ...
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Is there an intuitive explanation of the classic edge-triggered flip flop circuit?
I figure there must be a way to understand it in terms of the three underlying latches somehow locking each other out, but I'm not getting it.
Is there a way to understand the edge-triggered flip ...
- 3,105
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592
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Rising edge detector negative pulse emitter - how to prevent firing at power up?
The point of this circuit is to allow rising edges to send a negative pulse to a 555 timer. C1's purpose is to allow rising edges to trigger a positive pulse which in turn connects output to ground.
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Turn a positive clock edge into a negative pulse to make a 74LS170/670 register file synchronous
This is a follow-up o Why did they make the 74x170 (670) register file asychronous, no CLK input?.
I want to use that "register file" for my project, but I need to make it behave properly as a ...
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I2C data sampling is done at clock edge or level
I am trying to understand I2C data bus from this document. It explains the START-SLAVEADRESS-R/W-ACK-DATA.. as the master-slave take turns to get hold of the shared bus for mutual communication.
One ...
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Why not nickel-plated edge connectors?
The tracks used as an edge connector are gold coated to improve contact with the female connector: bare Cu oxidizes, and also wears out if they are inserted and removed repeatedly. Au cannot be ...
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Low power dual edge detector using too much power
I am creating a hobby circuit which transfer signal to edge triggered pulses. I created circuit like this:
But I have issue with power consumption. XOR gate need power which take 8mA which is really ...
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Connector footprint JAMMA
JAMMA connectors are card edge slots that were common in arcade games before cheap SBCs. They are designed for fairly high current (5A) and are robust and cheap in a range of sizes from 8 to 72 pin.
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Comparison of 1G123 to 4538
I am designing the edge detection circuit with predefined output pulse duration. Pulse width will be 18.33 ms, supply power is 5V. Error tolerable is +-1 ms.
There're a number of designs already ...
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Deciding which assembly is more common positive edge detector
I know of two circuits which can act as edge detector:
A clock connected as a voltage source across a RC component where resistance is composed of a diode and a resistor and this in series with ...
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Delaying rising edge of input signal - 3.3v logic
I'm new here and I need help with my project. I working on my DIY home automation and I need to delay rising edge of the input signal. Trigger is faling edge. I need to delay it 100 - 500ms and I use ...
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How to make a positive pulse with a button?
I want to make a circuit that sends a positive pulse that gets high for a few nano seconds when I push the button and then goes to low. I want this to happen even if I hold the button down without ...
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How to generate a single pulse using RC circuit from a fixed DC supply without any controller, timer or delay IC?
I have a DC supply (5 V) to turn some circuit on and in that circuit there is a module which uses a specific mechanism (i.e. a 2 seconds width high pulse) to turn on (even if a supply is connected, ...
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Problem with signal edge in schematics containing high speed IC switch
I am trying to design the following schematics:
There are two kOhms resistance which are connected serially. One is load and another is device resistance. I need to apply the voltage in a the ...
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Trigger Edge Detection Voltage issues
I'm trying to get an ESP8266 to wake up via external trigger. The trigger in this case is a PIR, which sends a 2+ second high signal when motion is detected.
I'm using an edge detector to turn that ...
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Active high, rising edge circuits update state when, exactly?
I'm very new to electrical engineering. On a recent exam, we had a circuit with two JK flip-flops connected in series with one another. The circuit is beside the point, however.
Both flip-flops were ...
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How to implement a negative edge triggered D Flip Flop (Master Slave Configuration)?
Can you please post a picture of the implementation of such flip-flop at logic gate level? How can I easily change a positive edge triggered D Flip Flop to a negative edge? Also, how will the truth ...
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Synchronize random edge to clock edge
I have a steady clock signal and another signal with random binary pulses. Is there a simple circuit that can detect the rising edge of the random pulses and generate a pulse that is synchronized to ...
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Overshoot on MOSFET drain
What can i do to minimize overshoot and undershoot when MOSFET switches on and off? (waveform taken using short ground spring probe, PCB is 2-layer) The rise and fall times should be less than 150ns.
...
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555 positive and negative edge detector?
Is there a circuit using the 555 (without additional logic gates) that creates a positive pulse when it detects a rising or falling edge?
The goal is to have a circuit that detects when a signal goes ...
- 1,902
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Why does this Edge Trigger Work on input of 555 monostable config?
I recently wired up a 555 timer in a mono stable configuration and found that when the trigger was held low for longer than the configured output pulse width, the output would stay high. After ...
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Long lines: whether or not to treat PCB traces as RF lines
My setup: 53 x 28 mm PCB, uC will run somewhere between 1 MHz and 8MHz. Dual layer PCB design.
From the info I gathered on this site it seems there are two aspects to consider in deciding how to ...
- 1,061
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transistor negative edge-triggered detector
This is a circuit I whipped up for an attempt to make a negative-edge triggered detector with inverted output.
The logic needs to be the following:
If input is high, output is high.
If input goes ...
user116345
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turn level-based input to edge-triggered input [duplicate]
I'm trying to figure out with the most minimal part count how to convert an input of a digital IC to an edge-triggered input.
I am using the 82C55 IC and the input on it I want to make negative edge-...
user116345
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Falling and Rasing Edge Detector
I will use a motor adapter in my design.This motor adapter doesn't have a spice model. Therofore I will design inside structure of this adapter. In this motor adapter has a delay and xor gate part.I ...
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Edge-triggering on simple logic
I'm making a module where a microcontroller can control RAM with only 10 GPIO pins (8 is data D0 through D7 and 2 are control).
One thing I want to do is that the moment a control line is raised, I ...
user116345
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How to get rid of this reflection on falling edge of i2c SDA line?
This is the scopeshot of the falling edge:
How to get rid of the reflections on the falling edge of this SDA line?
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How to clean up ringing / noise on rising edge of CMOS output?
I am feeding an interrupt input with the output from a CMOS Schmitt inverter. The falling edge of the inverter is nice and clean, But the rising edge is really dirty, and can get downright ugly at ...
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Convert falling / rising edge to pulses with minimal components
I have a signal that changes from high state to low every few minutes, after changing state it will remain constant, all level changes are clean.
I'm looking for the smallest possible circuit that can ...
- 1,902
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Arduino code - Why do we need to read the rising edge?
I'm having a difficult time figuring out why we need to read the rising edge instead of using both edges.
We are doing a school lab using interrupts in Arduino code, and I understand that we need ...
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How to generate edge-triggered pulse
First, a bit of background: I am just a hobbyist with electronics and have very little formal education in the area. I understand most terminology, but generally require a schematic for me to be able ...
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Why is D flip-flop positive edge triggered instead of level triggered?
I'm trying to understand this D type positive edge flip-flop:
simulate this circuit – Schematic created using CircuitLab
I'm having problem understanding why it is positive edge triggered and ...
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681
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Reconize JK Flip-Flop operating edge: rising or falling?
This is a JK Flip-Flop image.
Using this image is there a way to know if the output changes on raising or falling clock? In other words, is input data
transferred to the outputs on the HIGH-to-LOW ...
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What is the purpose of the sharp edges (aka mouse bites, aka perforated breakaway tabs) on the PCB?
I have received an NVIDIA Jetson board this week and it has the following edges near the mount holes:
I did a quick search on the internet but was only able to find similar edges on the Raspberry Pi ...
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