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Process compatibility between a non-planar avalanche photodiode and planar CMOS at 0.130μm process technology node

I plan to integrate a non-planar P⁺⁺/i/P⁺/N⁺⁺ avalanche photodiode (APD) array with a peripheral control circuit (e.g., trans-impedance amplifier, analog-to-digital converter, and quenching circuit) ...
Amita Rawat's user avatar
4 votes
2 answers
801 views

Why are drain and source not actually perfectly symmetric?

In textbook treatments, one has that the source and drain of a MOSFET are completely symmetrical and therefore interchangeable -- the distinction is only made by which is at a higher voltage in the ...
EE18's user avatar
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1 vote
1 answer
190 views

On different well processes (fabrication process)

My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the nature of fabricating wells in the twin-well and triple-well processes. My question here is about how we can use so few ...
EE18's user avatar
  • 1,151
25 votes
4 answers
4k views

Why do fabs bother to print circuitry right up to the edges of a wafer when they know that the partial dies will be discarded later?

Around the edge of a wafer (see image below) you will observe that there are many partial dies. It seems wasteful to use the lithography machine to print these partial dies because they will be ...
phil1008's user avatar
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1 answer
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What does optimizing fabs "for throughput rather than latency" mean?

In the context of a whirlwind tour of the modern VLSI design, tapeout, and fabrication flow in their CMOS VLSI Design, Weste and Harris write the following: Multiple chips are manufactured ...
EE18's user avatar
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1 vote
2 answers
64 views

How does MOSIS let designers “share” a mask set?

In Weste and Harris's CMOS VLSI Design, they describe MOSIS as follows: The MOSIS service [Piña02] is a low-cost prototyping service that collects designs from academic, commercial, and government ...
EE18's user avatar
  • 1,151
2 votes
0 answers
65 views

How many LC oscillators can you easily fit on a single chip?

I recently read this interesting blog post about 'thermodynamic computing' that tickled my fancy. The TLDR version is that the authors designed and built a circuit that can perform matrix inversion ...
Martin C.'s user avatar
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1 answer
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Ribbon Cable Pin Assignment

Preface: I am complete novice at electronics and this is my first project. I am trying to connect two PCB together with a 10pin ribbon cable. The ribbon cables I made (and bought) are all showing ...
user3746283's user avatar
1 vote
1 answer
356 views

Why aren't inverters used in a half adder made of NOR gates?

That's schematic of half adder using only NOR gates. Why aren'y inverters used? In the picture, there are 2 NOR gates where the two inputs are same as A or B. Why don't we replace these with a NOT ...
Hottestbeef's user avatar
2 votes
1 answer
45 views

Suggested Configuration of Sputtering System?

hopefully this is in the right section, a lot of electrical engineers work in semiconductors. I have an old hummer II desktop sputter coater I am trying to make use of. The documentation of something ...
Matt's user avatar
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3 votes
3 answers
159 views

Understanding fabrication steps of creating TFT MOSFET from ZnO

A few days ago I found this paper about fabricating a thin film MOSFET using ZnO at low temperature. It seems promising to me (to do at home, some people actually made their own MOSFET at home but ...
raspiduino's user avatar
0 votes
2 answers
444 views

Does wire size matter? If so, how?

I took the transformer from a microwave to make a spot welder. I cut the secondary wire out. Now I'm supposed to wrap a wire around the iron base. Primary wire is much smaller gauge than the secondary,...
Daze Daemar's user avatar
1 vote
1 answer
141 views

We fabricate P-type and N-type Schottky diodes and a P-type Schottky diode; can a PN-junction diode and PNP BJT be formed?

A Schottky diode is a unipolar device. If a P-type Schottky diode is fabricated on an N-type Schottky diode, can we make a PN-junction diode and a PNP transistor?
Chandra Prakash's user avatar
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0 answers
230 views

What does "field" in field oxide mean?

This is an excerpt from Design of Analog CMOS Integrated Circuits by Behzad Razavi. What does "field" in field oxide mean here, electric field?
hana's user avatar
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2 votes
3 answers
2k views

Why is silicon used as PCBs?

I know why silicon is used for ICs and transistors in general due to its doping features. But I don't know why we use silicon as a PCBs, all we need is to isolate pins from each other in a PCB, right? ...
Mohamed Abduljawad's user avatar
0 votes
0 answers
57 views

How is a diode packaged

I need to know the process for packaging a diode such as inserting the die on the package or case, what is that process like.
Roberto Lemaitre 's user avatar
19 votes
4 answers
5k views

Would you approve use of these PCBs??? Delamination issue

Our vendor pulled some PCBA out of storage, been sitting for about a year. They found about 5% delaminated. They claim it was 'because of the storage duration', but I'm not buying that. I think ...
Kyle B's user avatar
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3 votes
2 answers
1k views

How are other chipmakers keeping up with TSMC if their processes are just the best?

In the news recently was Intel's stock falling 20% because its 7nm processes are being delayed by 6+ months. The argument seems to be that Intel is already behind (since they're using 10nm processes ...
Allure's user avatar
  • 163
1 vote
2 answers
448 views

Shared IC tape out

I have a IC design about 300*300 micrometers. Due to the high cost of IC tape out, is it possible to fabricate the IC jointly with other people? Does the company have such a service?
seyyedali hosseini's user avatar
0 votes
3 answers
199 views

PCB Layout of a circuit

So, I drew a two sided PCB of a circuit represented in the picture below. I used the program DipTrace to draw it. The first picture represents the top side. And the next one represents the bottom side....
Kasiopea's user avatar
0 votes
2 answers
96 views

Dry or wet etching in fabrication cmos chip?

What types of etching are used in conventional chip fabrication technologies such as TSMC 0.18, dry or wet?
seyyedali hosseini's user avatar
2 votes
2 answers
118 views

What's the typical distribution of fabric speed grades in produced dies?

Let's say I produce 1000 FPGAs, what percentage of these 1000 FPGAs are considered super fast, fast, medium, and slow? Does it look like a normal distribution, exponential, linear, etc.? Does anyone ...
Charles Clayton's user avatar
2 votes
1 answer
2k views

Difference between Logic Chip and Memory Chip front-end manufacturing process?

I understand that memory chips like DRAM Chips require a little different set of Front-end setup than logics chips. However, I am not finding anywhere how the actual manufacturing steps differ, ...
Jnanadarshan Nayak's user avatar
0 votes
0 answers
79 views

What is the pad-etching process in standard CMOS fabrication process

What is the pad etching process? Is it possible to etch to the bottom metal layers or vias in standard CMOS fabrication?
seyyedali hosseini's user avatar
0 votes
1 answer
68 views

Does melting microwires cause internal shorts

If you overheat a chip, you can melt the microwires attaching the wafer to the package. When this happens, can the melted microwires cause shorts between the pins of the chip, inside the package of ...
Tom's user avatar
  • 59
0 votes
2 answers
110 views

Are bacteria on integrated circuits problematic?

Considering the scale of IC's using sub 50nm technology, I would think that even thought fabs are incredibly clean, there would still be a substantial amount of bacteria. Do they prove problematic in ...
Michael E's user avatar
  • 278
-1 votes
1 answer
4k views

How can a MOSFET can be used as resistor and capacitor [closed]

How can a MOSFET be used as a resistor or capacitor? Please explain this line: "The DS channel of MOSFET can serve as a resistor."
Hemanth kumar's user avatar
0 votes
2 answers
188 views

CMOS NAND Image

I was looking at this image which shows a CMOS NAND standard cell. However, how can I see this depicts a NAND? A CMOS NAND has parallel PMOS and serial NMOS transistors but somehow I can't see this ...
今天春天's user avatar
18 votes
7 answers
5k views

My PCB manufacturer only requires eagle board file, and not a gerber file is it fine to go about getting the board fabricated with him? [closed]

It's my first time getting a PCB manufactured. My manufacturer only requires eagle board file, but not a Gerber file. Is it fine to go about getting the board fabricated with them? Or should I be ...
Harshit's user avatar
  • 301
0 votes
0 answers
2k views

what is parallel run length in DRC check

What exactly is parallel run length in DRC check. I understand that there should be a minimum spacing between two metals depeding upon their parallel run length. In the above figure R1 is the ...
EmptyData's user avatar
  • 101
2 votes
1 answer
220 views

How is silicon for ICs produced? [closed]

You hear in grade school that the input to silicon foundries is sand and ICs come out the other side, but you never much more about the refining process or what is actually involved in extracting ...
tarabyte's user avatar
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4 votes
1 answer
1k views

What is the purpose of the gate runner on a semiconductor die?

With reference to the image of a FET die below, the gate pad is used to make connections from the die out to the device package. But what is the purpose of the gate runner? Why does the gate ...
Q'''s user avatar
  • 464
1 vote
1 answer
325 views

Process technology: LP and LPH

My question is related to the following news regarding IC process technology: Samsung has introduced 28-nm LP HKMG and a new variant, 28-nm LPH HKMG process technology. Following abbreviations are ...
threeA's's user avatar
4 votes
3 answers
3k views

Ordering Integrated circuit fabrication [closed]

Is there IC fabrication services? You upload the IC design you want and pay. They send you physical IC of what you ordered. Something like 3D printing service, such as shapeways.com for example, but ...
Mustafa's user avatar
  • 219
7 votes
3 answers
633 views

Are silicon microbolometers inherently more expensive than conventional CMOS light sensors?

We're finally starting to see practical thermal imaging sensors (microbolometers) entering the consumer market. However, they are still vastly more expensive than comparable visible imaging sensors. ...
feetwet's user avatar
  • 2,402
3 votes
2 answers
423 views

Thermocouple welder/fixture

I need to make around 500 or more thermocouples type J 30AWG per year. Currently I am using this thermocouple welder. The process is quite tedious. I need to strip the wire, sometimes twist the wire, ...
Terrance's user avatar
1 vote
1 answer
328 views

Silicon purity and electronic feature density [closed]

During development of an integrated circuit it is my understanding that you require a silicon purity of 99.99999999%. Has this always been the case? In 1971, had the first commercially available ...
Ben Crowhurst's user avatar
18 votes
5 answers
23k views

Why MOSFET source is indicated with arrow ?

I know that , a basic MOSFET contains source and drain , and either it's a NMOS or PMOS ; it is indicated by an arrow at source . But let's look at a fabricated NMOS. Here we can easily see that ...
Anklon's user avatar
  • 1,176
0 votes
1 answer
43 views

Can the machine readable files for integrated circuits be verified by the manufacturer design team?

My question is simple if you take the chip design files (blue print files for the fabrication process) which are used by the fabrication process that the design engineer(s) have completed the files ...
VictorM's user avatar
  • 17
1 vote
2 answers
564 views

Chip Design Computer Generated Files for Fabrication Process

Could someone provide an overview of how the chip design files are used by the fabrication process? What I mean is once the design engineer(s) have completed the computer generated design blue print ...
JkT's user avatar
  • 221
6 votes
2 answers
2k views

How electronic components like diodes, capacitors, resistors are added to CPU?

I have been trying to understand how CPUs are manufactured with those large and complex circuits. But Making of CPU only talks about projecting transistor diagrams(May be that is the major part). Bu ...
Darth Pingu's user avatar
30 votes
7 answers
13k views

Is transistor the only electronic component on a CPU?

I have been reading about CPUs recently and came to know that all logical blocks and memory on CPU can be made out of transistors. So is it the only electronic component on CPU? Edit (Made after ...
Darth Pingu's user avatar
8 votes
3 answers
9k views

Why more, smaller transistors increase power efficiency?

Transistors, bjt, MOSFETs OK got it. More transistors = better computing got it. But compressing the transistors closer to each in my mind only helps reduce the physical dimensions. So does a CPU or ...
Cit5's user avatar
  • 245
-1 votes
1 answer
144 views

At any given semiconductor node, how many fabs in the world? [closed]

Let's pick a node, say 45nm. How many wafer fabs are there worldwide that can produce chips with that resolution? Tens? Hundreds? And does this mean that producing equipment for them is almost a ...
Dirk Bruere's user avatar
  • 13.8k
0 votes
1 answer
2k views

Inter die vs Intra die process variation

Due to fabrication process, there will be variations, among wafers as well as among dies across a wafer. My question is that what variations are significant between dies? And what variations are ...
Earthgod's user avatar
  • 219
1 vote
1 answer
343 views

Pick and Place File with panelized PCB

I've designed my first PCB that will be machine populated. I sent my design to a fab who is going to panelize and make the bare boards. I'm using a separate company to populate the boards. Would it ...
Colin's user avatar
  • 345
0 votes
1 answer
439 views

CMOS Fabrication Process - Ion Implantation

During the process of producing the source and drain of the MOSFET, people use a technique called ion implantation. So my question is why use ion not atom? Thanks very much!
Earthgod's user avatar
  • 219
1 vote
1 answer
417 views

BOM/OPL parts help before PCB fab

I am completing my first official PCB project. I am outsourcing the PCB fab to Seeeed Studio. I was wondering if any of you might be able to shed some light on my issue. I am using their PCB ...
scarlso9's user avatar
  • 315
39 votes
7 answers
3k views

How do I make sure my electronics design is good from manufacturing perspective? [closed]

I am a beginner in electronics design. I have some experience with fairly complex PCB design. I want to design a product that will hopefully sell a lot. How do I ensure that the design is inexpensive ...
superczan's user avatar
  • 491
2 votes
2 answers
170 views

How differential pairs should be called out on fabrication print?

I have a design that the diff-pairs (100 Ohm impedance) and single-ended (50 Ohm impedance) are routed on the same layer. To specifying the impedance, on the “Lamination Stack-up”, I am going to add ...
lhphuc's user avatar
  • 163