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Questions tagged [fifo]

FIFO (First In, First Out) is one way of managing a buffer for data

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Simplest way to interface a high-speed (125 Msps) ADC: FIFO, RAM, SerDes or FPGA

I have a 1.8 V, 125 Msps ADC (ADS4125) with an output of 12-bit parallel LVDS or CMOS. The system is operating in bursts: the data is sampled for 8 - 30 us, with a 100 ms wait time in between. I need ...
Nitrogen's user avatar
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4 answers
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Is there a canonical way to signal WS2811/2812 LED strip?

The WS2811/2812 protocol is well-defined and hence the chip now seems to dominate addressable strip lighting products. People have managed to use SPI and UART to control it, and someone even did it ...
Milind R's user avatar
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How to Decode Quaternion Data from LSM6DSV16X IMU Sensor FIFO?

I'm working with the LSM6DSV16X IMU sensor, which comes with a Sensor Fusion Low-Power (SFLP) algorithm providing a 6-axis game rotation vector (quaternion) stored directly in the FIFO. The datasheet ...
Lister Remmir's user avatar
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SX1276_FSK Modem_Maximum Payload Length

I've been scanning the SX1276 datasheet recently and found the thing that puzzled me. It says that in Packet Mode the device is using FIFO as the payload source. The maximum size is 2047 bytes for FSK/...
Bushpulbek's user avatar
2 votes
2 answers
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FT232H FIFO slow USB?

So, I have an FT232H chip, specifically this breakout. I'm trying to read data as fast as possible from it, so I've set it to synchronous 245 FIFO mode, which the datasheet says should yield up to 40 ...
Erhannis's user avatar
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Determine which clock of a compound sensitivity list triggered always block

I am trying to implement a non-synthesizable dual-clock FIFO in Verilog (solely for testbench purposes). Since the FIFO has to operate correctly even when both clocks toggle precisely at the same ...
firegurafiku's user avatar
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IIM-42352 interrupt triggers multiple times, when condition is only met once

Currently I am working with esp32-s3-mini system which communicates with IIM-42352 accelerometer via SPI. My configurations are as follows: *FIFO mode- stream to FIFO *Packet size- 16 bytes *Interrupt ...
Dominykas's user avatar
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2 answers
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Shared FIFO control module between UART, PS/2 protocol, UART is ok, PS/2 has issue locking on to packets during read

I have brought over a design from a previously provided source in my FPGA. This is the FIFO controller for my system that gets instantiated in both UART sub system, as well as PS/2 sub system. The ...
Vahe's user avatar
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1 answer
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Verification of asynchronous FIFO

I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings. The goal is to verify this design by using the Tb components, so no UVM at all. I ...
Giuseppe Trematerra's user avatar
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Asynchronous FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?

For the first time, I am approaching the world of Verification by using SystemVerilog, and I have learnt about the TB components only recently (Generator, Driver, Monitor etc.). My actual task right ...
Giuseppe Trematerra's user avatar
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Importance of ADC Speed for Accelerator Pedal Position Sensor (APPS)

We are building a electric vehicle and need an accelerator pedal position system. We have the circuit designed as shown below. When simulating our circuit, the ADC speed of the Arduino Uno seemed slow....
Kalamakra's user avatar
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How to post various register updates from FPGA to CPU?

I hope this is not too broad a question, I try to be as specific as I can. I am using a Zynq SoC with FPGA and CPU. I am using the FPGA for a lot of DSP, that depends on many register values. In most ...
tobalt's user avatar
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STA timing closure for asynchronous FIFO

I have implemented an asynchronous FIFO However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees. Both read_clk and ...
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What are the possible strategies to transfer data from an FPGA accelerator to a hard-core CPU? [closed]

I am beginning with FPGAs and I am working on an accelerator that acquires data from a microphone (Pulse Density Modulation) and extracts a single frequency from the signal. My accelerator is ...
leopicchio's user avatar
2 votes
1 answer
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VHDL FIFO w/ RAM

I've been tasked with designing a FIFO in VHDL for the block diagram below. I understand the general mechanism of how a simple FIFO works, but I've been struggling with how to connect the address from ...
AyyBotto's user avatar
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Why do most FIFO chips have a 9-bit bus?

For example, on DigiKey, many FIFO memory chips have 9-bit or 18-bit words: https://www.digikey.com/en/products/filter/logic-fifos-memory/707 Is this to be used as a parity bit? It just seems strange ...
cratonica's user avatar
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How to initialize STM32F401 DMA SPI Slave with an empty FIFO Tx? (Or how to flush it?)

I am using the DMA SPI as slave on a STM32F401. I use: DMA SPI SlaveHAL_SPI_TransmitReceive_DMA(&hspi2, pTxData, pRxData, len}; When I do this a len amount of ...
Arjuna Deva's user avatar
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Difference between Gowin FIFO and FIFO HS IP

The question: what are the differences between the two Gowin's IP modules: FIFO and FIFO HS? I can only assume, that HS stands for "high speed", hence it should be preferred over non-HS ...
megasplash's user avatar
1 vote
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Command control for axi data mover block

I am a beginner in microcontroller programming and looking for a DMA block which will be a "bridge" between SPI and CPU ( memory). I have found AXI Data Mover block in IP catalogue of VIVADO....
Franki Lee's user avatar
-1 votes
2 answers
608 views

How to avoid empty FIFO when the read clk is higher than the write clk

I have an ADC, and, in order to avoid sync problems, I have used a FIFO with two different clocks: one for the write operation, that works at the ADC clock frequency and the other, FPGA clock that is ...
Diego Ruiz's user avatar
1 vote
1 answer
321 views

MAX14830 SPI UART Bridge not transmitting

I am using a MAX14830 SPI-UART bridge. I am trying to initialize the chip and get it to transmit a few bytes out of one of its UART. I can write to the UART's THR register, which gets added to the ...
Harid444's user avatar
7 votes
2 answers
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Need for Almost Empty and Almost Full flags in a FIFO buffer

I read somewhere that some implementations of FIFOs have almost full and almost empty flags, the threshold for which can be set by any particular user. It was explained that a need for such flags ...
Varun Desai's user avatar
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Writing into a full FIFO

I am using a FIFO as a temporary memory block to store values and then perform some calculations between the neighboring values once the FIFO becomes full. After the calculations are finished, I would ...
PrematureCorn's user avatar
-1 votes
1 answer
175 views

FIFO queue: how it works? queueless?

I study FIFO by myself using tutorials and lectures which are available (free access). Currently I am reading about FIFO queue. I have read , it provide a way to ensure messages are delivered in-order ...
LeeLeeYa's user avatar
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1 answer
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SPI slave: Store received byte? [closed]

SPI slave receives bit per bit (mosi) every clk and when a byte is completed (process A), this byte of data will be sent to the next process B (FlipFlop). If process B detects byte, process A starts a ...
LeeLeeYa's user avatar
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2 answers
1k views

Using BRAM as buffer

I'm trying to implement a buffer for an image processing pipeline and need to load data into BRAM. I've been following an online tutorial (https://www.youtube.com/watch?v=n35zS__YEFQ) for implementing ...
OM222O's user avatar
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2 votes
1 answer
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Asynchronous FIFO design with PULSE synchronizer

I'm trying to understand various implementations of asynchronous FIFO from the following link https://inst.eecs.berkeley.edu/~cs150/sp10/Collections/Discussion/Honors/Honors14_1PP.pdf In the slide 7 ...
Naveen's user avatar
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Why do we use a gray encoded signal by 2 stage flip-flop in asynchronous FIFO to avoid race-condition issue? [duplicate]

In the FIFO design, to compare the rptr and wptr, we are feeding one signal into another clock domain. The rptr which is coming from the slow clock domain to faster one can be synchronized with sync ...
Carter's user avatar
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What is the specific reason for using FIFO in the asynchronous domain in VLSI?

I was wondering that the reason is of using FIFO in the asynchronous domain in VLSI. Basically, to prevent x propagation in the asynchronous domain (aka CDC domain), it was taken care of by the two-...
Carter's user avatar
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FT2232H Asynchronous FIFO mode

Has anyone seen an FT2232H port not go into the mode set into the EEPROM? I've got a device that is programmed to be in asynchronous FIFO mode on port A, but functions as though it's still in UART ...
KyleG's user avatar
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How Does One Do Block RAM Inference on Altera Cyclone 10 LP FPGA Boards in Verilog [closed]

I have tried to google for this a lot but I can't seem to find anything.
Coder Motor's user avatar
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1 answer
843 views

how to add top module port to port list

...
TheBigBoyOverThere's user avatar
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FPGA Timing Constrain Problem

I am using the Cyclone V DE1-SoC in transferring data between HPS and ...
johnny2231's user avatar
1 vote
1 answer
478 views

There is a way to write into FIFO on both clock edges?

Im using Lattice ECP3 FPGA, didnt found any information about it on the internet. I have ADC which providing me 12bits data on both clock edges, so I used Lattice High Speed I/O Interface: This ...
Michael Rahav's user avatar
1 vote
0 answers
298 views

Huge spikes and sudden offset in accelerometer data (FRDM-K64F & ADXL357)

I'm working with vibration analysis on electric motors (AC). I have a mBed FRDM-K64F with a EVAL-ADXL357 connected to it - mounted onto a motor. The device samples from the FIFO 4000 times per second,...
Mads Gliemann's user avatar
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1 answer
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FIFO Clock Setup for CMOS Detector

When attempting to construct a miniature laser beam profiler with the Omnivision OV7740 CMOS detector and an Arduino Due, I am running into some problems with FIFO reading/writing. From the datasheet, ...
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Why bad data is read from SPI Flash

I have a device in which there is a SPI flash and a I2C EEPROM, W25Q256JV (32MB) and AT24C1024 (1MB) respectively. The MCU writes data packets in the flash fifo and saves its read write pointers in ...
alt-rose's user avatar
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How to instantiate a FIFO on an iCE40 FPGA?

The Memory Usage Guide for the Lattice iCE40 FPGAs implies that the embedded block RAM can be configured in various ways, including as a FIFO, but it gives no details about how to do this. Is there ...
Rocketmagnet's user avatar
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Max baudrate of FT2232H in synchronous FIFO mode

In datasheet at FT2232H chip: The FT2232H has the following advanced functions: ... Single channel synchronous FIFO mode for transfers upto 40 Mbytes/Sec. ... I configure device ...
Aave's user avatar
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1 vote
2 answers
350 views

How to design asynchronous LIFO?

Is it possible to design asynchronous LIFO ( i.e. LIFO with different READ and WRITE clock) In FIFO , we need to change the write address pointer only on wr_clk while in LIFO we need to change the ...
Shubham Gupta's user avatar
8 votes
1 answer
4k views

gray code clock domain crossing FIFO fast to slow

I'm trying to understand how clock crossing FIFOs are implemented, and the usual answer I see to convert the read/write address pointers to gray code and then pass through synchronizer circuits into ...
user2913869's user avatar
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Does a FIFO data buffer need to have the data be registered?

I'm trying to implement a 64 bit FIFO Data Buffer in Verilog. My design allows for data to be written at 4 bytes or 1 byte at a time, and I'm simply using two multiplexers with control signals for ...
Michael Wendel's user avatar
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2 answers
2k views

Single Clock FIFO with Single Port RAM

I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
Hachani Ahmed's user avatar
1 vote
1 answer
329 views

What are the use cases of FIFO Half-Full and Three-Quarter Full interrupts in Receive FIFO of a UART?

I am implementing a protocol decoder which receives bytes through UART of a microcontroller. The ISR takes bytes from the UART peripheral and puts it in a ring buffer. The main loop reads from the ...
SRK's user avatar
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2 answers
3k views

Simultaneous write and read to/from a FIFO

Could someone, please, clarify whether or not I could simultaneously read and write from the soft FIFO described in this document on p.157? It does say that I can use separate read and write clocks. I ...
Nazar's user avatar
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571 views

Asynchronous FIFO in clock domain crossing

Clock domain crossing issue can be solved by using asynchronus FIFO with input frequency f1 is of the source domain and f2 is of the destination frequency. If the data is sent in bursts, depth can be ...
digitalman's user avatar
4 votes
3 answers
1k views

Verilog router design and best way to handle variable size packets in verilog?

I have a synthesizable Verilog/logical design question. My question is more logical than syntax. I wish to implement some sort of router that has three input/output ports of full-duplex UART RS232, ...
shush's user avatar
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VHDL: ADC to USB Buffering using Fifo

I am trying to understand what is the correct way of doing such application, so please do not ask for complete code because each component is working fine on its own. I am struggling in the way of ...
nandflash1's user avatar
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1 answer
2k views

FIFO Buffer (Circular/ring buffer) for packet storage

I am developing a simple radio transmission network using B-L072Z-LRWAN1 boards. The network structure is formed by: One board acting as a gateway (where data is received). Multiple boards acting as ...
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1 vote
1 answer
2k views

In digital logic, when given a requirement of a 64 byte FIFO, is it possible to calculate the width and depth?

I have an input device that can write in either serial, 8-bit parallel, or 16-bit parallel. I know the input frequency and max write speed of those data formats. I am given a requirement of a "64 ...
Cit5's user avatar
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