Questions tagged [fifo]

FIFO (First In, First Out) is one way of managing a buffer for data

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How to design asynchronous LIFO?

Is it possible to design asynchronous LIFO ( i.e. LIFO with different READ and WRITE clock) In FIFO , we need to change the write address pointer only on wr_clk while in LIFO we need to change the ...
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1answer
87 views

gray code clock domain crossing FIFO fast to slow

I'm trying to understand how clock crossing FIFOs are implemented, and the usual answer I see to convert the read/write address pointers to gray code and then pass through synchronizer circuits into ...
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1answer
39 views

Does a FIFO data buffer need to have the data be registered?

I'm trying to implement a 64 bit FIFO Data Buffer in Verilog. My design allows for data to be written at 4 bytes or 1 byte at a time, and I'm simply using two multiplexers with control signals for ...
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1answer
96 views

Single Clock FIFO with Single Port RAM

I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
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1answer
70 views

What are the use cases of FIFO Half-Full and Three-Quarter Full interrupts in Receive FIFO of a UART?

I am implementing a protocol decoder which receives bytes through UART of a microcontroller. The ISR takes bytes from the UART peripheral and puts it in a ring buffer. The main loop reads from the ...
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0answers
110 views

LSM6DS3 Timestamp read in FIFO

I have a LSM6DS3 sensor connected to a MCU by SPI. My goal is to fill the FIFO buffer with the following sets of data: Gx, Gy, Gz, XLx, XLy, XLz, Ts, Pd. I am using a watermark to generate an ...
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2answers
109 views

Simultaneous write and read to/from a FIFO

Could someone, please, clarify whether or not I could simultaneously read and write from the soft FIFO described in this document on p.157? It does say that I can use separate read and write clocks. I ...
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121 views

Asynchronous FIFO in clock domain crossing

Clock domain crossing issue can be solved by using asynchronus FIFO with input frequency f1 is of the source domain and f2 is of the destination frequency. If the data is sent in bursts, depth can be ...
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169 views

Verilog router design and best way to handle variable size packets in verilog?

I have a synthesizable Verilog/logical design question. My question is more logical than syntax. I wish to implement some sort of router that has three input/output ports of full-duplex UART RS232, ...
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2answers
187 views

VHDL: ADC to USB Buffering using Fifo

I am trying to understand what is the correct way of doing such application, so please do not ask for complete code because each component is working fine on its own. I am struggling in the way of ...
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1answer
847 views

FIFO Buffer (Circular/ring buffer) for packet storage

I am developing a simple radio transmission network using B-L072Z-LRWAN1 boards. The network structure is formed by: One board acting as a gateway (where data is received). Multiple boards acting as ...
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1answer
206 views

In digital logic, when given a requirement of a 64 byte FIFO, is it possible to calculate the width and depth?

I have an input device that can write in either serial, 8-bit parallel, or 16-bit parallel. I know the input frequency and max write speed of those data formats. I am given a requirement of a "64 ...
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1answer
275 views

Problem FIFO in the implementation (VHDL)

I was working in that for the past five days and I don't know what happened. I must implement a FIFO to send some information, I attach the FIFO that I use. As you can see in the code, this FIFO using ...
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2answers
135 views

Analyzing the SX1276 FIFO implementation

I've been through the HopeRF95W datasheet a couple of times; some parts less and some parts more. The Payload Data Extraction from FIFO on page 36 is really very clear and concise. Once the ...
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1answer
122 views

Programming a microcontroller

I'm quite new in this, so I was hoping if someone could put me on a right track for programming PIC24FJ128GA202 In my new work position I was handed a task to program the mentioned mcu as a learning ...
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1answer
179 views

How to simulate a FIFO in Logisim

I'm looking at prototyping a design I plan to build using logisim. The design will make use of a FIFO IC (74HC40105) as a buffer between a data producer process and a data consumer process. I can't ...
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2answers
345 views

Efficient size of FIFO buffer for UART

I am designing a software for a microcontroller that transmits and receive data from various UARTs in a loop every 15ms. I am using UART interrupts to send and receive data. UART interrupt copy bytes ...
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2answers
120 views

What's the point of buffering a peripheral

I have seen in most modern microcontrollers that the peripherals are queued using a hardware FIFO. What's the point of getting a hardware FIFO? Most old microcontrollers like PIC and AVR doesn't have ...
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1answer
93 views

Metastability Deserialization and clock crossing domain

I have a question on metastability and clock crossing domain. I need to deserialize a bitstream out of an ADC. TXCLK, TXOUT1, INCLK are the outputs of the ADC. So the idea was to register the DATA ...
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1answer
76 views

FIFO IP CATALAOG independent clocks

[![enter image description here][2]][2]I am trying to simulate a FIFO generated by the IP Catalog. I chose for the FIFO implementation an independant clock BRAM with empty full almost empty almost ...
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1answer
200 views

How does the rollback work in a FIFO?

From reading the book titled "Advanced Chip Design practical examples by verilog", I faced some questions about when the Ethernet packet is read from the FIFO and how the rollback works for the ...
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2answers
1k views

Corner Cases to Verify Synchronous FIFO

I'm trying to figure out the corner cases for verifying a synchronous FIFO during hardware verification. My setup is a very simple two ports synchronous FIFO (write/read) and the write clk frequency ...
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2answers
283 views

FPGA Internal Timing constraint failing

I'm currently trying to implement an IP-Core on a Cyclone V 5CSEBA6U23I7 FPGA-HPS System using Altera Quartus II and TimeQuest Analyzer. The Verilog code pasted below produces a timing problem, namely ...
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1answer
1k views

Asynchronous FIFO cdc question

1) Why there is no multi-bit synchronization problem for slow clock domain ? it is obvious that the pointers could increment by more than one. Screenshot from sunburst asynchronous FIFO paper page 12 ...
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1answer
845 views

Input/output from unsynchronized ADC/DAC

DISCLAIMER : this question is somehow related to this other question of mine, but the latter did not have any satisfying answer. I'm working on an audio DSP project with the STM32F4xx, using 4 ...
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1answer
332 views

How to interface an ADC with FPGA through the CLKOUT signal in verilog?

I have a ADC (TLC2323-12) that (as far as i understand from the datasheet) has two modes of controlling the output of the converted signal. One method is with the input signal SCK that can be ...
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1answer
2k views

Benefits of RAM vs FIFO in FPGA

If I want to process data in the order it arrives, it seems that a FIFO would be most appropriate; however, I want to look over the data multiple times (at least 20 times), so I am considering either ...
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1answer
574 views

Asynchronous FIFO for fast-write-slow-read

I'm not quite sure how to generate full signal in a FIFO with fast-write and slow-read. Eg., if f_wr=10*f_rd, when the updated writing pointer is synchronized to reading side using simple ...
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2answers
259 views

FIFO Memory Volatile or Non Volatile

I am referring to IDT7203 datasheet. ( MEMORY FIFO 2048X9 25NS ) Link here: http://www.digikey.com/product-detail/en/idt-integrated-device-technology-inc/7203L25J/800-2478-5-ND/2014356 My question ...
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1answer
670 views

Parallel ADC IC interface to FIFO Memory

I am referring below schematics attached here. ADC AD7821KP IC is interfaced with IDT7203 FIFO memory. Now, I want to use 12 Bit ADC in above schematics. But I am not able to find 12 bit FIFO Memory ...
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2answers
986 views

Is there a connection between circular buffer, FIFO and shift register?

I know that circular buffer and FIFO are similar but do not understand the difference that causes different terms to be used. How do these two compare with a shift register? How do I know if I need ...
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1answer
137 views

Address coding in asynchronous FIFO

To generate FULL/EMPTY for FIFO control, the reading address/writing address needs to be transferred to the writing/reading side for comparison. A solution is to use gray code for the address to be ...
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1answer
188 views

Unexpected behaviour in Altera clock crossing FIFO

As far as I am aware, in a FIFO as we keep reading it will eventually become empty i.e no more data inside and its output shall become 0x0. If we keep reading it after it has become empty, we shall ...
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1answer
517 views

PIC32 UART buffer overrun in MIDI receiver application

I have a system that consists of both a MIDI transmitter and MIDI receiver, that are separate units and connected between each other with cables. A PIC32MX6xx-series microcontroller forms the heart of ...
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1answer
762 views

How do clock crossing FIFOs work?

I am fairly familiar with the concept of metastability: You have two asynchronous clock domains, there is no way to guarantee that the data will be setup/held properly when input to a flip flop if it'...
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1answer
439 views

FPGA: Choose RAM or FIFO for ADC input to be filtered

I will connect an ADS4125 12-bit 125-MSPS ADC with 6-bit parallel DDR LVDS output, with an Altera MAX10 FPGA. The sampled data is over a duration of 100 us, and will be filtered in the FPGA. I will ...
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2answers
3k views

Difference between buffer and mailbox

Peripherals in Micro-controllers usually provide a way for us to send and receive data from it. Usually this are memory mapped registers. I have come across few terminologies. The most often used one ...
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2answers
681 views

Serial Communication Rx ISR logic design

If im not wrong, an ISR is supposed to do minimal processing when it receives a data serially(via UART). Im planning on implementing such a protocol for communication between 2 systems via uart. This ...
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1answer
69 views

Xilinx Coregen FIFO as ZeroDelay model

My VHDL design contains a FIFO generated by Coregen from Vivado 15.3. I try to debug the design with a ZeroDelay simulation. But the core is not Zerodelay and makes short changes (much shorter that a ...
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1answer
116 views

FIFO for spartan 3AN : no storage on board but ok in simulation

I made a FIFO using the Core Generator and I'm trying to implement a code that use it... 1) By putting the switch (T9) ON, I start transmitting some datas to my fifo (Here H-e-l-l-o for test) 2) By ...
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1answer
1k views

ERROR:NgdBuild:604 using FIFO in VHDL

I would like to use a FIFO in VHDL, I used coregen to make it but when I want to use it into my project, I get this error : ERROR:NgdBuild:604 - logical block 'U101' with type '...
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1answer
376 views

FIFO in VHDL : ERROR:HDLParsers:3324

I'm programming a Spartan 3AN using ISE and I would like to implement a simple code that uses a Fifo : When I push a button, a data is sent to the FIFO and when I push another button, the fifo is ...
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3answers
922 views

VGA controller using FIFO memory, discrete ICs and Arduino Uno/Mega?

I love the Arduino boards. They're super easy to use and give me access to fairly powerful microcontrollers for all of about $12. Unfortunately, 16MHz isn't quite fast enough to display more than ...
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2answers
333 views

FIFO-related data transmission problems between microcontroller and PC

I have a situation in which a microcontroller is to perform a large number of ADC conversions and format the results into commands (or data packages) and send these to a PC using the UART. In order to ...
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1answer
568 views

Different ways of using UART

What is the difference when you send/receive data via Linux serial device file like ttyS3 and when you directly read/write from/to UART FIFO buffers? What situation is more safe and better? How ...
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2answers
1k views

How can I capture VGA (640x480) frames with RGB565 format from OV7670+FIFO (AL422B)?

I made a platform with LPC1788 (Cortex M3) which had external 8MB NOR flash and external 32MB (16bit) SDRAM. I connected them a CF7670C-V3 (OV7670+AL422B (FIFO)) camera module and I capture QVGA,QQVGA ...
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2answers
895 views

ov7670 camera module [closed]

I really need some help to figure out whether the ov7670 camera module I bought is with or without FIFO. I bought it from a local market.Can someone please tell me how can I find out whether the ...
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1answer
811 views

Setup and hold time violation constraints for Xilinx Fifo generator

I have a problem concerning the Xilinx Fifo generator and timing contraints described in the fifo manual. I am using the fifo generator version 9.2 (manual ) to generate a fifo. I would like to ...
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1answer
547 views

How to interface 1 MSPS ADC with processing module in FPGA?

I have DE1-SoC board which contains 1 MSPS ADC, I am trying to take samples from ADC and process them. ADC Controller clock is 20 MHz and data is available every 16 clock cycles. The module that takes ...
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1answer
594 views

FIFO in ethernet module

In Ethernet module , why do we need FIFO block before the mac layer ? Can we bypass it ? Thanx in advance