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7 questions
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Simplest way to interface a high-speed (125 Msps) ADC: FIFO, RAM, SerDes or FPGA
I have a 1.8 V, 125 Msps ADC (ADS4125) with an output of 12-bit parallel LVDS or CMOS. The system is operating in bursts: the data is sampled for 8 - 30 us, with a 100 ms wait time in between. I need ...
- 31
0
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1
answer
600
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Writing into a full FIFO
I am using a FIFO as a temporary memory block to store values and then perform some calculations between the neighboring values once the FIFO becomes full. After the calculations are finished, I would ...
- 578
1
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1
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916
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3
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1
answer
4k
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Benefits of RAM vs FIFO in FPGA
If I want to process data in the order it arrives, it seems that a FIFO would be most appropriate; however, I want to look over the data multiple times (at least 20 times), so I am considering either ...
- 463
0
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2
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556
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FIFO Memory Volatile or Non Volatile
I am referring to IDT7203 datasheet. ( MEMORY FIFO 2048X9 25NS )
Link here: http://www.digikey.com/product-detail/en/idt-integrated-device-technology-inc/7203L25J/800-2478-5-ND/2014356
My question ...
- 739
0
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1
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Parallel ADC IC interface to FIFO Memory
I am referring below schematics attached here.
ADC AD7821KP IC is interfaced with IDT7203 FIFO memory. Now, I want to use 12 Bit ADC in above schematics. But I am not able to find 12 bit FIFO Memory ...
- 739
4
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2
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630
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Does a 250MHz FIFO chip exist?
If I have 8-bit parallel data being clocked out of a chip at 250MHz, is there some way I can buffer it? I only need to store about 1kB. Preferably this would be a FIFO. Does such a fast FIFO exist at ...
- 27.6k