# Questions tagged [fir]

Anything related to Finite Impulse Response (FIR) digital filters, i.e. digital filters whose impulse response has strictly finite duration.

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### How can I prevent my IR sensor from sensing the sunlight?

I want to use an IR sensor for object detection. An LED will be turned on if an object is detected. But because of sunlight, it's malfunctioning (i.e. always getting logic 1). So, how do I omit the ...
72 views

### How to Implement this BEMF Observer

I'm using the lecture by Dave Wilson at TI to implement a BEMF observer. I have the motor winding currents for phase A, B and C. I also have the Bus Voltage I also am in the stationary reference ...
62 views

### Xilinx FIR filter behavior

We're currently simulating some Xilinx AXI Stream Finite Impulse Response (FIR) IP cores. https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_2/pg149-fir-compiler.pdf The ...
36 views

### FIR Filter Transition Coefficient

Design a length L=40 linear-phase FIR filter using frequency sampling design with an optimum approach. Use the transiton coefficient table given in Proakis and Manolakis. My M is 39, how can I use ...
41 views

### FIR input frequencies

I'm looking at this question with answers in my book and I don't understand one part of it. It works out the input frequencies shown at the bottom. Can someone tell me how they are getting they input ...
309 views

### FIR Filter on Cortex M0

Is it possible to implement basic DSP (such as an FIR Filter) on a Cortex M0 or is the architecture too limited?
630 views

### FIR filter in dsPIC with DSP Library

I have to make a digital filter with a dsPIC30F, but I don't know much about it. I've read part of the documentation about the dsPIC30F and the DSP Library, and I found a page on Microchip website ...
315 views

### Brute-force convolution reverb in FPGA

I'm completely new to the world of FPGAs, and would like to get a sense of what is possible to achieve, and since I happen to have an interest in convolution reverb algorithms, I will use that example....
645 views

### error defining multiple parameters

I want to define 19, 16-bit parameter in a way that I can call them like b[0], b[1], b[2], ... this is my code: ...
929 views

### Linear and non linear phase FIR filter

I am a confused about linear and non linear fir filter. I have this depiction of the solution space for linear-phase and nonlinear-phase FIR filters for a given set of specifications. Region 1 ...
119 views

### Understanding digital filters, specifically their effects on time domain information, how to preserve the waveform of a signal being filtered?

According to Steven W. Smith, in his book: The Scientist and Engineer's Guide to Digital Signal Processing, when designing a digital filter, "Good performance in the time domain results in poor ...
86 views

### Find filter's frequency characteristics from its impulse response

Impulse response is defined as . Its plot looks like this: Now I am basically supposed to say what does filter do with incomming signals based on this formula or plot. How can I approach this ...
202 views

### Efficiency of FIR filter in verilog language

Implementing a 4-tap FIR unity coefficients, is this code efficient in power and area ? ...
699 views

### FIR Lattice Filters

In DSP, sometimes the so-called Lattice Filters are use, having a structure like on this picture: I wonder what the advantages of the Lattice structure are, compared to other FIR filter types and ...
1k views

### FPGA maximum frequency : limiting factor

I would like to know which in general may limit the maximum clock frequency of a circuit implemented in FPGA. In the specific case I am building some FIR filters using Quartus and simulating them on a ...
118 views

I'm working with a Analog Devices ADAR7251 Sigma-Delta ADC. It has multiple sample rates to choose from (1800 kSPS, 1200 kSPS, 900 kSPS, 600 kSPS, 450 kSPS, and 300 kSPS) but my application requires ...
460 views

### Designing circuit with a FIR filter with feedback

I am trying to implement a VHDL circuit similar to the one in this image: This Simulink simulation works as expected, but trying to implement the same in VHDL is another issue. The problem is that ...
111 views

### FIR Filter delay calculation for cascaded filters

I have created a simulink model which had two filters implemented with an FIR block cascaded in series. The first filter in my case is a moving average filter and the second one a Gaussian filter(...
226 views

### Basic FIR Filter Question

We've just started learn about FIR filters in my DSP class. The homework question is: A particular FIR filter has coefficients {b(k)} = {3, 4, -4, -3} for k = 0, 1, 2, 3. Give the output y[n] when ...
3k views

### FIR lowpass filter

I'm trying to implement a low pass filter in Verilog for use on a Red Pitaya's FPGA (XilinxĀ® ZynqĀ®-7010). The end goal is to use this as part of a laser locking system using frequency modulation but ...
82 views

### How do we balance an FIR around its center?

How do we balance an FIR around its center? I was asked this question in an interview. What does this mean? Is the center point the point corresponding to the peak of impulse response?
882 views

### How to improve my digital filter to extract DC from noises?

Digital filter description: The filter's input are sensor data and output will be provided to a PID controller. Sampling rate: 64kHz Noises spectrum: from DC to 10kHz Filter target: to get DC ...
905 views

### IIR filter concerns in PID control systems

The following diagram represents the system: Here comes some more description: The system input (ref or reference is zero). And actually the goal of the controller is to maintain the output of the ...
912 views

### What is the relation between delay of a digital FIR filter and step response of it?

My question is indicated in the title: What is the relation between delay of a digital FIR filter and step response of it? Is the delay equal to the stablization time of the step response of the FIR?
5k views

### Verilog FIR filter using FPGA

I am implementing an FIR filter in Verilog, using the DE2 board. For some reason the output out of the speakers is full of static, although it does appear to filter out some frequencies. Here is the ...
341 views

### FIR filter output result Interpretation While input is taken from ADC161S626: 16 bit

I have implemented a 20 order FIR Low pass filter, 1000 HZ cutoff frequency on Sparten - 6 FPGA. First I calculate the coefficients in Matlab, Then I directly put them in vhdl code. Here are my ...
588 views

### Confusion over binary radix usage and formatting through FIR filter (and circuits in general)

I'm having a bit of a hard time trying to get my head around binary radix's. Specifically when it comes to use them in a circuit. On their own I can understand them fine. For example, 2s complement, ...
10k views

### Time delay: digital low pass filter VS analog low pass filter

I am new on digital filter, hopefully I can get some intuitive insights here. So, here is the question: A low pass filter with 5Hz cut-off frequency is to be designed. The signals presented have ...
1k views

### Finite state machine FSM model of FIR filter in VHDL for FPGA

I want to make a FSM model of FIR, for that I need to write FIR calculation code line in FSM implementation. Here is the actual and correct code for FIR ...
157 views

### How to decide to cuttoff frequecies of filter in case of using ADC( Flow: Analog-signal to ADC to bits to fir_filter to filtered_output) [closed]

FIR filter has to be used for removing the noise. I don't know the frequencies of the noise that might be adding up into the analog feedback signal I am taking. The ADC has takes just a voltage value ...
887 views

### How to scale output of FIR filter implemented in VHDL

For a DSP school project we need to implement sound effects in a SPARTAN 6 FPGA using VHDL. We tried to keep it simple and start off with a simple (100Tab) FIR filter. As coefficients we used those ...
1k views

### Is it possible to compute delay with an IIR filter between peaks?

I am developing a project which receives accelerometer signals as input, which must then be analysed via peak-detection algorithms (among other techniques). In order to do so more effectively, I ...
562 views

### Is a IIR digital filter with a0=1 effectively a FIR digital filter?

I have been experimenting with several digital filters for my thesis recently, and while learning about the FIR and IIR kind, they seem to have similar output expressions. While using a Java class I ...
48k views

### Code example for FIR/IIR filters in VHDL?

I'm trying to get started with DSP in my Spartan-3 board. I made a AC97 board with a chip from an old motherboard, and so far I got it to do ADC, multiply the samples for a number <1 (decrease ...