Questions tagged [fixed-point]
A number with a fixed number of digits before or after an implied decimal point. It contrasts with the floating point number representation. Often used in place of floating point numbers if hardware floating point unit is not present.
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Multiplication of two binary numbers in fixed point arithmetic
I'm performing some operations with fractional numbers in a 16-bit FIXED-POINT processor.
I have to multiply the numbers \$ x=-6.35 \$, represented in \$ Q_{11} \$, and \$ y=-0.1 \$, represented in \$...
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ACS71020 current value confusing
I have a quick question regarding the ACS71020 chip. I am using SPI to communicate with this chip, and the iRMS value is represented as a "15-bit fixed point number with 14 fractional bits". ...
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Input and output array for CMSIS DSP Real FFT Q15 functions
The first question:
in the documentations for CMSIS DSP real FFT functions, it is mentioned :
The FFT of a real N-point sequence has even symmetry in the frequency
domain. The second half of the ...
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Interpretation of I2S data
I am working with a TI PCM1807 ADC (datasheet: https://www.ti.com/lit/ds/symlink/pcm1807.pdf) and try do some signal processing on a FPGA. The PCM1807 output is I2S. I was wondering how to interpret ...
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Pulse generator in Simulink Matlab
I want to generate a pulse in Matlab Simulink fixed point solver.
The step size in the Simulink fixed solver is 1e-06, but I need a pulse width of 2e-08.
The figure shows the clear requirement of ...
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How to convert fixed point binary numbers to BCD? [duplicate]
I am trying to make a calculator that can do fixed point calculations but I don't know how to display them in decimal (BCD). People have told me to use reverse double dabble but I am looking for ...
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Use floating values in VHDL code
Assume I want to have a continous sine signal as input to my VHDL code. The values will be of type float since it will take on non-integer values for example: 10.5 mA.
How do I manage these numbers ...
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Range of unsigned fixed point division in VHDL
I was thinking about the range a result signal should have to acommodate an unsigned fixed point division. Suppose we have:
SIGNAL a : UFIXED (3 DOWNTO -3);
SIGNAL b : UFIXED (4 DOWNTO -2);
am I ...
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How to represent Negative real numbers in Fixed Point representation
I find this module for the addition of two Fixed Point Numbers.
Manual for using this Module:
https://opencores.org/project,verilog_fixed_point_math_library,manual
How to add -1.5 (or any negative ...
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RFFT on 8192 samples in Q15 with CMSIS
I need to perform an FFT on a block of 8192 samples on an STM32F446 microcontroller.
For that I wanted to use the CMSIS DSP library as it's available easily and optimised for the STM32F4.
My 8192 ...
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How to break multi digit number into separate digits in VHDL?
I found the method for c language.But I do not know how to perform this in VHDL.
Let a fixed point number (12 downto -19) like 3456.478396 I need break this number entirely into separate numbers 3456....
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Two single-precision versus one double-precision unit
Suppose you are designing a floating point unit, and it is desired that it be capable of both single precision and double precision operation, in the former case not by simply expanding the single ...
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Why does signed (2's complement) binary multiplication have different procedure than unsigned?
The 2's complement binary multiplication does not have same procedure as unsigned if the both operands do not have the same sign. What is the logic behind that?
Does special consideration apply to ...
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Can fixed point division be implemented using a divider that outputs quotient and remainder?
From what I have seen, division is a highly expensive operation in terms of time or area (tradeoff). It is usually implemented as an operation of continuous subtraction of a number from another number ...
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Is it possible to show fixed point numbers as base 10 in modelsim wave?
If a person is creating a system using fixed point numbers a decimal point is implied. In this case, if one is going to use the wave window to see the result, it will be beneficial to see the actual ...
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