Questions tagged [flipflop]

A flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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In Multisim, is the IC labeled "SR_FF" active-high or active-low?

I am analyzing the flip flop IC to understand how it works. Specifically, I am using the chip labeled SR_FF. I am told that a regular, 4 pin flip flop can either be "active-high" which ...
polimorphism's user avatar
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Vivado and simulation for a 4-bit up counter

I am creating a 4-bit up counter using Verilog in Vivado. For this counter, I would like to use flip-flops to represent each bits from Q0 to Q4. For simplification, I used D flip flop to represent Q3, ...
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3 Phase Pulse Generator

I cobbled together a simple 3 phase pulse generator for a project I am working on. I've attached a picture of the circuit. I need to get a quick (~50ns) pulse on each phase. I have concerns about the ...
Brian's user avatar
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JK flip flop timing diagram

Is this JK flip flop timing diagram for the Q output correct? I just want to make sure I didn't mess anything up.
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Is it ok to supply power over recommended, but under maximum rating?

I have a PCB application, which utilizes a very small and tightly packed PCB, featuring a D-flip flop with a Schmitt-triggered inverted output, specifically the SN74AUP1G80 from TI. The datasheet ...
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Why do we add the positive clock skew to the minimum clock period?

Given the following circuit: I was told that the minimum clock period would be the sum of the setup time plus the propagation delay plus the clock skew for a positive clock skew. I was wondering as ...
EskimoJones's user avatar
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Flip-flop contamination delay definition in Weste and Harris book

In Weste and Harris book "CMOS VLSI Design: A Circuits and Systems Perspective" at the paragraph 10.4.2 "Characterizing Sequencing Element Delays" ( pag 405 in the fourth edition), ...
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How to translate 0V pulldown switch to negative voltage?

I have a circuit with a momentary switch connected between GND and a net with a pullup resistor (switch output is 0V while pressed). This switch signal is then buffered by a flip-flop before feeding ...
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Mealy FSM using SR Flip Flops: pattern detector

I was asked to design a Mealy FSM using SR Flip Flops to detect a pattern. It should detect if the pattern is either '1001' or '0110'. I was able to make the state diagram (I have attached the image), ...
Rach.1961's user avatar
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How to design a T flipflop with NAND gates in Verilog (structural design)?

From a typical circuit diagram of T flip flops made of 3- and 2-input NAND gates, I tried to implement it with this code but could not figure out why am I not getting any answer in output terminal (...
Dhrubajyoti Mandal's user avatar
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How are flipflops with SR, RS, S'R', Qn Qn' in both order equivalent to each other? [closed]

All images link: https://imgur.com/a/feKDXzd I want to understand the various variations of above and be able to draw any of the above circuits if I know how to draw one of them. latch (using NAND/...
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I am confused with the maximum operating frequency calculation of the circuit

So, according to my understanding, the max operating freq has the setup time hold time and logic delay and also the clock to output delay... So my answer is tclk = (tsu+tco) + tlogic + (tsu+tco) = 2+5+...
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Simplify one-time switch made using a flip flop

I'm trying to make a one-time, "turn-on-once" switch. I've made a simpler design before, but I seem to have lost it.  So basically, when the comparator is pulled to high, the switch turns on ...
Zipho Lunika's user avatar
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Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?

Code for a counters Verilog file: (Go to: THE LINE OF ISSUE) ...
lousycoder's user avatar
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How can I implement my binary countdown from the output of JK flipflops to two seven segment displays from 15-0?

I am currently making a 2-way traffic stoplight. The stoplight signals are now fully functional. I have no idea how I can implement the 4 bits (not including my MSB because I just need to display 15-...
Yuan Marquez's user avatar
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D latch circuit not working

I have made the attached circuit, to make a on/off switch for a power circuit. I have made the set and reset pins high. Also shorted the Q' and D. After many trials, still stuck up with the output Q ...
Sainath's user avatar
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Exiting a clock loop in Logisim

I've been trying to get a traffic light simulation working on Logisim but I've run into some issues. The way the circuit works is that I default to the green light, and when I press a button (...
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Trying to design a synchronous sequential counter circuit with a given sequence

I'm trying to design a counter circuit that counts 6 → 4 → 2 → 0 → 2 → 5 → 3 → 1 using T flip flops and I haven't been able to achieve it. I tried the steps below and designed the circuit below in ...
Durchfall's user avatar
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NAND-based bistable with momentary switch

I want to create a circuit that has two outputs, and two states, where the outputs are either "on, off" or "off, on". The state should be switchable using a momentary SPST switch. ...
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Understanding the rigorous definition of hold time

Consider the attached from Weste and Harris's (WH) CMOS VLSI Design. I follow all of the discussion and definitions except for the hold time definition. Now I am familiar with the common/heuristic ...
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Optocouplers for comparator as current detector

I'm working on the realization of overcurrent detection that will be powered by a battery supply. I successfully simulated a comparator with an operational amplifier that will set the output high when ...
Simplifier's user avatar
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6 to 0 count down timer

I'm making a 60 second timer. I already made the 1st digit in my previous question. I want it to start at 6 not 0, basically 6,5,4,3,2,1,0. I made the flipflop state table and followed the similar ...
Noobielectrix's user avatar
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Making a 9-0 synchronous down counter using flip-flops

I've been trying to make a timer that starts from 0 then counts down at 9 to 0. I've been struggling to make it. I made state tables and diagrams and for the flipflops, but when implementing to a ...
Noobielectrix's user avatar
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Why do two nonoverlapping phase completely obviate the possibility of hold time issues?

In Weste and Harris's CMOS VLSI Design, they write In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the system has too much clock skew, i.e., if one flip-flop ...
EE18's user avatar
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Master-Slave JK Flip Flop Truth Table

In my computer logic and design class, we have gone over the different types of flip flops and their representations. I understand what the goal of the master-slave configuration is but I am having ...
Tony Martini's user avatar
3 votes
2 answers
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What is the point of using set and reset in JK Flip Flop?

Here is the scheme of a JK flip flop. I know what does asynchronous reset and set, but why would we use them? In what scenarios it is needed?
tozinn02's user avatar
3 votes
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Pulldown resistor on CLK input of 74HC109

I'm having trouble understanding the purpose of R3 on the CLK input of the 74109 in this circuit: This is the Clap activated light circuit by Frank Donald. As far as I know, the 741 should be able to ...
Fabrizzio Reumann's user avatar
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Flip-flop logic for comparator of overcurrent detection

I'm working on the realization of overcurrent detection that will be powered by a battery supply. I successfully simulated a comparator with an operational amplifier that will set the output high when ...
Simplifier's user avatar
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1 input signal, two edge detectors

I have a simple rising edge detector on the top and a falling edge detector at the bottom. The switches represent low-side switched sensor. In fact, I only have one sensor. How do I use one sensor ...
VvOoGame's user avatar
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Synchronization of handshake channel with different clock domains

My course on design of digital systems uses the book "Introduction to Asynchronous Circuit Design" by Jens Sparsø. On page 156 he talks about synchronizing a handshake protocol between a ...
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The logic gate design of a positive edge triggered, master slave d flip flop with asynchronous inputs preset and clear?

I'm a computer science student who's trying to get a better understanding of the d flip-flop. My project assignment is to make a CMOS design of a positive edged d flip-flop using ff master slave and ...
Are You Sure About That's user avatar
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3 answers
290 views

Analog voltage signal threshold to latch output

I am an aerospace engineer by trade, but currently working on a little side project that involves some basic electronics now. So go easy on my ignorance ;) Here is a description of what I want to ...
radiolite's user avatar
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Is it possible to create a logic gate design for a clocked D flip-flop register where there is a synchronous reset and an enable pin?

I'm currently designing a register where there needs to exist a data input pin (DIN), Clock (CLK), Reset (RST), and a RUN pin. The register is designed such that, only at positive edges of the clock ...
RizqiBusiness 's user avatar
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Why does the waveform simulation go wrong using structural D flip flop in Verilog?

I am designing a state machine in Verilog HDL to identify a specific number sequence. I must make it in structural. When I design the DFF with a behavioral style, everything is great, but with the ...
Thiên Lê's user avatar
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3 answers
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Converting a 74LS74 and a 74LS193 to CMOS. What inputs need pullups and what needs pulldowns

I have a circuit I traced out off an old, dead PCB that came from the early 90s. It was using TTL chips back then. One thing I noticed is that it has a dual flip-flop. One flip-flop is being used as a ...
Erik Vincent's user avatar
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Navigating race condition in Verilog using blocking assignment

If I want to create a pipelined flip-flop (FF) structure, where data from the input is at the output after 2 clock cycles. This is a top-down blocking assignment code. ...
lousycoder's user avatar
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Working of the 74LS76A (JK Flip-Flop)

I have been trying to understand the logic diagram of the 74LS76A as shown in this datasheet. Let's say that the flip-flop has been cleared using the CLR input and then it becomes stable as follows - ...
Kushagr Jaiswal's user avatar
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1 answer
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74LS74 Circuit Analysis

I am a little new to digital logic circuits and found this circuit a little interesting. This is off a PCB that I desoldered and traced. It came out of a Molex terminal applicator. I was wondering ...
Erik Vincent's user avatar
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1 answer
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LTSpice Double Edge flip-flop not working

I'm an absolute beginner with LTSpice; my first test circuit uses two D flip-flops: I checked the waveform and found that the D flip-flop is not working properly Am I doing something wrong, or is ...
neuron42's user avatar
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2 answers
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Working of edge-triggered flip flop

The above circuit is a master slave flip flop. Edge triggered. The working should be: During positive cycle, master is enabled by clock, storing data. At the negative edge (transition), slave takes ...
DaveFenner's user avatar
3 votes
2 answers
826 views

What's the difference between a latch and a flip flop? I found multiple answers

So I was checking out sequential logic and I found two different circuits for flip flops (or latches, or both). Let's take D flip flop for my quesiton. There's one circuit here, showing a D flip flop: ...
DaveFenner's user avatar
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How to make one time changing state pulse?

I'm undergraduate learning the analog circuit design. I want to make a signal that changes its state only one time when the input pulse signal changes its state at first. I'm trying to use D-flip flop,...
xoo's user avatar
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Turn on/off a LED using a D-FF and a transistor

I'm trying to control a LED using some microcontroller and I designed a circuit using a D-FF and a transistor to handle it. It looks like this: So I can control when to turn it on or of by simply ...
sergiopolog's user avatar
4 votes
4 answers
313 views

Capacitor function in a flip flop circuit

I'm new to electronics and I'm trying to figure out the following circuit. The circuit turns on one of the leds when one button is clicked, if the other is clicked then the current light is turned off ...
Fahed's user avatar
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Does the master-slave JK flip-flop really solve the race condition?

The master-slave JK flip-flop is said to solve the problem of racing, as per many online resources that I've referred to. However, let's say that the initial state of the flip-flop is CLK = 0, J = 0, ...
Kushagr Jaiswal's user avatar
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1 answer
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How ideal should the clock input be for registers built out of 74HC chips?

I am a just starting my first build where a fully digital solution just isn't practical. Basically I have an old laptop I want to give away but it doesn't have any backlight on the keyboard. I have 2 ...
Aaron Butkovich's user avatar
2 votes
3 answers
369 views

On / off push button flip-flop PCB?

I'm hoping someone could guide me in the right direction. I have an ongoing project that seemed simple: to utilize a push button. When you press it once, it toggles the LEDs on; when you press it ...
Warranty_void's user avatar
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Reading Incorrect Values from Flip Flops in Non-FIFO Queue Implementation

I am working on a non-FIFO queue design using flip flops to store data elements. During testing, I encountered an issue where reading the value from a flip flop after storing a new value in another ...
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D-type flip flop current rating

I built a circuit where I use a D-type flip flop (74LS74A) to directly drive an optocoupler (LTV-817) and the circuit seems to work fine. I measured the output current from the Dff (Q) to the opto ...
meext4's user avatar
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1 vote
1 answer
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D-type flip-flop never toggles

I have a circuit with a Nexperia 74LVC1G80 D-type flip-flop. The inverted Q is connected to the D input as I want to use it as a toggle switch for the OUT_SIGNAL. Problem is that I never get the ...
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