Questions tagged [flipflop]
a flip-flop or latch is a circuit that has two stable states and can be used to store state information.
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questions
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In SR latch when apply a pulse to reset latch how the Q is changed?
Here is the initial state of SR latch both reset and set inputs are zero.
Here we apply a pulse to the reset input and it shows it changes in this way
first -
and then -
The thing that I don't ...
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2answers
156 views
+50
Analysis of two D flip-flop designs based on D latches
I am trying to create D flip-flops with D latches. Below are 2 possible ones. (Note that they are both rising-edge triggered.)
I tried to analyze their behaviors at the clock edges.
For D flip-flop 1,...
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1answer
71 views
Timing when clocking MCU off of A/D
I'd like to try interfacing a fast (80 MHz) ADC with a microcontroller system. The ADC (ADC12DL080) connects to a buffer flip flop (SN74LVTH162374) which then drives the MCU data pins about 6 cm away ...
0
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1answer
55 views
Master-slave JK flip flop (74HC73) doesn't toggle
I'm designing a traffic light using two BCD counters and a JK flip flop. The simulation works perfectly on Proteus, but not in hardware (PCB).
The traffic light is required to count from 40 to 0 in ...
0
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1answer
51 views
Output Jitter of jittery bitstream through flipflop
I have a bitstream of about 10-20 MHz coming out of an FPGA, that is obtained by Delta Sigma modulation. This bitstream is expectedly very jittery and can not be passed directly through an analog ...
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2answers
42 views
Compare output of logic gates but ignore their difference due to propagation delays
I am triggering a current source for a coil. I made a safety circuit with a bistable multivibrator, which forces the trigger sent to the hardware to have some maximum duration. This is a duty-cycle ...
7
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4answers
2k views
Why can't I make flip-flops in logic simulators?
I've been playing with a few logic simulators and don't understand why flip-flops are not working. I'm trying to implement a T flip-flop with NAND gates:
All the simulators I've tried give the same ...
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0answers
36 views
why the D-FF does not use the clock assigned by me Quartus schematic
The schematic given above is a simplified version of a design. But this is enough to explain my problem. As you can see from the schematic, clock signal of second dff is connected to (Q0' & clk). ...
0
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1answer
30 views
Counter Flip Flop D no sequence
I have the sequence: 0-3-1-2-3-1.
Making the table for this.
|Present state | Next state | D1| D0 |
| 0 0 | 1 1 | 1 | 1 |
| 0 1 | 1 0 | 1 | 0 |
| 1 0 ...
0
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1answer
54 views
Why are master-slave D flip flops preferred for pipeline stage buffers?
I'm watching a lecture on designing pipelines in HDL, and it's mentioned that the buffers (for intermediate values) between pipeline stages should be master-slave flip flops to avoid race conditions. ...
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1answer
26 views
Battery Power Control with MOSFET - One Button FlipFlop
I cannot get my head around the circuit below of a Flip Flop SR switch using one push button and only MOSFETs:
The image below seems incomplete probably due to a typo (as R3 is not shown) but I ...
2
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1answer
64 views
T_hold and T_setup help me understand?
My exam is tomorrow and there is something I don't understand in the material, so I really hope to get some help with this.
Giving the following circuit:
And giving that both FF are connected to the ...
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0answers
28 views
How to produce sound when a certain condition is met in proteus?
I've made a 6-bit counter with 6 JK flip-flops that can count from 1 to 33. After it reaches 33, the circuit will go back to zero. I want the circuit to produce a sound when the counter reaches 33. I ...
0
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4answers
119 views
Problem mapping VHDL onto development board
I have a very frustrating problem and would really appreciate some help.
I am trying to test a RAM block using the switches and LED's on board the Nexys A7-100T FPGA development board. My code is ...
2
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2answers
149 views
D-Flip-Flop Hold and Setup Timing Requirements
Update: The answer is 28ns for sure
Giving the following circuit and timing table:
Question: It's known that the time between positive-edge and negative-edge of the clock (which comes after) is ...
1
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1answer
84 views
D-Flip-Flop Hold and Setup Timing
I am solving some question to prepare for my exam but got stuck on this one and need your help.
Giving the following circuit:
Where input x gets updated 10ns after ...
0
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0answers
59 views
2:1 MUX connected to a D Flip Flop
I have to describe the function of the circuit below which is a 2 to 1 multiplexer connected to a D Flip Flop and even though I understand their functions individually I cannot really understand what ...
1
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1answer
41 views
DG flip-flop behavior?
I'm having trouble finding information related to a "DG" flip-flop as shown in Figure 2-9 of SLAU320AI:
I'm just interested in the truth table for this. I'd guess this is a gated D flip-...
1
vote
4answers
55 views
CD4013 timing question
The data sheet for the CD4013 specifies a "setup time" value, but when you look at the included waveforms, that value describes the timing between the "data" input and the leading ...
1
vote
1answer
45 views
Trouble Storing Information in D Flip Flop
So I'm really not understanding how to store bits in flip flops and have them enable for to change on a condition. Here's the general setup that I'm trying to do but it just doesn't seem to work.
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0answers
78 views
7474 flip-flop- D simulation
I'm trying to use a D flip-flop 7474 for my project.
When I tried to simulate it, this warning appears (see picture.)
My parameters for input clock are:
OFFTIME = 0.1S
ONTIME = 0.1S
DELAY = 0
...
0
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1answer
75 views
Does a 555 timer actually have a flip flop?
I'm new to electronics and have been studying the 555 timer. One of the key components within the 555 timer is the "Flip-Flop", at least that's how every resource on the internet refers to ...
0
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1answer
39 views
Implementing certain sequence of JK flipflop to the circuit using tinkercad
I am a beginner when it comes to electronics and what I'm trying to create is a circuit in which it outputs to the 3 LED (3 bits) the following sequence below using JK flip flop.
This is the picture ...
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3answers
1k views
How is the Q and Q' determined the first time in JK flip flop?
My background is in Computer Science, and this is my first time posting in electronics SE.
This is a circuit diagram of JK flip flop.
I don't understand how it works at the beginning, when the ...
2
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2answers
69 views
Capacitor for triggering negative edge J-K Flip Flop's Clock
I have some SN74LS73AN Flip-Flops which, if I understanding well, are triggered by the negative (falling) edge signal of a clock.
I wish to use a simple pushbutton as a clock, and I am aware that, for ...
0
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1answer
29 views
Unused gates on Flip Flops best practices
If I'm using a 74LS112 and I only need to use one flip flop, what are the best practices for the other unused inputs? Should I tie J, K, ~SET, ~PRESET, and CLK on the unused JK FF to Vcc?
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0answers
216 views
FSM binary number divisible by 5 truth table
I am having trouble seeing if my truth table based on the exercise's instructions is correct (mostly because the instructions are really confusing me and the TA's explanation really didn't help, this ...
0
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1answer
56 views
Need circuit to permit the lowest frequency of two input signals and stop the other one (audio)
I am working on a paraphonic signal processor which shifts the pitch of an incoming note down by a full octave. It's a relatively simple principle which I know well (Flip Flop divide down frequency) ...
1
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1answer
46 views
How is clock signal edge detection done / pros and cons of different approaches? [closed]
I'm currently learning about flip-flops, and I'm curious about the different ways in which the clock signal is handled. So far I've come across 3 different techniques:
AND-ing the clock signal with ...
1
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1answer
80 views
Finite State Machine made of JK Flip Flops in Logisim help [closed]
I'm trying to make a 4 bit finite state machine that prints out (2, 3, 5, 7, 11) in order. I have completed the next state table, flip flop transition table and the JK Karnaugh maps for all the bits. ...
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2answers
144 views
Logisim Help - Using Custom D Flip Flop
I am trying to create a D Flip Flop to use in a bidirectional 4-bit shift register, using Logisim. However, when using my D flip flop the shift register acts just as a normal register setting the bit ...
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0answers
61 views
How I can command the four switches without microcontroller
I try to command 2 SWitch H bridge rectifier (two mosfet two diode) during the positive half cycle M1 switching and M2 be considered as a secondary switch that is continuously ON. During the negative ...
0
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0answers
82 views
Questions about A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops
For A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops ,
Why ...
0
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1answer
218 views
Verilog code for this question
The question in my textbook was:
Design and implement a Serial 2’s Complementer with a Shift Register and
a flip–flop. The binary number is shifted out from one side and it’s
2’s complement shifted ...
0
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0answers
28 views
Logic.ly JK Flip Flop Input Error
I am trying to stimulate a JK Flip Flop in Logic.ly
But, when the input is 0 in the circuit shown below, there is an error, which I cannot pinpoint. How do I fix this?
This is the initial circuit:
...
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0answers
18 views
Recover correct value from unstable memory through read operation
We are given a memory with 32-bit width for each word. it has the length (N - number of rows) which is not relevant for the question. we know that the memory has a problem where at any row, one bit ...
2
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3answers
112 views
how to design a circuit that gives high output between input transition and next rising edge of CLK
I'm trying to understand how can one build a circuit that does the following functionality:
I see according to the output that I should have a D-FF, that works at Falling-Edge mode, so I need to add ...
2
votes
1answer
122 views
Rising Edge vs Falling Edge D Flip-Flops
Is there any difference between a rising edge and a falling edge triggered D flip flop? For example, a falling edge flip flop will be faster or if there will be any change in result.
Is it correct for ...
0
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0answers
53 views
CD4013 cannot drive Mosfet
General Circuit information :
Function/Purpose: After the user press a tactile and hold for 6 seconds the circuit latches and turns on the mosfet to in turn turn on the power for a system
Power ...
0
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1answer
28 views
T and D flip flop - > pin
I have found many projects(digital timers) which use D and T flip flops.
In the left bottom pin we put the clock source, can this pin be always high or always low?
And if that's possible writing data ...
0
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1answer
32 views
LC tank connected to t flip flop
A t flip flop needs a clock signal to operate correctly.
That clock signal will be provided by a LC tank circuit.
Can I just connect the CLK pin to one of the nodes of the LC circuit or is it more ...
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2answers
2k views
How does electricty flow in a flip-flop circuit? I can't understand how memory bits work with NAND gates
Consider:
simulate this circuit – Schematic created using CircuitLab
The i bit is what we want to store, and the s bit is ...
2
votes
1answer
62 views
Toggle Flip-Flop for Voltage Higher than Logic Levels
I need a T flip-flop for 24V. The purpose is to take a 24V 50% duty cycle 0.5Hz pulse wave and halve its frequency to 0.25Hz, so that the output wave toggles between 0 and 24V at the input's rising ...
3
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5answers
215 views
I understand how D flip flop works but still not understand how it “store” a bit of data in a register in a running computer
I am reading this book "Computer Architecture and Organization" by Subrata Ghosal because I'm curious about how data is "stored" in the CPU register.
When I say "data is ...
2
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0answers
35 views
How does the loopback on a non-retriggerable monostable work?
I understand how to connect a monstable multivibrator to be in the non-retriggerable mode. Just loopback the /Q to the falling edge input or the Q to the rising edge output) as in the following ...
0
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1answer
220 views
D Flip Flop design using multiplexer
I was trying to implement a simple D Flip Flop using 2 multiplexers.
Are there any errors in design?
Do you have any other suggestions about design? Thanks.
Update:
As you'd recognise I've not ...
0
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1answer
49 views
Flip-flop circuit variation
I am having troubles understanding how the following circuit works. It is from the AoE book 3rd ed. p. 196 Fig. 3.99C.
I added the resistor in red myself as I assume it was missing from the schematic ...
0
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0answers
53 views
Counter with 4 flip flops jk synchronous from 1 to 12?
I wanted to create a circuit that would count from 1 to 12 to make hours counter for the digital clock. I work on logisim. I already made counter mod 13 but don't know how to adjust from 1 to 12 (not ...
2
votes
1answer
98 views
How can a 74LS76 JK Flip Flop's outputs Q and Q-bar not be fully complementary?
I have a 74LS76 JK flip flop hooked up as follows:
You think that should be easy. But look at my scope traces of Q above and Q-bar below:
how the heck can a JK flip flop's output Q and Q-bar be not ...
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3answers
161 views
Is this D Flip Flop positive edge triggered or negative edge triggered?
It is an edge triggered D flip flop where X is input, Y is clock, Q is output.
Is this D Flip Flop positive edge triggered or negative edge triggered?
ADD (copied from a comment): Actually I am trying ...
