Questions tagged [flipflop]
a flip-flop or latch is a circuit that has two stable states and can be used to store state information.
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How do I detect a button press between MCU loop function calls?
Currently, I have a few buttons connected via an I2C shift register, hooked up to an MCU. Super simple, so not sure if it needs a schematic, but I can share one (and any other details) if needed. I'm ...
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Is my understanding on flip flops accurate?
I have done a lot of research on flip flops so to speak and I have put together my understanding, please correct were I’m wrong.
Flip flops are bistable multivibrators able to store two states (one ...
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NPN high-edge flipflop [closed]
I'm looking for a design of an NPN flip-flop that reverses its output when the input is brought high. I'm looking to use the 2N2222 for this purpose.
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Logisim - Initializing a state on a counter
Full context: I am building a stopwatch / countdown timer. The design is that there will be up/down counters that increment/decrement the time. The counters are then connected to 7-segment displays to ...
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Why does a flip-flop's outputs have to be the inverse of each other and an invalid/forbidden state discouraged [duplicate]
After reading, researching, and asking questions about flip-flops.
My understanding is as follows:
They are not the only means of storing state but are one of them.
The circuit has been constructed ...
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How to design, build and test synchronous sequential circuits using T-Flip Flops?
I want to Use T flip-flops to design the circuit specified by the state diagram of following figure. Zi represents the output of the circuit. This is my school project.
I did everything. But I cannot ...
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T flip flop from NAND gates
I recently was interested in whether a T flip flop could easily be made from NAND gates. A google search did reveal lots of examples that basically all look like an RS flip flop with two additional ...
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Why are flip flops criss crossed
I want to simulate how a computer works using logic gates, now I am trying to build out the memory aspect of it.
After looking at various articles and books I see a lot of them using flip-flops/...
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Interfacing LM3914 to CMOS logic circuitry
I built the ubiquitous battery voltage monitor using the equally ubuiqutous LM3914. It monitors a 12V battery and controls a charger.
The datasheet mentions the IC can interface with TTL or CMOS logic,...
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How to create 4-bit asynchronous counter?
I am new to Multimedia Logic and am trying to create a 4-bit asynchronous counter. I did something like this, but it doesn't work.
I'm not sure if everything is properly connected and if I was using a ...
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Stove spark igniter make the touch switch off/on
I've made a capacitive touch/on (currently on bread board) with TTP223 touch IC on active low mode and used 74HC74D as output flip flop. When I use this board near stove and power up the stove spark ...
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How to fill flip flop clock truth table? [closed]
I have this truth table that I want to fill, however, I have no idea how to read the flip-flops on the left. Can anyone provide me a minimal example of how to approach this problem?
EDIT: drawing ...
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How can one pass values to a bus in Verilog without first making a wrapper bus?
I have just defined an SR flip flop, and I need to now define a D flip flop. I am going about this by using an SR flip flop within my D flip flop. However, because I used a bus for my S and R inputs ...
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What causes the output of the flip-flop to be LOW in 555 timer monostable circuit?
Before pressing the button, the external capacitor isn't charging because of the short circuit applied across it, but the short circuit is happening because discharge transistor is ON because the \$\...
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How does this NOR gate S-R latch work?
I am unclear who the NOR gate S-R latch works.
If the input of one depends on the output of the second one, and vice versa, no output signal can be generated until we have a single gate output.
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How do shift registers work on the gate level?
I am trying to understand how a serial to parallel shift register works on the gate level. Where I want to shift/load a bit each clock cycle.
I found this schematic for a positive edge triggered D ...
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Non volatile memory on simple hardware board [duplicate]
I'm designing a low frequency board with some analog signals inputs and a few discrete logic gates which drive warning LEDs. I want to save the status of the LED even if the board is powered off. No ...
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How to increment a counter multiple times from 1 input
My circuit is for a quiz scoreboard and when the player gets 5 correct answers in a row they are awarded 3 bonus points. I have 2 separate d type flip flop binary counters to do this, one for the ...
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Advice on SIPO FIFO clock, as well as 555 timer usage
I've made a circuit which involves me entering inputs, and the result being displayed in a seven segment LED. The LED must flash on and off and display the input number at least two times in two ...
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PIC16 Configurable Logic Cell (CLC) - toggle signal
I have a 1Hz square signal (in_1) and a 1/16Hz pulse (in_2) as inputs of a PIC16F1778. The rising edges of the two signals are synchronous as shown in the picture:
I want to use the configurable ...
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What kind of latch would be best to continuously store and feed in a series of inputs?
So I've got an assignment where I've two buttons and LED screen. One button inputs a '1' and the other a '0', and when four inputs are detected the screen displays the number eg. If I typed 0011 it ...
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Flip Flop not flopping
Haven't used a flip flop since week 2 of uni (well over 20 years ago now) but had a requirement for one in a current project. I need an output that toggles after a button press. Seems like a flip flop ...
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What is the function of a forward inverter and an inverted inverter in parallel in a digital circuit?
When I was simulating a divider using two D-latch as shown below (two D-latches in series,) I found that the circuit in the red rectangular is key to the differential D-latch.
In fact, the circuit in ...
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Issue converting push switch to toggle action using a D-Type flip-flop
I'd like to convert a momentary switch in a toggle switch using a D-Type flip flop from an SN74HC74AN.
For this reason I've created and simulated a circuit like this:
All works fine on the Multisim ...
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Why does the propagation delay need to be greater than the hold time when you have two D-FFs connected like this?
In the above circuit, why does the propagation time Tp > Th? As I understand it, once the first D-FF changes value, it will propagate that value to its output, ...
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Why is the operation of this latching circuit using a momentary switch and a D-flip flop inconsistent?
I'm trying to make a toggle circuit that uses a momentary switch and D-flipflop to toggle an LED on and off.
Here is what I have breadboarded, and the logic table for the flipflop. Both resistors are ...
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Programing the ESP32 with FTDI cable
I bought FTDI’s TTL-232R-3V3 to USB Serial Converter cable to program my ESP32 board
When I decided to put the flip flop circuit to connect ESP32 reset & boot0 pins to DTR & RTS pin, I ...
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JK flip flop gate level description in Verilog gives Z output
Im trying to implement a jk flip flop gate level in verilog using nand gates but for some weird reason i dont get a proper output.
Here is my jk flip flop module:
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Synchronizing a clock enable signal with an input clock
I'm designing a basic PCB for testing equipment in lab. The goal is to take a clock input, a clock enable (from a PC indicating that the measurement is beginning), and then distribute it to a number ...
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The same Minterm Twice in a sequental D flip flop
So my professor gave me a question that I have to search the answer for, it's a sequential D flip flop circuit with this sequence.
I have searched far and wide and still don't understand how to solve ...
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What happens if clock cycle is replaced with constant high voltage in a processor?
Would the data in registers change at light speed and maybe become unstable/undefined, or would the processor stop changing state altogether?
This post says:
To give all the gates time to change ...
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To turn a ratioed circuit into non-ratioed circuit, what should be the transistor sizes for proper operation of this circuit?
The circuit is at the bottom. I know it is a ratioed circuit however, how can I convert it to a non-ratioed circuit without adding two more PMOS transistors between Vdd and the other PMOSs. Also, what ...
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What does this circuit do? (flip flop) [closed]
I am trying to understand a circuit which does two arithmetic operations of 5-bit words in 2 cycles:
Q = 2*Q - A (one cycle)
Q = 11*Q (two cycles)
What does this part do?
This is the whole circuit:
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SR Flip Flop not working
Disclosure: I’m using the iCircuit app to model the question below
When I manually construct (in iCircuit, bottom half of image)the synchronous SR flip flop it works as expected. My expectation is ...
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How come two DFF can avoid metastability? [duplicate]
In my signal processing class, my professor said using TWO flip flop can avoid metastability. But he didn't explain it well. I wonder if anyone could enlighten me here? Thanks in advance!
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How enable for latch converts to clock in flip flop [duplicate]
Latch has enable signal and we cascade latches to make flip flops. How enable for latch converts to clock in flip flop.
I mean how and why enable driven latches form edge triggered flip flops. Why ...
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Does this combinational lock circuit contain any memory?
Consider a simple lock circuit built using a 4-bit, active HIGH digital comparator. The first input is variable; it is the input that unlocks the lock. All the bits of the second input are tied to ...
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Flipflop's output voltages are 0V
I'm building a 4-bit asynchronous up counter with D flip-flops. Unfortunately the 4 output voltages are always 0V. Can someone please tell me why?
I had already placed a digital source in front of the ...
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In LTspice XVII, 74HC107 has an error, but I can't figure out what the problem is
I made a circuit like this picture above with LTspice XVII.
Q(0), Q(1), Q(2) are output, and CL is CLK (clock pulse).
JKFFs are negative-edge-triggered JK flip-flop (ie. 74HC107).
And, the graph of ...
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Trying to make a mod-10 counter with JK flip-flops in CircuitMaker but my outputs are always coming out HIGH instead of counting, not sure whats wrong
Trying to make a mod-10 counter with JK flip-flops in CircuitMaker but my outputs are always coming out HIGH instead of counting, not sure whats wrong
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I designed neg. edge-triggered jk flip-flop circuit in LTspice XVII. But, it doesn't work
Voltage sources work but, 74HC107(neg. edge-triggered jk flip-flop) doesn't work.
Output Q(0), Q(1), Q(2) turn out always 0V.
I can't understand what is the problem.....
Please help me......
And, ...
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DFLOP LTspice inputs and outputs
I want to use the symbolic form of following DFLOP in the schematic. but I don't know which pin refers to which indicator(n001, n002, ...). for a better understanding of my question, I attached an ...
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How to make this T-flip-flop circuit
I am trying to make a T-flip-flop circuit with a relay, which would:
toggle on a button press (12 V) [default state: off]
allow control from an external micro-controller (optocouplers)
allow ...
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Hold time constraint equation
I am trying to understand the equation for hold time in the Digital Design and Computer Architecture book: https://www.sciencedirect.com/topics/computer-science/hold-time-constraint
Hold time ...
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Digital logic/sequential circuit to produce one pulse for every 5 clock pulses
I'm working on a problem where I'm trying to design a digital logic circuit (sequential circuit?) to produce output Y given input A:
So the goal is to produce one pulse for every 5 input pulses.
What ...
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Impedance of JK flip flops [closed]
Lets assume we get a square wave signal output from an astable multivibrator. Can we connect the output as input of the clock signal in order to create a digital counter with some specific frequency ...
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How does an SR-latch actually work?
In case of a NOR SR-latch, if we make S = 0 and R = 0, then output Q = 1 and nQ = 0. I also know one important rule which is if we put high input in the set line (S = 1) then output Q goes high.
If S =...
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I have a JK flip-flop circuit that works in simulation, but not with real components on a solderless breadboard
I'm building a control mechanism for a seat heater in my car. Eventually, it will drive power relays to control the current to the heating elements. It works in a simulation on simulator.io, but it ...
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Standart Retiming circuit with two D type Flip Flops
I am trying to build a button(for adjusting the clock) syncroniser circuit for a seven segment clock. The button signals are of course async inputs so there needs to be retiming to make sure it goes ...
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What kind of flops does state retention synthesis take?
I have designed my own standard cell library using some commercial process technology. I am trying to synthesize a large design that is implemented as a retimed module whose latency is controlled by ...
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