Questions tagged [flipflop]
a flip-flop or latch is a circuit that has two stable states and can be used to store state information.
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How does the TI CD14538BM96 behave in response to long input pulses?
This is related to my earlier question on driving dual coil latching relays from a single logic signal.
This question is on how whether the TI CD14538BM96 monostable multivibrator can be used to ...
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How do D flip flops know the correct count sequence?
Let's say we want to show the count sequence 001->010->100->111 using D flip flops. Next step would be making a state table.
After simplifying using K-map, we get D^A=C', D^B=B', D^C=A. Then ...
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Can't make toggle with TC4013BP
Beginner to circuit building here. I tried to build the following toggle switch using one side of a TC4013BP [EDIT: I'm using a 9 V power supply, why did I write 12V? Sorry!]:
(I know, white wires ...
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D flip-flop push button schematics
I have a circuit fed by a 4.2 V Li-po battery and want to add a D type flip-flop to turn off the power by a GPIO from my ESP32.
The sequence that I need is the following:
When the battery is connected ...
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Truth table for stateful circuits?
I made this circuit, which is intended to take input signals of arbitrary pulse lengths and timings, and then when "capture" is set, synchronously output all the input signals that at some ...
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How can I improve this RAM implementation in VHDL?
I'm practicing for a lab exam and I'm trying to solve one from past years. I feel like I'm doing something wrong because I don't have much experience with VHDL.
Exam question
Write the VHDL code for ...
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Is there a single cycle wave trigger circuit?
Is there a circuit design where if the input is high (at any length of time), the output will only be one cycle at a fix amount of time?
I'm currently working on a capacitive touch switch (I'll use ...
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Asynchronous SR DFF positive edge triggered [CMOS, SPICE]
I have been following some reference designs from Texas Instruments and Nexperia, and have been trying to replicate a model in LTspice (I am aware of the one in LTspice's library, but I would like ...
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LM339 comparator not working properly in the defined window
I have designed a circuit that uses an LM2901 comparator which is used for a window in which I should get a signal. I have set two limits for the comparator: 7.7 to 8.8 V for the lower limit, and 11.3 ...
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How to generate a clock signal using an op-amp
I am trying to build a circuit which toggles a lamp on and off. I am using a JK flip-flop for the toggling action.
I want a clock pulse of 1 Hz. I know there are many ways to generate a clock pulse, ...
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JK flip-flop simulation
I'm trying to simulate JK flip-flop behavior. Everything seems to be working perfectly except that the Q output is not toggling, but Q̅ does when both J and K are up.
My circuit:
The result of the ...
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Using behavioural modelling, how do I design a positive edge triggered T flip-flop with asynchronous preset and clear?
I am having trouble doing the above.
I have written a little bit of code along with a testbench, and it requires some changes. I also need to add the conditions for preset. How do I do that?
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How does a D flip-flop stabilize?
I am trying to understand how a flip-flop stabilizes internally after setting up, before the clock starts ticking.
I assume:
An electric signal takes no time to transmit from one end of a wire to ...
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JK flip-flop in Logisim
I'm trying to create a JK flip-flop using Logisim, but I don't get an output.
Can somebody help me find the problem?
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(Logisim) D-flip-flop asynchronous reset not behaving as intended
I made the following 1-minute clock circuit in logisim that's supposed to count up to 59 seconds and then loop back to zero:
It works mostly fine, but the problem happens when it reaches 59 and loops ...
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Question about T flip-flop
I am trying to implement a switch that works like the description in the picture. In my research I came across the T flip-flop, however a T flip-flop requires a clock signal. I don't have that.
Is ...
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What actually makes a flip-flop edge-triggered?
I understand the concept of level-triggered latches, as well as edge-triggered flip-flops. What I don't understand however, is what actually makes flip-flops positive/negative edge triggered. When ...
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Need to build a counter circuit using D-type flip flops [closed]
I can only learn by examples it seems. I feel I've understood my classes well... but I cannot for the life of me decide where to begin, or link my understanding to anything practical right now.
I need ...
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555 timer diagrams Q/Q bar confusion
I've seen this in several places and am perplexed. First, I thought that the output of an SR latch was Q, and the inverted output, or 'not Q' is shown as either Q with a bar over it or denoted with a ...
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Designing a jk flip-flop that has a toggle state when j=k=0
Can we design a JK flip-flop using only NOR gates? The logic circuit implementation would look like this.
In this case the toggle state would be when j=k=0 instead of when they're equal to 1.
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How is D flip-flop typically constructed?
In textbooks and websites, we can find many different ways to build an edge-triggered D flip-flop. Some examples are shown below. My questions are:
What are the advantages and disadvantages of these ...
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Problem about output Q does not correct logic of jk flip-flop but it's look like logic of nand gate
I'm try to simulation jk flip-flop on Pspice follow pic.
Use tsmc180nm model to nmos and pmos
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How to detect a sine wave signal to trigger a logic gate? [closed]
I need a way to detect a signal input and then output it as a logic high. The signal input has a 40 kHz frequency and it's a sine-shaped signal. The amplitude is not sure, could be from 12 V to 1 V.
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Can a register be considered a sequential circuit?
If you build a 2-bit register with JK flip-flops with the objective to allow storing the bit that was last added, can this be considered a sequential circuit?
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Cascaded D-FF with Async Clocks Output Trouble
I am trying to latch the output of a D-FF_1 into D-FF_2. When I apply a rising edge to the clock input of D-FF_2, and the output state of D-FF_2 changes, the output of D-FF_1 freezes, and gets "...
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What should I fix in my settings in PSpice for simulation?
I am trying to build a D flip-flop from CMOS NAND gates.
This is the CMOS circuit to be built with NAND gates:
I can simulate NAND gate logic like this, and it works:
1 0 = 1,
0 1 = 1,
0 0 = 1,
1 1 = ...
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I can't get output voltage from flip-flop in PSpice
I'm simulation a flip-flop in PSpice, but it doesn't show an output voltage.
This is testing a flip-flop; look at Q output. It shows X(undefine). I don't know if I'm missing anything in PSpice.
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Flip-flop timing diagram problem
I am trying to understand the solution of this exercise from Floyd's Digital Fundamentals book.
I don't understand why the Q output changes in the positive edge of the 4th pulse; shouldn't that ...
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How does electricity flow in this SR latch from Petzold’s Code?
I am confused as to how this circuit is complete and hence how electricity flows through it.
Petzold explains earlier in the book that the V refers to a battery connected to ground the way in which I ...
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Modulus 11 Counter
I'm trying to build a modulus 11 counter that will count from 0 to 10 and reset at state 11 in Multisim using a 4516 counter and a D-FF based off the following figure:
Because the D-FF inserts a ...
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D-type flip flop and Schmitt trigger [closed]
I've built a D-Type flip flop + Schmitt trigger to convert a momentary switch in a toggle switch using an SN74HC74N Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset and a CD40106BE ...
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Sequential (toggle) input lock
Recently, I was working on my sequential input lock for my class assignment. The task is to make a password security system with toggle input. In my system, I have to make sure that it'll work using ...
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J-K flip-flops TTL to CMOS
The following uses 3 TTL 74SLS76N J-K flip-flops, which are active low:
However, I'm trying to figure out what the settings for the PR and CLR inputs would be using CMOS CD4027 J-K flip-flops. For ...
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Confusion with edge-triggered D-type flip-flop in code by Charles Petzold
I am confused about a circuit which is presented in Charles' Petzold's 'Code' book (Page 178), and I would like some clarification. The book says that the following flip-flop is edge-triggered:
I don'...
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Edge detection circuit causing multiple inputs
I am trying to build a shift register using only 2 inputs - a button to enter high, and a button to enter low. Since I'm not using a separate button for the clock, I need to make an edge detection ...
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How do I make a shift register from flip-flops using only two inputs? [closed]
For a project I'm working on, I need to make a serial-in shift register out of only 74LS175N quad flip-flops, and two buttons (button for input 1 and button for input 0). I also can't use ...
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Which of the following input binary conditions will produce an ambiguous state in the flip flop?
For ambiguous state, both outputs x and y must be zero(for active low) to be considered invalid i.e. of both PRESET and CLR are logic "0". Now, analysing the circuit, $$ x=a \oplus D_0 $$
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Extend classic transistor flip-flop to an n-state flip-flop?
There is the classic flip-flop using two transistors. I now tried to extend it to be able to store more than 2 states, and thought it'd be interesting to be able to extend it to 3 or an arbitrary ...
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Why do we not care about intermediate values inbetween rises of the clock with a D-type flip-flop?
I teach D-type flip-flops as part of A level computer science in a very basic way. A student asked me today why we don't care about intermediate values inbetween rises of the clock with a D-type flip-...
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Why are the outputs of the comparators in a 555 timer inverted?
I'm confused as to why the outputs of the comparators in a 555 timer are inverted (and inverted again on the NOT Q output of the flip-flop).
Would it not have been easier to leave the comparator ...
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Designing a Mod-6 synchronous counter with specific behaviors?
So a Mod-6 synchronous counter can be designed by using 3 D-flip-flops connecting the output of the previous one to the next and having the complement of the last one as the first ones input. However, ...
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SR flip-flop with Preset and Clear should not work as described
In the presented flip-flop, suppose the Enable signal is high, the S is low, and R is high. Now we set the Preset low (0) and the Clear high (1). In this condition, we expect Q=1 and Q'=0.
But ...
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How do I create a digital timing diagram based on D flip-flop signals?
We are constructing a D flip-flop using 2 latches and a control-signal coming from a clock.
The flip flop looks like this (x1 and x2 are connected to two switches, L1 and L2 are standard latches ...
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Circuit using a D flip-flop and logic gates
How do I create a circuit with two inputs A and B and one output Q using only one D flip-flop and logic gates? The circuit should perform the following when the clock ticks:
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How do I connect a D flip-flop to a common anode 7-segment display?
I have a circuit in which I have an SN74LS175N D flip-flop, which outputs Q and Q’, and an INND-TS40Y6AB common anode 7-segment display. My goal is to make it so that when Q is true, only the “a” line ...
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LTspice flip-flop not working
I am trying to simulate a simple flip-flop in LTspice but I am having issues. I have followed some other similar posts but am not able to find why my flip-flop isn't outputting correctly:
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No DC convergence issue
I am simulating a circuit consists of a clock, a NMOS, and a D flipflop.
I wonder why it gave me the error no DC convergence? How should I fix it?
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Why doesn't my discrete gate SR flip-flop work? [closed]
When I make a SR flip-flop using NAND gates and configured it as in the above circuit. Why does it simulate differently and is useless?
Here is the circuit I made:
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How would I externally drive the Reset signal alongside a classic Power-On Reset circuit?
Say I have a D Flip Flop and I have a resistor, capacitor, diode, and Schmitt buffer to keep its reset line low for a few ms during startup (as per this answer)
This takes care of power-on, but during ...
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Bistable memory cell with paired buffers instead of paired inverters
Bistable memory cells with paired inverters are very standard and basic building blocks (was used in Intel 8086 for example. ) But why not use paired buffers instead?
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