Questions tagged [flipflop]

a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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Functionality of the circuit

I made the timing diagram for this circuit, but i am not sure if it is correct. Please confirm my timing diagram and what is the functionality of this circuit? Is it to generate a pulse 5 clock cycles?...
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DRAM inspired edge-triggered D-type flip-flop

I was thinking about using DRAM cells as edge-triggered D-type flip-flop, I put the elements in falstad circuit simulator and it worked, but I am not sure on how would this translate to an actual ...
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Calculate the next state for flip flop sequential circuit

Based on my previous question, i managed to draw out the truth table Inputs for flipflops sequential circruits ...
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Inputs for flipflops sequential circruits

Not very sure if these inputs are correct before i draw my truth table. Too many lines and i am confused. JA = QB = KA = B KA = B DB = D' TC = 0
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Clock frequency divider circuit (divide by 2) using D flip flop

I was trying to implement frequency divider by 2 using D flip flop with the logic connection of ~Q to D input. I provide 2x clock frequency of 50% Duty cycle in the hardware where D flip flop is made ...
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Prevent long press in changing state on D Flip-Flop

I've made a circuit on Logisim that allows me to switch between three LEDs at the push of a button. Essentially allowing me to cycle between OFF, LED1, LED2 and LED3 repeatedly. I'm doing this using ...
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32 views

4-bit memory serial to parallel memory register circuit question

I am building a 4-bit serial to parallel memory register and I feel like so far I have gotten things right, but I'm unsure of where to connect the CLR connections. Could someone have a look at my ...
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Mod-3 asynchronous up counter using T flip flop in verilog

Design: ...
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Design this memory with D Flip-Flops

Design the following memory with D Flip-Flops. (you can use other gates or decoder if needed) The following memory has 4 one-bit locations and can access 2 locations in each moment and read from ...
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How to trigger a buzzer on a specific time?

Basically, what you are seeing right now is a circuit counter timer in Multisim. I'm using multiple JK Flip-flop here. I'm still confused on how to trigger the buzzer when it counts to 10 minutes (...
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What will happen if I initially set J=K=Clk=1 in this circuit?

Will it remain in the state \$Q = Q-bar = 0\$ as the feedback given back will always be zero? Will this lock the JK in this state as long as the \$V_cc\$ is connected? Note: I have used the word ...
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Why is there no race around condition in NOR SR latch when S=R=0(initially)?

When the IC gets connected to the Vcc+, both the NOR gates get the input 0 and 0 (low) which yields the output 1. Now since both the outputs are again connected as one of the input to each of the NOR ...
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75 views

Can I make a latch using 2 AND gates, instead of NAND gates?

I have seen that, generally, a simple latch is made using either 2 NAND gates or 2 NOR gates. Can I make a latch using 2 AND gates ?
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How to simulate flip flop noise

Or is flip flop noisy at all? would you simluate its noise as you would do with a strong arm comparator? Why is strong arm comparator noisy but not a flip flop?
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Register File for MIPS Processor

I am writing code for Register file (32 registers, each of 32 bit) for MIPS Single Cycle processor. I want writing to happen at the negative edge of the clock. As usual, reading can happen any time (...
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How to modify D-FF Setup/Hold Times using Verilog?

I am new to Verilog. I need to find a way to modify setup/hold-time and clock to output delay timing parameters. Why I need this is to simulate a problem that changes the timing parameters with some ...
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Understanding complements on inputs

I've got a problem understanding formal writing down of complements on inputs. During my laboratory exercise I was working with a device that had D flip flop embedded in it. The goal was to ...
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Initial value for 32 bit register made using D F/F in verilog

I am trying to make a 32-bit register using 32 negative edge trigerred D F/F. Here is the verilog code for D F/F: ...
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What's wrong with my timing diagram?

I have made this simple timing diagram that presents the triggering way of D flip flop. The flip flop is triggered by clock's rising edges. I am convinced that the diagram is correct signal-wise. ...
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How do you make a digital counter circuit which counts to 10 minutes and 15 minutes, it will give a signs buzzer? [duplicate]

I asked in this site before, but apperantly I don't quite understand. I want to make a digital counter circuit which it counts to 15 minutes for my big project in my campus . When the circuit counts ...
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69 views

Clock domain crossing of a bus between related clocks

Imagine I want to transfer a bus from a fast clock (i.e., 100MHz) to a slower clock (50MHz). The clocks are related (come from the same MMCM, phase aligned). The Xilinx Timing Closure User Guide ...
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76 views

Which is better latches or flip flop

I was reading about flip flops where author is convincing that it's better to use flip flop than latches. He gave following reason for it. As seen from the block diagram of Fig. 5.2. a sequential ...
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4 bit synchronous binary counter using T flip-flops

I'm trying to make a 4 bit synchronous counter using T FF. I managed to draw the excitation table and evaluated the functions but I'm unsure what the pin configurations will be. I tried connecting the ...
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Stable state and don't care

I have a latch but I can't understand what are the meaning of Un/Stable state and ...
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Expected output of DFF_2 if DFF_1 has hold violation

I am trying to figure out the output of flop DFF_2 when If DFF_1 has hold violation. My answer - DFF_2(Q) = X If DFF_2 has hold violation. My answer - DFF_2(Q) = X I understand the FF's go to meta-...
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Flip flop asynchronous reset timing

Let's say you unassert an asynchronous reset signal to a flip flop after you need to to meet setup timing but before the positive edge of the clock. You're in trouble right? Now let's say you've got ...
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How can i make my mod 10 up/down counter wrap from 0 to 9 when counting down?

I know there is something wrong with my reset logic because when counting down it starts from 5 and changes if i have any wires connected to the reset of the flip flops. I don't know how to fix this ...
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Preset and Clear in SR Flip Flop

In Practical Electronics for Inventors, Paul states the following as the pulse triggered SR flip flop: Of course there are some minor issues in the truth table. (One of the \$Q\$’s must be \$\...
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When can the output of any flip flop (e.g., JK FF) be indeterminate?

I came across following problem: In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in A. Q = 0, Q' = 1 B. Q = 1, Q' = 0 C. Q = ...
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D Flip-Flops at MCU IOs

I found below PCB from a machine. It has a MCU for control all inputs and outputs and MCU inputs and outputs go through HCT374 IC to optocouplers that isolate all inputs and outputs. What is the ...
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How do D flip-flops (dff) start up in Quartus?

If I connect Q0 of one dff to its D0, its Q0 stays 0. But if I take another dff and connect its Q1 with Q0 of the first dff through OR to his D1, its Q1 stays 1. I understood that all registers are ...
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Hold time of a D Flip Flop

which is the physical cause of hold time of a D flip flop? Why is it necessary to keep its input data constant for a certain amount of time?
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Clap switch working on 220 Volts AC

I have made this clap switch.It is working fine presently. I need suggestions for improvement for its long term use. Specifically I want to know if the capacitor based power supply is okay in this ...
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Different implementations of JK flip flop

I know following variants of SR flip flop: Using NAND-NAND combination Using AND-NOR combination I was guessing how we can obtain JK flip flop for each of these variants. I found below approach ...
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Different variations of SR latch

Wikipedia gives following circuits of flip flops: SR latch using NORs SR latch using NANDs Note that circuit 1 have R input at top and S below it. Also note that circuit 2 have active LOW inputs, ...
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Forming synchronous SR flip flop from asynchronous SR flip flop

Wikipedia gives following circuits of flip flops: SR latch using NORs SR latch using NANDs Clocked SR latch using NORs: Clocked SR latch using NANDs: I understand how circuit 3 is obtained from ...
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How JK flip flop works?

Consider below JK flip flop circuit and truth table: I was guessing how Qn+1 column in truth table is calculated. Interpretation 1 One text book says: Consider the case J=1, K=0, Qn=0, Qn'=1, line ...
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Is there possibility for a race condition in the following circuit?

On this wikipedia page, there is an example of a circuit which implements a D latch using NAND gates : Let's say the flip flop is initialized correctly (eg : Q = 0 and !Q = 1). If D = 1 and E = 0, ...
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Clock signal on toggle flip-flop - does it have to be a pulse?

simulate this circuit – Schematic created using CircuitLab I'd like to actuate a relay using a controller output that is already in use by another part of my system. This output is supposed to ...
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147 views

Which of these is the correct circuit for JK flip-flop

Are both of these correct ? I am seeing both of these in different places
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74LS74AN Binary Up-Counter

I have an issue with my binary up-counter using a 74LS74AN D-Flip Flop The issue is the following: I am trying to toggle the flipflop state by sending it a 1Hz Square wave (5V Peak) to make it toggle ...
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208 views

JK flip flop PRESET and CLEAR function

I understand that Preset and Clear inputs are asynchronous inputs which means whenever Clock signal is low one of them can immediately set the output to 1 (Preset) or to 0 (Clear) (assuming they are ...
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Obtaining D flip-flop mosfet-level schematics from CMOS layout

Could anyone help to derive D flip-flop mosfet-level schematics from the following CMOS layout described in this conference document : Open Cell Library in 15nm FreePDK Technology ?
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Clock Dividers with Clock Domain Crossing

I am doing a design in FPGA that looks like this: 100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with ...
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Long cable run for a flip-flop sensor

I have some home automation, and want to put a rain sensor far away (about 30') from my computer. (EDIT: Rainfall meter or rain gauge, not a sensor. as per Transistor) The sensor uses a mechanical ...
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Should a D Flip Flop store its input on clock rise?

I've seen conflicting descriptions and conflicting implementations of D Flip Flops, when it comes to how the Flip Flop behaves when its input value changes at the same time the clock rises. ...
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Design a synchronous sequential circuit

I can't figure out how to do this exercise: (sorry for my bad english) Design a synchronous sequential network according to the Mealy model with an input and an output which must assume the value 1 ...
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Setup and hold in flipflops

Usually the data launched at 1st clock edge will be captured at 2nd clock edge. But Is it possible to launch at 1st edge and capture data in same clock edge? The clock to capture flip flop is delayed ...
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Do Clocked/Edge triggered flip-flops have same truth table regardless of whether they are derived from NAND Latch or NOR Latch?

While going through my Basic Electronics textbook, I noticed that NAND Latch gives Q=0 for S=1 & R=0 and Q=1 for S=0 & R=1. N0R Latch gives Q=0 for S=0 & R=1 and Q=1 for S=1 & R=0. ...
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D flip-flop sequencer to light three LEDs up sequentially together and then turn them all off

This circuit should turn on three lights sequentially whenever there is a high logic level until all are lit and then turn them all off, restarting the cycle. It seems the following sequencing ...