Questions tagged [flipflop]
a flip-flop or latch is a circuit that has two stable states and can be used to store state information.
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What's the difference between these flip-flops? (images attached)
I was trying to understand how does this edge-triggered D flip-flop work:
It's very complicated, so I decided to remove Preset and Clear inputs to simplify circuit and to see what it would be like.
I'...
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VHDL code which flip flop is this?
I have some doubts with the following code,is this a flip flop JK or SR latch?
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Differences between ripple counter (e.g. 74LS161) and CMOS 4040
I have been using the 74LS161 for some tinkering, and then switched to the CD4040 because it had 3 times as many counter stages in the same package size, and I don't need preset for my purpose.
Early ...
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0answers
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Divide by 2 for “wasted spark” motorcycle rev counter input [migrated]
My motorcycle just got an upgraded ignition timing method. This new method fires the spark plugs twice each cycle which in turn increases the RPM * 2 according to the tachometer.
Is there a way to ...
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1answer
44 views
Query on Edge triggered D-flipflop using SR-latches
When clk is 0 and during this time let us assume d is 0 this drives r and rbar to be 1. Isn't this a forbidden case of SR latch?? After this state if clk and d becomes 1 at the same time wont it cause ...
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1answer
36 views
Flip-flop feedback timing problem
So this is my first question here.
I am reading this book, "Digital Electronics & Computer Design - By M.M. Mano". While I was reading the Sequential logic and flip-flops, I found this:
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1answer
29 views
SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops
Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive ...
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4answers
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Frequency divider circuit of a factor of arbitrary number
We know that using T-Flip Flops in a cascaded manner(something like ripple counter) allows us to divide the clock frequency by a factor of \$2^{n}\$ where \$n\$ stands for the number of flip-flops. ...
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Why might a D-Type flip-flop skip a beat?
simulate this circuit – Schematic created using CircuitLab
I am using a D-Type flip-flop to octave down a square wave.
The chip am using is the CD4013BE with a 10V supply.
The square wave is ...
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1answer
53 views
LED blinking circuit design
I am trying monitor activity on Rx/Tx lines of UART signals with led's. I have more number of channels(20) so i dont have place to use micro controller for this purpose. NE556 timer in monostable ...
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2answers
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Using synchronous input along with asynchronous input at the same time in a flip flop
For example let us consider an SR flip flop.
If the clear input is 0 (active low) and preset is 1 this will force the output to go to reset condition (Q=0 and Q'=1.) But if the clear=0 and Preset =1 ...
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1answer
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SR Flip-flop logic
I am trying to understand SR flip-flops from a book which uses the above circuit to describe different states that this circuit can get in. Initially, both the switches are open and the current flows ...
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1answer
71 views
D flip flop with asynchronous reset circuit design
I've been looking at the circuit for the D flip flop with asynchronous reset and I do understand how the overall circuit works, but I can't understand what the point of connecting the wire in the red ...
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1answer
62 views
You are given a free running clock with a duty cycle
You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-...
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2answers
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Flip-flop vs latch: Do flip-flops have an edge detector integrated?
As far as I know, a latch and a flip-flop are the same excepting that flip-flop only "works" with an edge of the clock (let's supose rising edge for the question.)
To make the flip-flop &...
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2answers
57 views
Mutually exclusive latching momentary pushbuttons
Here's a circuit which implements a radio button arrangement.
All switches activate the clock.
One of the switches enables a latch which has no output connection.
The other two switches each enable ...
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1answer
37 views
Synchronous counter delay calculation
My Doubt is that, This is synchronous counter, all the flip-flop are activated simultaneously Right?
Suppose at t=0 clock is activated then j0 and k0 will be activated instantly but my doubt is that ...
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1answer
59 views
SR FlipFlop Question
I am studying Digital Logic Circuit right now and I have question to ask. I have searched lot of places in order to find this answer, however due to my lack of searching ability I was not able to find ...
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1answer
59 views
Implementing Push button as ON/OFF Toggle
Here is the flow:
1) Push button once to start the motor.
2) Push button again to stop the motor.
3) Push button again to Start the motor.
. . .and so on
I am trying to implement this with flip-...
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1answer
49 views
Using RS flip-flops to solve this problem
Consider a rail with a wheel mounted on it. The wheel can move from point A to B or B to A. There is a linear sensor to track the position of wheel between A and B. At point A, the linear sensor gives ...
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T-type flip flop based on SR without additional gates?
I have a question that keeps bugging me. I know how to make a T-type flipflop from SR flipflop by using 2 additional AND gates, but I was wondering, if it is possible to create T-type from SR without ...
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1answer
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Building a T flip-flop with enable and reset using only a JK flip-flop that has no enable or reset, and use some necessary logic gates
I am confused about whether if I should use don't cares to fill in the J and K on the state table, or just use keep and change. If I use don't cares I will not get any Q inputs (as seen on the K-maps),...
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Build a T flip-flop with enable and reset using only a JK flip-flop (without enable or reset) and some necessary logic gates!
So I was told to make such circuit asked above, I am thinking that if Enable is low then Q(t+1) will be just Q(t) (like 'keep') while if enable is high then check Reset, if reset is high then Q(t+1) ...
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How to design sequential circuits using JK flipflops from output sequences of LED pairs?
How do I solve problems like these where I'm given an output sequence of LED pairs and I have to design sequential circuits using JK flipflops? what should be my approach? where would I even begin?
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How to implement a negative edge triggered D-flipflop using using level triggered D-flipflops?
Say here's a negative edge triggered D-flipflop with its timing diagram with random binary signal.
And on the other hand, here's a level triggered one:
How do I implement the negative edge triggered ...
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30 views
D flip flop problem on logisism
I have a slight problem with logisism concerning d flip flop. Please tell me if this is a bug or not : My d flip flop trigger is high level.
Thank you for any answer you may give
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1answer
132 views
PROTEUS 8.9 version Error: No model specified for CLOCK#000C. (Fast help pls.)
I did everything on my project, but I am getting these errors. How can I fix it?
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1answer
49 views
Verilog state machine not as expected
I have a simple problem, but not able to debug. I am not a novice in Verilog, but this problem seems surreal and weird. I have tried all I could to debug, but still cannot figure it out, so sking for ...
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31 views
Question About Arbitrary Sequence Counter and Changing the Sequence
hope you are all well. I have an homework which wants from me something like this:
...
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1answer
122 views
Making flip-flops using logic gates in Proteus - I'm getting gray (unknown) signals
for my school project i have to use Proteus to design my circuit. My professor told us that we cannot use any flip-flops and if we had to use them we should make them by using logic gates. I'm trying ...
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1answer
42 views
Detecting rising edges from two different inputs
I want to build a circuit with two inputs A and B and one output Q with the following behavior:
assume A and B are never high at the same time
on the rising edge of A, Q must become low (A means "...
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0answers
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How can I determine the max frequency of the clock signal for a 3 bit ripple counter
I can't figure out how to determine the max frequency at which a ripple counter functions properly.
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1answer
70 views
How to draw the stick diagram of a JK flip flop
Recently me and my friends have been tasked a project to design a frequency divider using a JK flip-flop (divide by 4).
After drawing the transistor circuit, I noticed that it was complicated for me ...
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2answers
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Confusion about when a JK flip flop is triggered
I started learning about latches and flip flops recently, and my understanding is that edge-triggered devices like flip flops ignore their inputs until the clock signal transitions from low to high or ...
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1answer
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Are there errors in the CD4013B datasheet by TI?
The CD4013B datasheet by TI contains the following statement:
Setting or resetting is independent of the
clock and is accomplished by a high level on the set
or reset line, respectively.
Table ...
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4answers
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The difference between these two D latch circuits
I simulated both ones and could not see any difference in functionality. So, what is the need for that extra NOT gate? When it is preferred?
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2answers
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Counter which counts to 5 and then turns on a led
hope you are all well and healthy during those times. I have a question which I cannot solve. Question is like this:
Design a counter which counts from 0 to 5 and then stops and turns on a led. The ...
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2answers
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What is the relevance of a !Q in the D Flip-Flop when using for a memory module?
If the purpose of this circuit is to store the value of D in Q, why should I need a !Q? Why don't use a circuit like this instead?:
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1answer
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How do I model a simple metastable flip-flop in ngspice?
Problem
I'm trying to simulate the simplest possible model for a flip-flop: two inverters connected in a circle. I'm using ngspice 31 on Arch Linux. I based my model on the CMOS SOI Inverter example (...
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1answer
24 views
Implementing a total sum with logic gates
I'm trying to implement a total sum that looks like this.
TOTAL = TOTAL + INPUT
I'm using binary adders to add and D flip flops to store TOTAL. However, whenever ...
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1answer
34 views
Preset D flip flop as 0 for total sum
I'm trying to implement a total sum that follows this code
SUM = SUM + INPUT
SUM and INPUT are 5 bit signals in binary. I know how to implement the adder and i ...
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2answers
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How to output downsampling bus in single stream on fpga? (verilog)
Im working on a block which implements downsampling.
In general it not hard at all to do simple downsampling, all I need is the factor which I should downsample by, and the data input, Im just using ...
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2answers
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Which is slow among the two? Latches or Flip-Flops?
I have a question regarding latches and flip-flops. Which of them, is faster? Please explain me this with a suitable reason.
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1answer
109 views
4-bit shift register wont work (unknown state)
I must design a 4-bit shift register circuit. I am pretty sure that I need 4 D flip-flops sharing the same clock. right??
So I did that and here is the result:
As you the LED lights are neither ...
2
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1answer
41 views
Why do we reset/clear at 1010 (10) when designing a BCD Ripple Counter
Shouldn't we reset at 9, I believe that a decade counter goes as follows '0->1->2->3...->8->9->0" or at least that's how its done for synchronous BCD counters.
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Why does this input pin stay high?
simulate this circuit – Schematic created using CircuitLab
I am working on a project with some 8-bit D-Flip-Flops (using CMOS logic), feeding the first output into the second, the second into ...
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1answer
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Do I have to protect the CD4013 outputs from short circuits?
I'm trying to determine whether a CD4013BE ("CMOS Dual D-Type Flip Flop") can take damange if one of the outputs (Q or Q-bar) is set to high, but shortened to ground (or vice versa) with no resistor ...
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1answer
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3 bit synchrous up-counter stops at six but it need to be stop at seven
I am trying to design a 3-bit counter circuit with jk flip flops that count from 0 to 7 with a clock signal and remain constant at 7 until reset.
Counter counts well but it stops at six not seven.
My ...
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2answers
87 views
What does the T stand for in “T flip-flop”?
The meaning of the letters J and K in "JK flip-flop" was previously discussed here, and the meaning of the letter D in "D flip-flop" was previously discussed here.
What does the T stand for in "T ...
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How to build a selector
So I've been looking at this problem for a couple of hours, and I'm pretty sure I need to use finite state machines or at least some kind of memory elements to solve it... it goes as follows:
"A ...
