Questions tagged [flipflop]
a flip-flop or latch is a circuit that has two stable states and can be used to store state information.
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Deriving state table /equation confused
A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output z. The flip- flop input equations and circuit output equation are
JA = BX+B'Y' KA = B'xy'
JB = A'x KB = A +...
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2answers
48 views
Low power dual edge detector using too much power
I am creating a hobby circuit which transfer signal to edge triggered pulses. I created circuit like this:
But I have issue with power consumption. XOR gate need power which take 8mA which is really ...
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1answer
37 views
Finding functions for JK / D / T flip flops
I am trying to understand this concept of flip flops. Given some Karnaugh Map, all I need to know is how to find the functions of various flip-flop types:
sr flip-flop (\$s = \text{ ??} \quad r = \...
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3answers
981 views
Detect the first rising edge of 3 input signals
I have 3 input signals which are pulse waveforms The output is switch to high once once all 3 first rising edges of 3 inputs are detected.
Is there a digital circuit from logic gates, flip flop that ...
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1answer
101 views
Designing a special 4-bit counter with flip flops
This is a normal design of 4-bit counter using D flip-flops
The outputs Q0 to Q3 are connected to diodes. I want to modify this counter in such a way that it follows the following counting sequence ...
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3answers
82 views
Is it possible to get complementary clock output from a clock generator such as a 555 timer using simple digital logic?
I'd like to get complementary output from a 555 timer. I've seen previous suggestions of using a D Flip Flop, which is a fine suggestion, however that halves the frequency at the outputs of the flip ...
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1answer
24 views
How to hold a data during N clock cycles using DFFs?
I want to hold a data during N clock cycles using posedge sensitive DFFs.
The timming diagram would look like:
What will be the equivalent circuit?
Thanks
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1answer
317 views
Is there a right way of implementing a T flip flop in verilog wrt using reset signal?
I made a t flip flop using structural modeling in verilog.
...
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1answer
23 views
CMOS IC Dynamic Edge-Triggered Flip Flop setup and hold time calculation
Before explaining i should point out that i refer to changes of signals in the text as a reference change on which i will calculate these times as 50% change of one signal to 50% change of the other ...
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2answers
74 views
Why the replacement of 7812 with R-78E12-0.5, DC/DC makes the circuit not working?
I have this simple surge protector and soft start inside the PSU. My transformer is out of its specifications yields 21.3V after bridge rectification. And 0.1A load (12V fan for cooling pass ...
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0answers
43 views
Flipflop value a long time after startup
After power up in an ASIC, is it save to assume that all flipflops are in a stable state ('0' or '1')? I do not care in which stable state they are, but it is crucial that all metastability has ...
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1answer
26 views
karnaugh maps simplification
I'm in the process of making a JK arbitrary sequence counter and I'm now making the k maps to get a logic equation. I was just just wondering if this is allowed (looping the bits around the middle bit)...
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3answers
155 views
What's wrong with my interpretation of what should happen in the circuit and what's happening? [closed]
Here is what I expected to happen:
A B C D
0 0 0 0
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
0 0 0 0
...
Initially, suppose all flip flops have output 0. Then, Q' of the ...
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0answers
56 views
Home brew CPU register trouble shooting
update
Apparently I’m an idiot. It took me this long (hours) to check the supply voltage of the flip flops, which was at .25 volts from a bad connection. Rookie mistake. Hard lesson learnt.
In the ...
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3answers
91 views
Build a nearly 50% duty cycle, adjustable oscillator using D-FF
Starting from an example circuit, I'd like to simulate and physically realize a D-FF circuit that generates a 50% duty-cycle clock.
Scope of this:
Clock generator for a test circuit
Out 0-5v
I don'...
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2answers
51 views
Creating D-latch using Nand gates in Logisim?
I have designed a D-latch using NAND gates. The problem is when I convert it into a subcircuit the output is False no matter what my second input(clock input)is? It only works if I put the default ...
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0answers
31 views
Creating coder of MFM linear code (Miller) using logic gates
I have a problem with the implementation of my MFM encoder using logic gates (in the CEDAR program). It's not working correctly, and I don't know if this is software problem, or if I'm doing something ...
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2answers
63 views
Master-Slave D flip fop
The master slave D flip-flop, is it used to prevent glitches in the data signal?
Say, when there is a transition between LOW -> HIGH or HIGH -> LOW in the data signal when clock signal is at level ?
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2answers
59 views
JK flip flop integrated circuit (7473) toggle malfunction
I built a state machine using JK flip flops, I tested it but I kept getting seemingly random results. I decided to test each jk flip flop individually.
Here is the schematic for my testing:
simulate ...
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0answers
33 views
Analysis of Sequential Circuits - Derive the state Equations from the Diagram
How can I derive boolean expression for this diagram?
This is my answer:
D0 = Cnt ⊕ Z D1 = ZCnt' + ZQ'Cnt + ZCntQ'
For D1, I don't know what will be the expression if the input came from ...
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votes
3answers
69 views
Deciding which assembly is more common positive edge detector
I know of two circuits which can act as edge detector:
A clock connected as a voltage source across a RC component where resistance is composed of a diode and a resistor and this in series with ...
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0answers
64 views
Sawtooth oscillations in bidirectional bus splitter [duplicate]
I am trying to listen in on a SPI-like protocol which is transferred on one busline in both directions (no slave-select). To discriminate which data is sent by which side, I need a bus splitter that ...
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1answer
52 views
De Morgan's Theorem applied on the SR Flip Flop characteristic equation
How the second equation is resulting by applying only De Morgan's theorem on the first one?
How does the second one helps you build the SR flip-flop with only NAND gates?
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1answer
23 views
How to convert asynchronous set FlipFlop Hard macro into asynchronous reset FlipFlop?
My query is, if there is a asynchronous set flop in a library but the implementation or RTL required a asynchronous reset flop, how to achieve this?
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2answers
295 views
How to reverse direction of stepper motor with flip-flop
I am trying to reverse the direction of a stepper motor. The stepper motor drives a scanner head and when it gets to the end, I want it to reverse direction. I have some photo interrupters that ...
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1answer
45 views
IC 555 as monostable multivibrator
How is the output of a monostable multivibrator affected if the trigger pin is kept at a negative voltage (0V)?
The upper voltage reference comparator will change its output to logic 1, while the ...
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2answers
69 views
What's the difference between a hardware register and a shift register?
There are two different wikipedia articles but they don't articulate the difference very clearly. Is the main difference that the shift registry uses a clock?
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2answers
36 views
Output Register and pipeline implementation
In his book "Finite State Machines in Hardware: Theory and Design (with VHDL and SystemVerilog)" the author said : 'The optional output register can be used to obtain a fully pipelined implementation ...
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2answers
63 views
Howto debug ngspice error PPerror: syntax error during transient analysis
In an effort to better understand software and how my computer actually works I have been experimenting with simple electronic circuits.
I am working up to having three two bit registers (A, B, C) ...
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1answer
158 views
Why are latches level triggered and flip flops edge triggered?
I know what it means to be edge or level triggered but considering the block diagram or logic diagram of inside of latches and flip flops I cannot see what inside them specifies this property of each, ...
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1answer
31 views
Altera FlipFlop stuck at GND
I'm trying to make a counter that counts: 0,1,2,3,4,5
I need this for a frequency divider of 6
So I made this table:
From this I get:
J0= 1
K0= 1
J1 = NOT Q0 AND Q1
K1 = Q1
J2 = Q1 AND Q2
K2 =...
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1answer
46 views
flip flops RS(with NOR gates or NAND gates)
Being a total newbie, I have been reading about logic gates. I got some doubts
about flip flops RS(with NOR gates or NAND gates). The flip flops are said to keep a previous state so:
Why an AND gate ...
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2answers
96 views
How would I finish out this mini project (emitting 1 whenever 101 is read)?
Design a Moore finite state machine that detects 1 0 1 in consecutive
digits in the input stream of 0's and 1's received every clock cycle.
The circuit should output a 1 when it detects 1 0 1 ...
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1answer
97 views
Shift register using dff verilog
I want to create a shift register using d-flip-flop as basic structural element,
code:
dff:
...
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1answer
47 views
What happen to a dff(flip flop) without input?
I have this question but I don't know what happen to a dff without an input is it always 0 ?? like this picture below the 2nd dff hasn't any d ??? Also, if someone can draw the answer of the question ?...
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1answer
135 views
D Flip Flop Toggle — Q into Hex Inverter into D, Unstable Output, Help
simulate this circuit – Schematic created using CircuitLab
I created the above circuit. There is essentially a switch that is normally high. I press a button. Using a NTE4049T hex inverter, ...
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1answer
50 views
monostable Eccles - Jordan multivibrator, theory
I’ve a few problems and questions to the principle of monostable multivibrator’s work. Basic schematic is as below:
What is the reason for D1, C1, R3 elements at input? Why I can’t just tie a ...
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1answer
221 views
How to create a state transition table for a Mealy machine
I'm trying to design the counter shown in the diagram below with the counting sequence 123456 (i.e X1=1, X2=2, ...) as a Mealy machine.
However, I'm having trouble figuring out how to create the ...
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1answer
96 views
How is asynchronous reset physically implemented in a flip-flop?
In Cliff Cumming's excellent paper on asynchronous vs synchronous resets, the following paragraph about the risk of metastability appears on page 19:
Attention must be paid to the release of the
...
3
votes
1answer
461 views
Why ripple counter increments on each 8th pulse
I have connected the ripple counter CD4020 to an Atmega328, which sends a 50ms (low logic level) pulse to the CD4020's input each second and monitors all of its 12 outputs.
However instead of ...
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2answers
1k views
No Q bar on flip-flop
I'm currently using Quartus and I'm trying to make a 4 bit counter. I noticed that when I imported the built-in flip-flop that there is no Q bar output. It's the same issue with the JK flip-flop as ...
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1answer
83 views
Design a T flip flop and draw the asynchronous state diagram
I am supposed to design a T flip flop using logic gates (asynchronous sequential circuit) and also draw the state diagram. I don't really understand why the output doesn't change from 0 to 1 when ...
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2answers
50 views
What would an acceptable replacement be for a discontinued Motorola HCT174A?
I am trying to replace a Hex D Flip-Flop on an Amiga A4000 motherboard. The original chip has the label
HCT174A
XAA346
I believe the datasheet describing this ...
5
votes
3answers
1k views
I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?
A schematic by Lattice Semiconductor includes the diagrammed D flip-flop. This D flip/flop accepts, among others, a Set/Reset signal.
I would have understood a Set signal. I would have understood a ...
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1answer
60 views
Question about SR latch timing
I have a question about how SR latches work:
To my understanding the real-world implication is that one of the two gates will receive power first and produce an output signal, and they aren't going ...
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2answers
45 views
Difference between low signal and no signal for a SR latch?
I am struggling to understand how the SR latch works.
When an input has designation 0, this means "low signal" correct? Is this completely different than "no signal"? Doesn't a logic gate need some ...
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1answer
199 views
JK Flip Flop Not Toggling in Logic.ly
This may be simply a logic.ly issue. I'm trying to simulate a JK flip-flop in logic.ly/demo using two AND gates and 2 NOR gates, but the simulation does not work when both inputs are high and the ...
2
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1answer
524 views
Implementing circuit with d-flipflop in verilog
I'm fairly new to Verilog and I'm currently trying to do a structural implementation of a circuit that consists of an d flipflop, it has inputs x and y, x and y are exclusive or'd and that result is ...
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1answer
52 views
Using 2 Data Flip Flops to create an up counter from 0 to 3 and repeats
I've done most of the legwork. I've got this design working using 2 set reset(SR) flip flops, but I need to make it using 2 data flips, a.k.a D flip flops.
What I did:
Note the numbers not in ...
0
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1answer
304 views
8-bit synchronous up/down counter [Logisim]
I am trying to create an 8-bit programmable up/down counter using D Flip flops. So far, this is what I have:
The first 3 flip flops function correctly for both up and down, but the 4th doesn't. I ...
