# Questions tagged [flipflop]

A flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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### Flip flop circuits and delay

Is it possible that if you input data in a malformed way to a flip flop (malformed meaning for example abnormal voltage, or any other condition) it can cause it to get "stuck" on a specific ...
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### Is it correct to say that a D Flip Flop only stores a given value for a single Clock Cycle?

With respect to D Flip-Flop's, is it correct to say that a given value is only stored for the duration of one Clock Cycle? I'm completely new to the topic of Flip Flops, but I believe I have a solid ...
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### Master-Slave register with dynamic CMOS logic

I just cannot understand the operation of this circuit: (there is an error in the transmission gate, the yellow "0" ... but whatever) If the input (light blue) is 0 and the gate is closed (...
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### Flip flop circuit

When I search the circuit of a flip flop I often find: But sometimes it's drawn like this: I suppose there are several ways to create a flip flop ... but I am not clear on the difference between the ...
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1 vote
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### In flip flop datasheets, why is the clock input called CP?

Why is the clock input pin in flip flops referred to as CP? Is there a reason to avoid referring to it as CLK? Link to example datasheet: https://www.mouser.com/datasheet/2/916/74LVC1G175_Q100-1480587....
1 vote
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### Convert binary number in flip-flop for use with mux select lines?

If there is a binary number stored in a flip flop register, how can I convert this into a single positional bit in another flip flop register? For instance, if the number is 11b or decimal 3, I want ...
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### Wiring the output of a D flip-flop to its input

I've got a simple question about flip-flops, particularly the SN74LS175. I want to know if it's possible to wire the output of the flip-flop through some combinatorial circuit and then back into the ...
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### Help Needed with Compact Circuit Design for Pulse-Triggered Switch-Off Sequence

I am currently working on a small electronics project for my swimming club and could use some advice. Forgive me if this is basic, I'm really new to electronics. The project requires a compact circuit ...
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### LT spice, JK Flip Flop: Wrong behaviour when J K and Clock are high

Here's a picture of a JK Flip Flop I try to simulate with NAND gates: This is the behavior I would expect; if Clk, J and K are all high, Q_n+1 should be negated Q_n: However this is what I'm ...
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### Is it possible to use a 2 flip-flop synchronizer for reset?

I have seen designs for asynchronous resets synchronization like in this picture: I think I understand the asynchronous assertion and synchronous deassertion that this design delivers. I am not ...
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### Where do I need give my inputs to this three stage master slave flip flop?

In his paper on TSPC logic, professor Razavi talks about use of the following topology as a master slave flip flop However, I don't know where to give input to this circuit while trying to simulate ...
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### 3 bit Asynchronous Counter

> Blockquote In our lab, using digital trainer kit, we designed the 3 bit asynchronous counter using JK flip flops by connecting clock to pin 1, following this circuit: We had three inputs that ...
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### Why isn't the CLK input manipulated directly in flip flops?

In Ben Eater's video he uses a circuit below to create a D-Flip-Flop with a LOAD pin. From my understanding, the circuit makes it so that the flip flop only loads in D1 or input when LOAD is high, ...
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### A good rising edge D Flip Flop CMOS implementation

I'm currently trying to create a basic CPU with SOT32 CMOS transistors. I have made a good design and architecture and began testing and ordering PCB's. However, I found that there are a lot of rising ...
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### Modeling Flip-Flops (RS, T, JK) in Verilog

I encountered an unusual behavior while simulating flip-flops in Verilog using Vivado. Take, for instance, a four-bit up counter where I used an RS flip-flop for the most significant bit (...
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### In Multisim, is the IC labeled "SR_FF" active-high or active-low?

I am analyzing the flip flop IC to understand how it works. Specifically, I am using the chip labeled SR_FF. I am told that a regular, 4 pin flip flop can either be "active-high" which ...
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### Vivado and simulation for a 4-bit up counter

I am creating a 4-bit up counter using Verilog in Vivado. For this counter, I would like to use flip-flops to represent each bits from Q0 to Q4. For simplification, I used D flip flop to represent Q3, ...
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### 3 Phase Pulse Generator

I cobbled together a simple 3 phase pulse generator for a project I am working on. I've attached a picture of the circuit. I need to get a quick (~50ns) pulse on each phase. I have concerns about the ...
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### JK flip flop timing diagram

Is this JK flip flop timing diagram for the Q output correct? I just want to make sure I didn't mess anything up.
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### Is it ok to supply power over recommended, but under maximum rating?

I have a PCB application, which utilizes a very small and tightly packed PCB, featuring a D-flip flop with a Schmitt-triggered inverted output, specifically the SN74AUP1G80 from TI. The datasheet ...
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### Why do we add the positive clock skew to the minimum clock period?

Given the following circuit: I was told that the minimum clock period would be the sum of the setup time plus the propagation delay plus the clock skew for a positive clock skew. I was wondering as ...
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### Flip-flop contamination delay definition in Weste and Harris book

In Weste and Harris book "CMOS VLSI Design: A Circuits and Systems Perspective" at the paragraph 10.4.2 "Characterizing Sequencing Element Delays" ( pag 405 in the fourth edition), ...
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### How to translate 0V pulldown switch to negative voltage?

I have a circuit with a momentary switch connected between GND and a net with a pullup resistor (switch output is 0V while pressed). This switch signal is then buffered by a flip-flop before feeding ...
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1 vote
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### Mealy FSM using SR Flip Flops: pattern detector

I was asked to design a Mealy FSM using SR Flip Flops to detect a pattern. It should detect if the pattern is either '1001' or '0110'. I was able to make the state diagram (I have attached the image), ...
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### How to design a T flipflop with NAND gates in Verilog (structural design)?

From a typical circuit diagram of T flip flops made of 3- and 2-input NAND gates, I tried to implement it with this code but could not figure out why am I not getting any answer in output terminal (...
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### How are flipflops with SR, RS, S'R', Qn Qn' in both order equivalent to each other? [closed]

All images link: https://imgur.com/a/feKDXzd I want to understand the various variations of above and be able to draw any of the above circuits if I know how to draw one of them. latch (using NAND/...
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1 vote
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### I am confused with the maximum operating frequency calculation of the circuit

So, according to my understanding, the max operating freq has the setup time hold time and logic delay and also the clock to output delay... So my answer is tclk = (tsu+tco) + tlogic + (tsu+tco) = 2+5+...
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### Simplify one-time switch made using a flip flop

I'm trying to make a one-time, "turn-on-once" switch. I've made a simpler design before, but I seem to have lost it.  So basically, when the comparator is pulled to high, the switch turns on ...
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### Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?

Code for a counters Verilog file: (Go to: THE LINE OF ISSUE) ...
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### How can I implement my binary countdown from the output of JK flipflops to two seven segment displays from 15-0?

I am currently making a 2-way traffic stoplight. The stoplight signals are now fully functional. I have no idea how I can implement the 4 bits (not including my MSB because I just need to display 15-...
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### D latch circuit not working

I have made the attached circuit, to make a on/off switch for a power circuit. I have made the set and reset pins high. Also shorted the Q' and D. After many trials, still stuck up with the output Q ...
1 vote
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### Exiting a clock loop in Logisim

I've been trying to get a traffic light simulation working on Logisim but I've run into some issues. The way the circuit works is that I default to the green light, and when I press a button (...
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### Trying to design a synchronous sequential counter circuit with a given sequence

I'm trying to design a counter circuit that counts 6 → 4 → 2 → 0 → 2 → 5 → 3 → 1 using T flip flops and I haven't been able to achieve it. I tried the steps below and designed the circuit below in ...
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### NAND-based bistable with momentary switch

I want to create a circuit that has two outputs, and two states, where the outputs are either "on, off" or "off, on". The state should be switchable using a momentary SPST switch. ...
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### Understanding the rigorous definition of hold time

Consider the attached from Weste and Harris's (WH) CMOS VLSI Design. I follow all of the discussion and definitions except for the hold time definition. Now I am familiar with the common/heuristic ...
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### Optocouplers for comparator as current detector

I'm working on the realization of overcurrent detection that will be powered by a battery supply. I successfully simulated a comparator with an operational amplifier that will set the output high when ...
1 vote
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### 6 to 0 count down timer

I'm making a 60 second timer. I already made the 1st digit in my previous question. I want it to start at 6 not 0, basically 6,5,4,3,2,1,0. I made the flipflop state table and followed the similar ...
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### Making a 9-0 synchronous down counter using flip-flops

I've been trying to make a timer that starts from 0 then counts down at 9 to 0. I've been struggling to make it. I made state tables and diagrams and for the flipflops, but when implementing to a ...
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### Why do two nonoverlapping phase completely obviate the possibility of hold time issues?

In Weste and Harris's CMOS VLSI Design, they write In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the system has too much clock skew, i.e., if one flip-flop ...
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1 vote
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### Master-Slave JK Flip Flop Truth Table

In my computer logic and design class, we have gone over the different types of flip flops and their representations. I understand what the goal of the master-slave configuration is but I am having ...
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### What is the point of using set and reset in JK Flip Flop?

Here is the scheme of a JK flip flop. I know what does asynchronous reset and set, but why would we use them? In what scenarios it is needed?
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### Pulldown resistor on CLK input of 74HC109

I'm having trouble understanding the purpose of R3 on the CLK input of the 74109 in this circuit: This is the Clap activated light circuit by Frank Donald. As far as I know, the 741 should be able to ...
1 vote
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### Flip-flop logic for comparator of overcurrent detection

I'm working on the realization of overcurrent detection that will be powered by a battery supply. I successfully simulated a comparator with an operational amplifier that will set the output high when ...
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### 1 input signal, two edge detectors

I have a simple rising edge detector on the top and a falling edge detector at the bottom. The switches represent low-side switched sensor. In fact, I only have one sensor. How do I use one sensor ...
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### Synchronization of handshake channel with different clock domains

My course on design of digital systems uses the book "Introduction to Asynchronous Circuit Design" by Jens Sparsø. On page 156 he talks about synchronizing a handshake protocol between a ...
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### The logic gate design of a positive edge triggered, master slave d flip flop with asynchronous inputs preset and clear?

I'm a computer science student who's trying to get a better understanding of the d flip-flop. My project assignment is to make a CMOS design of a positive edged d flip-flop using ff master slave and ...
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### Analog voltage signal threshold to latch output

I am an aerospace engineer by trade, but currently working on a little side project that involves some basic electronics now. So go easy on my ignorance ;) Here is a description of what I want to ...
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### Is it possible to create a logic gate design for a clocked D flip-flop register where there is a synchronous reset and an enable pin?

I'm currently designing a register where there needs to exist a data input pin (DIN), Clock (CLK), Reset (RST), and a RUN pin. The register is designed such that, only at positive edges of the clock ...