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Questions tagged [flipflop]

a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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Whats the truth table for this one?

What's the truth table for this, I can't get it right.
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What's the difference between a hardware register and a shift register?

There are two different wikipedia articles but they don't articulate the difference very clearly. Is the main difference that the shift registry uses a clock?
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24 views

Output Register and pipeline implementation

In his book "Finite State Machines in Hardware: Theory and Design (with VHDL and SystemVerilog)" the author said : 'The optional output register can be used to obtain a fully pipelined implementation ...
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Howto debug ngspice error PPerror: syntax error during transient analysis

In an effort to better understand software and how my computer actually works I have been experimenting with simple electronic circuits. I am working up to having three two bit registers (A, B, C) ...
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46 views

Why are latches level triggered and flip flops edge triggered?

I know what it means to be edge or level triggered but considering the block diagram or logic diagram of inside of latches and flip flops I cannot see what inside them specifies this property of each, ...
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Altera FlipFlop stuck at GND

I'm trying to make a counter that counts: 0,1,2,3,4,5 I need this for a frequency divider of 6 So I made this table: From this I get: J0= 1 K0= 1 J1 = NOT Q0 AND Q1 K1 = Q1 J2 = Q1 AND Q2 K2 =...
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40 views

flip flops RS(with NOR gates or NAND gates)

Being a total newbie, I have been reading about logic gates. I got some doubts about flip flops RS(with NOR gates or NAND gates). The flip flops are said to keep a previous state so: Why an AND gate ...
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How would I finish out this mini project (emitting 1 whenever 101 is read)?

Design a Moore finite state machine that detects 1 0 1 in consecutive digits in the input stream of 0's and 1's received every clock cycle. The circuit should output a 1 when it detects 1 0 1 ...
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66 views

Shift register using dff verilog

I want to create a shift register using d-flip-flop as basic structural element, code: dff: ...
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38 views

What happen to a dff(flip flop) without input?

I have this question but I don't know what happen to a dff without an input is it always 0 ?? like this picture below the 2nd dff hasn't any d ??? Also, if someone can draw the answer of the question ?...
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D Flip Flop Toggle — Q into Hex Inverter into D, Unstable Output, Help

simulate this circuit – Schematic created using CircuitLab I created the above circuit. There is essentially a switch that is normally high. I press a button. Using a NTE4049T hex inverter, ...
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monostable Eccles - Jordan multivibrator, theory

I’ve a few problems and questions to the principle of monostable multivibrator’s work. Basic schematic is as below: What is the reason for D1, C1, R3 elements at input? Why I can’t just tie a ...
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51 views

How to create a state transition table for a Mealy machine

I'm trying to design the counter shown in the diagram below with the counting sequence 123456 (i.e X1=1, X2=2, ...) as a Mealy machine. However, I'm having trouble figuring out how to create the ...
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How is asynchronous reset physically implemented in a flip-flop?

In Cliff Cumming's excellent paper on asynchronous vs synchronous resets, the following paragraph about the risk of metastability appears on page 19: Attention must be paid to the release of the ...
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445 views

Why ripple counter increments on each 8th pulse

I have connected the ripple counter CD4020 to an Atmega328, which sends a 50ms (low logic level) pulse to the CD4020's input each second and monitors all of its 12 outputs. However instead of ...
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2answers
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No Q bar on flip-flop

I'm currently using Quartus and I'm trying to make a 4 bit counter. I noticed that when I imported the built-in flip-flop that there is no Q bar output. It's the same issue with the JK flip-flop as ...
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1answer
32 views

Design a T flip flop and draw the asynchronous state diagram

I am supposed to design a T flip flop using logic gates (asynchronous sequential circuit) and also draw the state diagram. I don't really understand why the output doesn't change from 0 to 1 when ...
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What would an acceptable replacement be for a discontinued Motorola HCT174A?

I am trying to replace a Hex D Flip-Flop on an Amiga A4000 motherboard. The original chip has the label HCT174A XAA346 I believe the datasheet describing this ...
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I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?

A schematic by Lattice Semiconductor includes the diagrammed D flip-flop. This D flip/flop accepts, among others, a Set/Reset signal. I would have understood a Set signal. I would have understood a ...
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51 views

Question about SR latch timing

I have a question about how SR latches work: To my understanding the real-world implication is that one of the two gates will receive power first and produce an output signal, and they aren't going ...
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39 views

Difference between low signal and no signal for a SR latch?

I am struggling to understand how the SR latch works. When an input has designation 0, this means "low signal" correct? Is this completely different than "no signal"? Doesn't a logic gate need some ...
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1answer
80 views

JK Flip Flop Not Toggling in Logic.ly

This may be simply a logic.ly issue. I'm trying to simulate a JK flip-flop in logic.ly/demo using two AND gates and 2 NOR gates, but the simulation does not work when both inputs are high and the ...
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53 views

Implementing circuit with d-flipflop in verilog

I'm fairly new to Verilog and I'm currently trying to do a structural implementation of a circuit that consists of an d flipflop, it has inputs x and y, x and y are exclusive or'd and that result is ...
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48 views

Using 2 Data Flip Flops to create an up counter from 0 to 3 and repeats

I've done most of the legwork. I've got this design working using 2 set reset(SR) flip flops, but I need to make it using 2 data flips, a.k.a D flip flops. What I did: Note the numbers not in ...
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1answer
125 views

8-bit synchronous up/down counter [Logisim]

I am trying to create an 8-bit programmable up/down counter using D Flip flops. So far, this is what I have: The first 3 flip flops function correctly for both up and down, but the 4th doesn't. I ...
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44 views

Setup and Hold Time: A general method to find whether a block satisfies the constraints

How to determine whether setup and hold time constrains are satisfied in a digital block? I encountered a question on the same, and it would be really helpful to know a general way to determine the ...
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73 views

J K Flip Flop and Boolean Algebra

Y=K'J'Q+K'J+KJQ' The output Y should be that of a JK flip-flop. That is: Y=JQ'+K'Q I tried to solve the following way: 1. Y=K'J'Q+K'J+KJQ' 2. =K'(J'Q+J)+KJQ' 3. =JK'+K'Q+JKQ' 4. =J(K'+KQ')+...
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(Reasonably) accurate 1Hz clock generator

I would like your advice on components before I purchase anything. I am going to make a digital 24hr clock using probably JK flip flops/multiplexors with 7 segment displays. But it must be battery-...
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2answers
64 views

Weird circuit behavior at breadboard

I have no picture to show what my circuit is like, but I'll try to draw it and explain here as best as possible. The circuit contains a NE555 timer, working in the astable mode with a frequency of ...
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1answer
66 views

Digital Logic: What are “hamming code” and “Binary code” state machines?

I'm asked to draw the circuit for a state machine in one hot, hamming code and binary code models. I know what is one hot state machine, but i'm not sure what are the other 2. Google also didn't help. ...
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1answer
860 views

CMOS implementation of D flip-flop

I am trying to implement edge triggered flip-flop using CMOS logic. Google search provides following diagram on wikipedia: Upon simulating this using tanner, I find out that output resembles positive ...
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Make a double-tapping button (ideally without ICs or keeping ICs to a minimum) for a small “tiny cell” powered device

Conditions: small device, extremely space constrained (large caps are a no-go) Powered by a small battery (something like under 120 mah) Thus, adding a few more ICs like the 555 or "TimeBlox ...
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1answer
279 views

Identifying a component with only a partial part number

I have taken apart some circuitry that no longer works and I accidentally went a bit too far with the dremel. This means I've partially obscured the serial number of a component i'm wishing to ...
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1answer
51 views

Altera Cyclone IV clock-to-output delay

Trying to find what is the clock-to-output delay for registers inside EP4CE6E22C6. Have looked through the 3 Cyclone IV handbooks searching by delay but have not found any values specified. All the ...
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1answer
32 views

Why does the condition -(t_setup)<t_hold has to stand

I was given this inequality in logical circuits class and I can't figure out the reason behind it, and how can t_hold be negative. Is the condition relevant when t_hold is positive?
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1answer
196 views

How to make shift register logisim

How would i make a 4 bit shift register with d flip flops so that only 1 led is active at once. So for example if a button was pushed the first led would light up and the other 3 would be off. If the ...
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173 views

Asynchronous Active High SET & RESET D-FlipFlop

I have two pieces of modules as below, may I ask which one is the right verilog to represent an Asynchronous active high set/reset D-flip flop (Rising clock edge)? Are both of them logically ...
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1answer
68 views

voltage output and flip flop output

Shown below is the circuit I would like to implement. (the circuit is from this paper). Basically, it's a circuit designed to cut off voltage when electrochemical etching is done. The sudden drop in ...
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94 views

How many flip flops are required to build a digital circuit?

Here is an example: The periode of the this circuit is 9, and i want to build a digital circuit with only J-K flip flops. Here is my argument, I can tell there is nine different states that leads ...
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3answers
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what's the correct way to add counter inside flip-flop?

I want to count number of "clock enable" signal inside flip flop. I learn from tutorials that the output value should be assigned for all combinations of input. However I don't know how to add ...
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Can we apply state reduction to a state table having more than 1 input?

Consider the following state diagram: I assigned states as follows: a=00 b=01 c=10 d=11 But when I attempted to reduce the table, I realized that: Some present states do have the same next state ...
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Tricky Flipflop to State transition table

Question 1: what is the state transitiontable of given form: Question 2: the wiring between is relevant but what would happen if it was removed (in that case b would be connected with 0)? What would ...
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Xilinx(schematic) flip-flop D

I am working on a VGA drier. I have a problem using the flip-flop D. I tried to simulate only an flip-flop D and i don't get why it's output works like that. Shouldn't just delay the signal with 1 ...
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1answer
68 views

5mm RGB Led built in IC [closed]

Is there any standalone IC do the same job this 5mm Led (standalone flasher and builtin control IC) does?
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1answer
54 views

gates operation in flip flop [closed]

The operation of logic gates in the flip flop is pretty confusing for me. If I am not wrong then the NAND and NOR gates provide output only when there are at least two inputs. But in case of the flip ...
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2answers
436 views

Minimum Clock Period from setup and hold time

I found several different answers to how setup and hold-time of Flip-Flops influence the minimum time between two rising clock edges. tclock >= Propagation delay + tsetup + thold tclock >= ...
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How a Computer Represents a Number Electronically

I understand how computers represent decimal numbers using binary. I have yet to absorb this video on how computers add numbers, which looks helpful. Before understanding that though, I would like to ...
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How much can I draw from the output of a flip flop? [duplicate]

I have a simple question. I'm looking at using http://www.ti.com/lit/ds/symlink/cd4013b.pdf for my project and I need to be able to draw ~500ma from the 'Q' or '!Q' pin on the flipflop. How much ...
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3answers
260 views

Latching Soft ON/OFF Button

Would it be reasonable to implement a soft ON/OFF button like this? My design requirements in short: Enable the system power from a single-cell LiPo battery immediately after the ON/OFF button has ...
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2answers
102 views

Temperature and Voltage variation affects on Metastability

Are there any effects of temperature and voltage variations on Metastability of the flip-flop? If Yes, What are the effects?