Questions tagged [flipflop]
a flip-flop or latch is a circuit that has two stable states and can be used to store state information.
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What are the states of the flip-flops after one clock pulse?
It is given that Q0[MSB] and Q1[LSB] are both 0 initially and the circuit is edge triggered. The answer says this circuit will generate 2, but I am arriving at 3 and I can't see where I am going wrong....
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How to form a 8-Bit bidirectional shift register using two 4-bit bidirectional shift registers?
I really had some trouble with one design question in my homework (the deadline has passed). We were asked to design a 4-bit bidirectional shift register using D-Flip flops and after that to create a ...
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3answers
56 views
Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?
There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
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1answer
28 views
Two pulse to create one pulse circuit
I have two pulse quick outputting of an Op Amp at a particular voltage. What I am trying to do is have an output pulse to trigger at the first rising edge pulse and fall at the second rising edge ...
26
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4answers
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Why aren't resistors being used in this flip-flop used in static MOS RAM?
In the book, Digital Computer Electronics, there is a diagram on page 140 (figure 9-4 a) of a flip-flop used in static MOS RAM to store a bit. The book says that Q3 and Q4 act like resistors, which ...
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1answer
71 views
SPI slave: Store received byte?
SPI slave receives bit per bit (mosi) every clk and when a byte is completed (process A), this byte of data will be sent to the next process B (FlipFlop). If process B detects byte, process A starts a ...
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1answer
153 views
What is the triangle symbol in circuit diagrams?
What is the triagular symbols shown in the image, is it a buffer or some kind of delay?
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45 views
How to change flip-flop type using multiplexer
The idea is to create a D or T flip-flop from a JK flip-flop and a 2-entry multiplexer. If the selection line is 0, the flip flop should act as type D, and if it's 1 it should act as a type T.
a NAND ...
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3-Bit Up ASynchronous Counter Using JK Flip Flop
By using the excitation table for JK FF I was not able to get where the Values of JC KC came, specially the JC=X and KC=X states. I feel there are mistakes in the table for JC and KC column. Please ...
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1answer
60 views
sequential synchronous circuit
I'm learning about sequential synchronous circuits, and I was trying to do an exercise, but I'm not going as I expected.
The exercise is about
Elaborate the excitation equation of flip-flops;
Write ...
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50 views
How do I eliminate voltage spikes at edges of a pulse?
I am making a Negative edge triggered T flip flop using I2L.
Here is a photo of the circuit
Its working fine and the output waveform is correct, but there is an undesirable voltage spike at each ...
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1answer
95 views
is it posssible to make a 4-bit up/down asychronous counter using jk flip flops, xnor gates and nothing else?
the image below is supposed to represent the last segment of the circuit, where the 'updown' input would change the direction of the counting: when updown=0 it counts backwards (f,e,d,...1,0,f...) ...
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2answers
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What is this “flip-flop-like” circuit element from the Apollo Guidance Computer?
I've been trying to condense the pure NOR-gate based Apollo Guidance Computer schematics into a more higher level view of the logic elements and came across this interesting piece:
simulate this ...
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2answers
83 views
Power on state of D Type Flip Flop
I'm looking at the following two d-type flip flops to create a toggle for the EN pin on another IC.
I was going to feed Q back into D with an inverter such that it is toggled when clocked ( would this ...
0
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2answers
101 views
How do I make an edge triggered T flip flop using integrated injection logic (I2L)?
I have been searching everywhere online on how to make this circuit. I found out I can make NAND gates using I2L and connect them together to make a T flip flop , but this is very impractical since I ...
3
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2answers
167 views
Cascaded flip-flops and shift register timing
In the D-flip flop at the edge triggering of the clock, \$Q(t+1)=D\$.
In the figure below, shift-register using cascaded flip flops, why don't we assume that at clock edge triggering
\$Q_1(t+1)=D_1\$ ...
0
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1answer
45 views
Problem simulating 2-bit counter with OrCAD
I used OrCAD Capture to create a 2-bit counter using two D-type Flip-Flops (DFFs).
Here is the schematic:
My problem is that I get no output when I try to simulate it. I know for sure that V3, the ...
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0answers
55 views
IR reciever somewhow being triggered by cell phone screen?
First time asking a question here.
I am curious why the TSOP4838 ir sensor is acting eratically when my Google Pixel 2's screen is facing it.
As you can see from the schematic, I have a 555 arranged ...
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0answers
57 views
74HC5555 triggering
I want to use the 74HC5555 as a long period oscillator for which it seem suited. and I wish to use the internal oscillator (and divider) to determine the Q / not Q transition time of 28 days
The ...
0
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3answers
74 views
Usage of 555/556 Timer as a One shot timer
Im using two 555 timers / one 556 timer IC for a project. I've used it a couple of times before but never in monostable mode. Basically I need to activate a DC Motor in one direction for a set amount ...
10
votes
1answer
707 views
Falling edge detector sometimes doesn't work
I have a falling edge detector built based on a D flip-flop as shown in the following figure:
Components: 74hc74, 74ls04n, 74hc08
A sample output is shown below (I ...
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1answer
63 views
How to track down all the registers connected to a specific downstream register? (for set_max_delay's --from)
The Xilinx Vivado's set_max_delay requires -from to be set.
Basically I'd like to set max delay TO a register.
Because there can ...
0
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3answers
79 views
NL17SZ74 D-Flip Flop circuit doesn't work!
I've been having trouble with what should be a really simple Momentary-to-Latch D flip flop switch circuit.
Basically:
I want the momentary switch PUSH to set the CP (Clock Pulse) Pin Low and on ...
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1answer
48 views
Why can’t we use synchronous counters for high clk frequencies?
My professor said we can’t use synchronous counters for high clock frequencies. Is it because with many flipflops the delay becomes quite big and so the outputs change after the next triggering edge ...
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1answer
93 views
Anyone know how to hold a 74ls93? [closed]
I need to have a system where the 74ls93 holds and does not change until they are cleared. Does anyone know of a relatively simple way to do this?
Edit: Nevermind all, figured out how to do it by ...
0
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1answer
69 views
Will this circuit behave as I am expecting it to?
I'm an almost total newbie at electronics, but keen to learn more. As a first "serious" project, I wanted to build a device with 4 half-bytes of addressable NOR memory. As a first step to ...
1
vote
1answer
104 views
Why for setup check AND gates use rising edge, while OR gates use falling edge and vice versa for hold check in clock gating?
I have two questions on set_clock_gating_check SDC command.
Why for setup check, AND, NAND gates use rising edge, while OR, NOR gates use falling edge ?
Why for hold check, AND, NAND gate use ...
0
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0answers
42 views
N-Pulse Oscillator
I want to build a circuit which, each time a button is pressed, outputs 'N' pulses from an oscillator. I'm working on a solution which uses a flip-flop to control a switch at the output of the ...
0
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3answers
78 views
Difference between latches and flip flops in datasheet
At university and several online searches (Difference between latch and flip-flop) I have been taught that the difference between a latch and a flip flop is that the latch is level triggered while the ...
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0answers
48 views
Step a motor from a slow charging power source
I'd like to design a circuit that can power a stepper motor from a very weak power source such as a solar cel. Physics will of course make that a problem, but in my case I have no need to power the ...
0
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1answer
81 views
SRAM output voltage with 74HC chips
I am attempting to connect a CMOS parallel SRAM chip to a few different 74HC chips, but mostly 74HC377 octal flip-flops.
I'm having inconsistent results with values being loaded sometimes not being ...
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1answer
193 views
Unable to simulate a JK Flip-Flop using VHDL dataflow modelling
I want to write code and simulate waveforms for flip flops strictly using dataflow modelling. In this case I'm simulating a jk flip flop with only j,k and clock (no set , reset). It compiles fine, but ...
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0answers
20 views
DDR memory READ preamble and postamble
For Preamble detection and postamble closure for a memory interface controller , could anyone explain how the following Figure 4 , Figure 5 and Figure 6 work together to sample (or capture) the ...
0
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2answers
108 views
Creating a Delay Locked Loop (DLL) on an FPGA
I currently have a delay line using a series of flip-flops and buffers which precisely measures the time between rising edges of a start and stop signal. I would like to implement a delay locked loop (...
0
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1answer
90 views
Logism: Rising-Edge J-K flip-flop outputs 0 when J = 1 and K = 0 [closed]
According to the truth table of the J-K flip-flop:
When J = 1, K = 0, and CLK (Clock Signal) = 1, Q = 1.
FYI, the flip-flop is a Rising-Edge flip-flop. Below are the timing diagrams which show the ...
0
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3answers
270 views
JK Flip-Flop Counter: How to reset a counter?
I currently have a 3-bit asyncronous counter (built using J-K flip flops) that continuously counts up. However, I am struggling to figure out how to reset the counter to 0 when an input (Reset) is ...
0
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1answer
97 views
Data flip flop - I don't understand its purpose
The data flip flop can delay operation based on the time of the cycle of the clock.
If the clock's cycle is fast, the DFF is useless because it's like an instant change.
Is it possible to change the ...
0
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1answer
44 views
74HC377 Octal D flip-flops latching on falling edge of clock
What would cause a 74hc377 octal D flip-flops to occasionally latch on the falling edge of a clock?
I have several different 74hc chips across several breadboards. I was daisy chaining the breadboard'...
0
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1answer
55 views
74HC73 reset on released button
I want to use one button for set and reset. With a hex-inverter (because of falling edge), when I press the button, set works fine, but I need another button to reset the 74HC73.
Is there some ...
0
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0answers
42 views
Forwarding in RiscV multi cycle Pipeline
Any idea could be helpful
I have been trying for days to understand forwarding mechanism in RiscV but unfountly I keep failing, so I though about asking basic question to make sure I am building on ...
2
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2answers
152 views
Why do we need a flip-flop in this circuit?
Supposing I built some machine x3 that is capable of multiplying the input by 3. If I want to multiply some number with 3^3 then I should use 3 instances of the ...
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2answers
61 views
SR Flip Flop Latches
Which gate, NAND or NOR is a better choice for making SR Flip Flop latch? Please, provide the reason too.
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1answer
34 views
In SR latch when apply a pulse to reset latch how the Q is changed?
Here is the initial state of SR latch both reset and set inputs are zero.
Here we apply a pulse to the reset input and it shows it changes in this way
first -
and then -
The thing that I don't ...
8
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3answers
373 views
Analysis of two D flip-flop designs based on D latches
I am trying to create D flip-flops with D latches. Below are 2 possible ones. (Note that they are both rising-edge triggered.)
I tried to analyze their behaviors at the clock edges.
For D flip-flop 1,...
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1answer
76 views
Timing when clocking MCU off of A/D
I'd like to try interfacing a fast (80 MHz) ADC with a microcontroller system. The ADC (ADC12DL080) connects to a buffer flip flop (SN74LVTH162374) which then drives the MCU data pins about 6 cm away ...
0
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1answer
92 views
Master-slave JK flip flop (74HC73) doesn't toggle
I'm designing a traffic light using two BCD counters and a JK flip flop. The simulation works perfectly on Proteus, but not in hardware (PCB).
The traffic light is required to count from 40 to 0 in ...
0
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1answer
81 views
Output Jitter of jittery bitstream through flipflop
I have a bitstream of about 10-20 MHz coming out of an FPGA, that is obtained by Delta Sigma modulation. This bitstream is expectedly very jittery and can not be passed directly through an analog ...
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2answers
46 views
Compare output of logic gates but ignore their difference due to propagation delays
I am triggering a current source for a coil. I made a safety circuit with a bistable multivibrator, which forces the trigger sent to the hardware to have some maximum duration. This is a duty-cycle ...
7
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4answers
2k views
Why can't I make flip-flops in logic simulators?
I've been playing with a few logic simulators and don't understand why flip-flops are not working. I'm trying to implement a T flip-flop with NAND gates:
All the simulators I've tried give the same ...
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0answers
39 views
why the D-FF does not use the clock assigned by me Quartus schematic
The schematic given above is a simplified version of a design. But this is enough to explain my problem. As you can see from the schematic, clock signal of second dff is connected to (Q0' & clk). ...
