Questions tagged [flipflop]

a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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37 views

The same Minterm Twice in a sequental D flip flop

So my professor gave me a question that I have to search the answer for, it's a sequential D flip flop circuit with this sequence. I have searched far and wide and still don't understand how to solve ...
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What happens if clock cycle is replaced with constant high voltage in a processor?

Would the data in registers change at light speed and maybe become unstable/undefined, or would the processor stop changing state altogether? This post says: To give all the gates time to change ...
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To turn a ratioed circuit into non-ratioed circuit, what should be the transistor sizes for proper operation of this circuit?

The circuit is at the bottom. I know it is a ratioed circuit however, how can I convert it to a non-ratioed circuit without adding two more PMOS transistors between Vdd and the other PMOSs. Also, what ...
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What does this circuit do? (flip flop) [closed]

I am trying to understand a circuit which does two arithmetic operations of 5-bit words in 2 cycles: Q = 2*Q - A (one cycle) Q = 11*Q (two cycles) What does this part do? This is the whole circuit:
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Why am I not getting expected output in SR Flip flop LTSpice circuit?

simulate this circuit – Schematic created using CircuitLab I'm using Ltspice to design a synchronous SR flip flop circuit using NAND gate. When I run the simulator it is giving me same voltage ...
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SR Flip Flop not working

Disclosure: I’m using the iCircuit app to model the question below When I manually construct (in iCircuit, bottom half of image)the synchronous SR flip flop it works as expected. My expectation is ...
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Proteus JK Flip Flop - Gmin Stepping failed / Real Time Simulation fails to start

Apologies in advance as some googling indicates that this is probably a common error but other questions I've found are for more complicated circuits and I don't really understand the answer or how it ...
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2answers
95 views

How come two DFF can avoid metastability? [duplicate]

In my signal processing class, my professor said using TWO flip flop can avoid metastability. But he didn't explain it well. I wonder if anyone could enlighten me here? Thanks in advance!
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How enable for latch converts to clock in flip flop [duplicate]

Latch has enable signal and we cascade latches to make flip flops. How enable for latch converts to clock in flip flop. I mean how and why enable driven latches form edge triggered flip flops. Why ...
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Confused about positive edge-triggered D flip-flop

I'm reading the book Digital Design and Computer Architecture. I don't understand this passage: This is a D flip-flop with active low asynchronous set and reset inputs. If S' and R' are both 1, the ...
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How does this JK flipflop work?

Could someone explain to me how the impulse diagram of this circuit works? I don't understand the inputs in the JK flip flop. Why does J start with 1 ?
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Does this combinational lock circuit contain any memory?

Consider a simple lock circuit built using a 4-bit, active HIGH digital comparator. The first input is variable; it is the input that unlocks the lock. All the bits of the second input are tied to ...
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Understanding SAR ADC Control Logic

I am trying to understand how SAR control logic works before I use it in a design. I have read a few papers that design SAR ADCs but they don't go into detail on the control logic; they only show the ...
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1answer
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Flipflop's output voltages are 0V

I'm building a 4-bit asynchronous up counter with D flip-flops. Unfortunately the 4 output voltages are always 0V. Can someone please tell me why? I had already placed a digital source in front of the ...
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In LTspice XVII, 74HC107 has an error, but I can't figure out what the problem is

I made a circuit like this picture above with LTspice XVII. Q(0), Q(1), Q(2) are output, and CL is CLK (clock pulse). JKFFs are negative-edge-triggered JK flip-flop (ie. 74HC107). And, the graph of ...
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Trying to make a mod-10 counter with JK flip-flops in CircuitMaker but my outputs are always coming out HIGH instead of counting, not sure whats wrong

Trying to make a mod-10 counter with JK flip-flops in CircuitMaker but my outputs are always coming out HIGH instead of counting, not sure whats wrong
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I designed neg. edge-triggered jk flip-flop circuit in LTspice XVII. But, it doesn't work

Voltage sources work but, 74HC107(neg. edge-triggered jk flip-flop) doesn't work. Output Q(0), Q(1), Q(2) turn out always 0V. I can't understand what is the problem..... Please help me...... And, ...
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DFLOP LTspice inputs and outputs

I want to use the symbolic form of following DFLOP in the schematic. but I don't know which pin refers to which indicator(n001, n002, ...). for a better understanding of my question, I attached an ...
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1answer
94 views

How to make this T-flip-flop circuit

I am trying to make a T-flip-flop circuit with a relay, which would: toggle on a button press (12 V) [default state: off] allow control from an external micro-controller (optocouplers) allow ...
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1answer
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Hold time constraint equation

I am trying to understand the equation for hold time in the Digital Design and Computer Architecture book: https://www.sciencedirect.com/topics/computer-science/hold-time-constraint Hold time ...
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2answers
91 views

Digital logic/sequential circuit to produce one pulse for every 5 clock pulses

I'm working on a problem where I'm trying to design a digital logic circuit (sequential circuit?) to produce output Y given input A: So the goal is to produce one pulse for every 5 input pulses. What ...
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2answers
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Impedance of JK flip flops [closed]

Lets assume we get a square wave signal output from an astable multivibrator. Can we connect the output as input of the clock signal in order to create a digital counter with some specific frequency ...
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3answers
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How does an SR-latch actually work?

In case of a NOR SR-latch, if we make S = 0 and R = 0, then output Q = 1 and nQ = 0. I also know one important rule which is if we put high input in the set line (S = 1) then output Q goes high. If S =...
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1answer
206 views

I have a JK flip-flop circuit that works in simulation, but not with real components on a solderless breadboard

I'm building a control mechanism for a seat heater in my car. Eventually, it will drive power relays to control the current to the heating elements. It works in a simulation on simulator.io, but it ...
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Standart Retiming circuit with two D type Flip Flops

I am trying to build a button(for adjusting the clock) syncroniser circuit for a seven segment clock. The button signals are of course async inputs so there needs to be retiming to make sure it goes ...
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Flipping Flip-Flop Terminology [closed]

On 1 October 2021, NXP released version 7 of its I2C protocol, in part, to comply with its inclusive language policy where master/slave have been replaced with controller/target: Updated the terms &...
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What kind of flops does state retention synthesis take?

I have designed my own standard cell library using some commercial process technology. I am trying to synthesize a large design that is implemented as a retimed module whose latency is controlled by ...
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51 views

flip flop counter design

I need to design a counter count from 0-9 using a 4 bit counter(JK,T,SR and D flip flop). I know the concept of using an excitation table, draw the K-map for each input. But for this case, since this ...
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Circuitry with bistable Flip-Flop

I am trying to build a logic in hardware where a pulse will define the state of two output lines. I believe it should be possible to build this with two or three bistable flipflops. There would be 3 ...
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1answer
79 views

Flip Flop frequency divider by 17

I have a task to make frequency divider by 12, 17, 30. I have figured out how to make divider by 12 using staging dividers by 6 and staging dividers by 10. But 17 is odd number and i can't make it ...
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Why does a 4-bit asynchronous counter need exactly 4 flip-flops?

We can get the same result (counting from 0000 to 1111) by removing the last flip-flop (Q3 output) and taking clock line as one of the inputs (i.e Q0 will be from clk itself and rest 3 outputs from 3 ...
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Finding setup time of a flip-flop

First I'll write the definition I know for things Im gonna mention in my question. Given a flip-flip, a setup time is the amount of time the synchronous input must show up and be stable, before the ...
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Is "transition time" the same as "contamination delay"? If not, what is equivalent to \$t_{cd}\$ in the datasheets?

In the CD4013B datasheet the following timing table (excluding clock related values) can be found: According to the answer to this question, the contamination delay would be the minimum propagation ...
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1answer
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How to adjust the frequency of the generated PWM signal from a TL494?

From the datasheet of TL494 IC, I have found that the frequency of the generated PWM signal for single ended mode is (f=1/(R×C)). From the following figure, the frequency is constant to 10kHz or 10 us ...
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Positive edge-triggered JK flip-flop circuit

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1answer
135 views

How do I develop a discrete SR latch into a simple shift register?

I trying to develop a discrete SR flip-flop into a serial in parallel out (SIPO) shift register, say 2 bits for the sake of learning. I don't have a clue how to proceed. For the SR latch, I suppose I ...
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4answers
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How to set the initial conditions of an astable multivibrator

Consider the following oscillator circuit: I have this running and oscillating at about the frequency I want. However, when first powering it on, one of two things happen: Both LEDs momentarily ...
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Metastability in 3 or 2 flop synchronizer if input is valid for at least 2 clocks

In this image: Figure 1: metastability in 2 or 3 flop synchronizer If the metastability of first flop doesn't get resolved in 4th clock, is it possible that it may get resolved to '0' in 5th clock? ...
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Shared rising edge detector? [closed]

Why do we have a rising edge detector in every flip flop of a register. Can't we just make a shared one for all the flip flops in order to save hardware?
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1answer
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Ballpark energy consumption per state transition for a D-flipflop in a modern chip manufacturing process?

For a D-flip-flop in a modern yet-not-too-extravagant chip manufacturing process (let's say 28nm or 40nm), what are some ballpark figures for the energy cost per switching H->L or L->H one can ...
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Is it possible to use the RTC alarm signal on the tamper pin in order to hold that value in a D flip flop? STM32 (bluepill)

I've been doing a lot of research concerning Low power modes for the STM32 (Bluepill) and I was wondering if I could power my board through VDD and then, right after going into sleep mode, I would use ...
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For an RS flip flop, what if S=1, R=0, and Q =0, Q bar =1? Is it legal or not? Why?

Assuming we are using NOR gates to build the RS flip flop. After reading so much material on RS flip and flop circuit, I understand that: When S=1, R=0, Q=1, and Q bar=0, for the next clock cycle, Q'=...
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Won't this jk flip flop circuit be facing a race condition?

Below is the question and answer for my assignment but I don't really understand why it shows the output as below: I am confused here. Shouldn't the circuit for flip-flop A which is connected to flip-...
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1answer
155 views

Custom D Flip Flop in Logisim Simulation Error

I am building a custom D flip flop in Logisim as a part of the project for my computer organization course and I am not allowed to use the built-in flip flops. When I designed this flip flop ...
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What is the correct way to code asynchronous debounced input signals for a Moore Finite States Machine in VHDL?

What is the correct way to code, in VHDL, asynchronous debounced input signals of a Moore Finite States Machine that needs to be implemented on an FPGA? The Moore machine models a machine that has two ...
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Building edge triggered D flip flop from BJTs

I am trying to make a low speed D flip-flop (positive edge triggered) with idea to save D input state into 100n capacitor, lock it, wait few ms and finally write state to output bistable circuit. It ...
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1answer
64 views

Synchronized reset signal on asynchronous input - D flip flop

For a D flip flop with an asynchronous reset, what is the behavior if the reset input signal is synchronized with the input clock? This is what I'm picturing: If the CLR signal is just a divided ...
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2answers
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VHDL -- K-map reduced characteristic equation fails

I have this circuit (D-latch): and I can directly write the logical equation by only watching the gates: $$ Q = \overline{(\overline{(D \cdot C) + Q}) + (C \cdot \overline{D})} $$ If I want to ...
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2answers
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What are the states of the flip-flops after one clock pulse?

It is given that Q0[MSB] and Q1[LSB] are both 0 initially and the circuit is edge triggered. The answer says this circuit will generate 2, but I am arriving at 3 and I can't see where I am going wrong....
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How to form a 8-Bit bidirectional shift register using two 4-bit bidirectional shift registers?

I really had some trouble with one design question in my homework (the deadline has passed). We were asked to design a 4-bit bidirectional shift register using D-Flip flops and after that to create a ...

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