Questions tagged [flipflop]

a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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Functionality of the circuit

I made the timing diagram for this circuit, but i am not sure if it is correct. Please confirm my timing diagram and what is the functionality of this circuit? Is it to generate a pulse 5 clock cycles?...
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DRAM inspired edge-triggered D-type flip-flop

I was thinking about using DRAM cells as edge-triggered D-type flip-flop, I put the elements in falstad circuit simulator and it worked, but I am not sure on how would this translate to an actual ...
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What is the purpose of a master-slave flip-flop?

Why is having a 2 stage flip-flop desirable? Are there advantages of having a master-slave compared to a one stage JK flip flop?
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Calculate the next state for flip flop sequential circuit

Based on my previous question, i managed to draw out the truth table Inputs for flipflops sequential circruits ...
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Inputs for flipflops sequential circruits

Not very sure if these inputs are correct before i draw my truth table. Too many lines and i am confused. JA = QB = KA = B KA = B DB = D' TC = 0
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Clock frequency divider circuit (divide by 2) using D flip flop

I was trying to implement frequency divider by 2 using D flip flop with the logic connection of ~Q to D input. I provide 2x clock frequency of 50% Duty cycle in the hardware where D flip flop is made ...
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4-bit memory serial to parallel memory register circuit question

I am building a 4-bit serial to parallel memory register and I feel like so far I have gotten things right, but I'm unsure of where to connect the CLR connections. Could someone have a look at my ...
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Design this memory with D Flip-Flops

Design the following memory with D Flip-Flops. (you can use other gates or decoder if needed) The following memory has 4 one-bit locations and can access 2 locations in each moment and read from ...
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351 views

How to create a state transition table for a Mealy machine

I'm trying to design the counter shown in the diagram below with the counting sequence 123456 (i.e X1=1, X2=2, ...) as a Mealy machine. However, I'm having trouble figuring out how to create the ...
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Prevent long press in changing state on D Flip-Flop

I've made a circuit on Logisim that allows me to switch between three LEDs at the push of a button. Essentially allowing me to cycle between OFF, LED1, LED2 and LED3 repeatedly. I'm doing this using ...
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262 views

Is there a way that only change one of result of d-flip flop?

I drow the ring counter schematic,but the last two flip flop simulation signal didn't "shift". My D-flip flop is designed as set=1,then Q=0; reset=1,then Q=1; set=1=reset,then Q=1,when D=1 occur at ...
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How to trigger a buzzer on a specific time?

Basically, what you are seeing right now is a circuit counter timer in Multisim. I'm using multiple JK Flip-flop here. I'm still confused on how to trigger the buzzer when it counts to 10 minutes (...
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What will happen if I initially set J=K=Clk=1 in this circuit?

Will it remain in the state \$Q = Q-bar = 0\$ as the feedback given back will always be zero? Will this lock the JK in this state as long as the \$V_cc\$ is connected? Note: I have used the word ...
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Why is there no race around condition in NOR SR latch when S=R=0(initially)?

When the IC gets connected to the Vcc+, both the NOR gates get the input 0 and 0 (low) which yields the output 1. Now since both the outputs are again connected as one of the input to each of the NOR ...
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63 views

What's wrong with my timing diagram?

I have made this simple timing diagram that presents the triggering way of D flip flop. The flip flop is triggered by clock's rising edges. I am convinced that the diagram is correct signal-wise. ...
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Can I make a latch using 2 AND gates, instead of NAND gates?

I have seen that, generally, a simple latch is made using either 2 NAND gates or 2 NOR gates. Can I make a latch using 2 AND gates ?
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How to simulate flip flop noise

Or is flip flop noisy at all? would you simluate its noise as you would do with a strong arm comparator? Why is strong arm comparator noisy but not a flip flop?
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136 views

Turning switch state at two different voltage

I have a requirement to change the transistor/mosfet switch state at two different voltages. Below is a small graphical representation. 3.3 v (red) to 4.5 (green). switch should be open when the ...
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Register File for MIPS Processor

I am writing code for Register file (32 registers, each of 32 bit) for MIPS Single Cycle processor. I want writing to happen at the negative edge of the clock. As usual, reading can happen any time (...
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How to modify D-FF Setup/Hold Times using Verilog?

I am new to Verilog. I need to find a way to modify setup/hold-time and clock to output delay timing parameters. Why I need this is to simulate a problem that changes the timing parameters with some ...
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Understanding complements on inputs

I've got a problem understanding formal writing down of complements on inputs. During my laboratory exercise I was working with a device that had D flip flop embedded in it. The goal was to ...
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Initial value for 32 bit register made using D F/F in verilog

I am trying to make a 32-bit register using 32 negative edge trigerred D F/F. Here is the verilog code for D F/F: ...
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How do you make a digital counter circuit which counts to 10 minutes and 15 minutes, it will give a signs buzzer? [duplicate]

I asked in this site before, but apperantly I don't quite understand. I want to make a digital counter circuit which it counts to 15 minutes for my big project in my campus . When the circuit counts ...
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Clock domain crossing of a bus between related clocks

Imagine I want to transfer a bus from a fast clock (i.e., 100MHz) to a slower clock (50MHz). The clocks are related (come from the same MMCM, phase aligned). The Xilinx Timing Closure User Guide ...
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103 views

Preset and Clear in SR Flip Flop

In Practical Electronics for Inventors, Paul states the following as the pulse triggered SR flip flop: Of course there are some minor issues in the truth table. (One of the \$Q\$’s must be \$\...
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Which is better latches or flip flop

I was reading about flip flops where author is convincing that it's better to use flip flop than latches. He gave following reason for it. As seen from the block diagram of Fig. 5.2. a sequential ...
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What is the meaning of JK flip flop's J and K ?

In D flip flop, D means DATA. In SR flip flop S means SET and R means RESET. What is the meaning of JK flip flop's J and K ?
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High frequency clock from clocked RS latch

We were taught that this circuit is not of much use as when CLK=1, J=1 & K=1, Q toggles at a very high rate. So suppose I want to make a high-frequency clock, can I use this? Of course, the ...
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8-bit synchronous up/down counter [Logisim]

I am trying to create an 8-bit programmable up/down counter using D Flip flops. So far, this is what I have: The first 3 flip flops function correctly for both up and down, but the 4th doesn't. I ...
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Dual edge detector

I am designing a hobby project that will run on a battery so I am trying to reduce power consumption. The SoC I am using has the ability to go into a deep sleep mode where it consumes very little ...
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4 bit synchronous binary counter using T flip-flops

I'm trying to make a 4 bit synchronous counter using T FF. I managed to draw the excitation table and evaluated the functions but I'm unsure what the pin configurations will be. I tried connecting the ...
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Stable state and don't care

I have a latch but I can't understand what are the meaning of Un/Stable state and ...
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Asynchronous Active High SET & RESET D-FlipFlop

I have two pieces of modules as below, may I ask which one is the right verilog to represent an Asynchronous active high set/reset D-flip flop (Rising clock edge)? Are both of them logically ...
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D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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Expected output of DFF_2 if DFF_1 has hold violation

I am trying to figure out the output of flop DFF_2 when If DFF_1 has hold violation. My answer - DFF_2(Q) = X If DFF_2 has hold violation. My answer - DFF_2(Q) = X I understand the FF's go to meta-...
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Design a T flip flop and draw the asynchronous state diagram

I am supposed to design a T flip flop using logic gates (asynchronous sequential circuit) and also draw the state diagram. I don't really understand why the output doesn't change from 0 to 1 when ...
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282 views

Design Counter With Arbitrary Sequence Using Load

I'm trying to design an asynchronous counter with JK flip- flops, with an arbitrary sequence. The sequence is: 0, 1, 2, 3, 4, 5, 2 ? I know how to solve this kind of problems, but in this case how ...
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Asynchronous Down Counter using D Flip Flops

After fixing my Up Counter, I'm having troubles writing structural verilog code for an Asynchronous 4-bit Down Counter using D Flip Flops. Here's the D Flip Flop code (which was tested and works): <...
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Flip flop asynchronous reset timing

Let's say you unassert an asynchronous reset signal to a flip flop after you need to to meet setup timing but before the positive edge of the clock. You're in trouble right? Now let's say you've got ...
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How can i make my mod 10 up/down counter wrap from 0 to 9 when counting down?

I know there is something wrong with my reset logic because when counting down it starts from 5 and changes if i have any wires connected to the reset of the flip flops. I don't know how to fix this ...
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Building a D flip-flop with two D inputs using 3 S-R latches

"Use three clocked SR latches to build a D flip-flop with two D inputs (D1 and D2 ) and two clock inputs C1 and C2 . Clock C1 takes data D1 and clock C2 takes data D2 ." Any hints how to start?
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Purpose of the logic gate configurations on the Kenbak-1

I was just looking through the schematics of the Kenbak-1 computer (long story), and I found this: simulate this circuit – Schematic created using CircuitLab I hurt my brain a little bit ...
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Why do we clock Flip Flops?

I am trying to understand Flip Flops & Latches. I am reading from Digital Logic book by Morris Mano. One thing I am not able to understand is why we clock flip-flops? I understand why we need '...
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How to determine the flip-flops input in truth table

I've only one simple problem about JK flip-flops. The last columns in the following table (Flip-flop inputs). How were they genereted from the other parts on the left? Does this has a relationship ...
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When can the output of any flip flop (e.g., JK FF) be indeterminate?

I came across following problem: In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in A. Q = 0, Q' = 1 B. Q = 1, Q' = 0 C. Q = ...
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How is the Truth Table of Positive edge triggered D Flip-Flop constructed?

simulate this circuit – Schematic created using CircuitLab Consider this diagram which represents a positive edge triggered D Flip-Flop. In the analysis of this circuit, my book (Morris Mano) ...
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D Flip-Flops at MCU IOs

I found below PCB from a machine. It has a MCU for control all inputs and outputs and MCU inputs and outputs go through HCT374 IC to optocouplers that isolate all inputs and outputs. What is the ...
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Confusion regarding PRESET and not(PRESET)

After watching the video explanation (https://www.youtube.com/watch?v=mXoQ4WAQ0qk) regarding PRESET and CLEAR . I have made following conclusions . Considering Active Low / bubbled case as shown ...
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Suspicious diagrams depicting PGT of D flip flop

I encountered a designing problem in digital system: Add the necessary logic circuitry to accommodate the transfer of data from memory into the A register.The data values from memory are to enter the ...