Questions tagged [flipflop]
a flip-flop or latch is a circuit that has two stable states and can be used to store state information.
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How is the Truth Table of Positive edge triggered D Flip-Flop constructed?
simulate this circuit – Schematic created using CircuitLab
Consider this diagram which represents a positive edge triggered D Flip-Flop. In the analysis of this circuit, my book (Morris Mano) ...
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Telling which way a KY-040 Rotary Encoder has been turned
I am stripping this problem down to the bare minimum.
I have KY-040 Rotary Encode,
When it is turned clockwise I want a blue LED to blink for every increment it is turned.
When it is turned anti ...
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2answers
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VHDL JK Flip-Flop with logic gates
I am trying to make a JK flip-flop in ActiveHDL environment.
I want to make it with logic gates.
It should look like this:
This is my code:
...
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1answer
106 views
Preset and Clear in SR Flip Flop
In Practical Electronics for Inventors, Paul states the following as the pulse triggered SR flip flop:
Of course there are some minor issues in the truth table. (One of the \$Q\$’s must be \$\...
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Which of these is the correct circuit for JK flip-flop
Are both of these correct ? I am seeing both of these in different places
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Design a T flip flop and draw the asynchronous state diagram
I am supposed to design a T flip flop using logic gates (asynchronous sequential circuit) and also draw the state diagram. I don't really understand why the output doesn't change from 0 to 1 when ...
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Make a double-tapping button (ideally without ICs or keeping ICs to a minimum) for a small “tiny cell” powered device
Conditions:
small device, extremely space constrained (large caps are a no-go)
Powered by a small battery (something like under 120 mah)
Thus, adding a few more ICs like the 555 or "TimeBlox ...
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3answers
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what's the correct way to add counter inside flip-flop?
I want to count number of "clock enable" signal inside flip flop.
I learn from tutorials that the output value should be assigned for all combinations of input.
However I don't know how to add ...
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134 views
Turning on and off an output with just one button and a FlipFlop
I am trying to make a circuit with the following characteristics: If I press the switch once and then immediately release the circuit activates the output and leaves it activated. If I press it again ...
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1answer
124 views
Suspicious diagrams depicting PGT of D flip flop
I encountered a designing problem in digital system:
Add the necessary logic circuitry to accommodate the
transfer of data from memory into the A register.The data values from
memory are to enter the ...
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0answers
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Is this a ring counter ? What is its definition?
We can know the ring counter like :0000 -> 1000 -> 0100 -> 0010 -> 0001,it shifts the "1" bit.
Here is my schematic,the same as the schematic from the internet,and because my d-flip flop is active ...
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1answer
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Ripple counter, reset problem (J-K flip flop counter)
I am trying to simulate a decade counter using a ripple counter 4 bits and a NAND gate to reset the 4 J-K flip-flops when it reaches 10 (1010).
The thing is it does not reset but goes to 4 (0100) due ...
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Fibonacci LFSR - polynomial , sequence, phase shift
Hi, it's my first post here. I have a question according this picture. So let's see.
IMHO the primitive polynomial for that LFSR will be \$x^4+x+1\$ but I'm not sure if I'm thinking good. I've read ...
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Functionality of the circuit
I made the timing diagram for this circuit, but i am not sure if it is correct.
Please confirm my timing diagram and what is the functionality of this circuit?
Is it to generate a pulse 5 clock cycles?...
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DRAM inspired edge-triggered D-type flip-flop
I was thinking about using DRAM cells as edge-triggered D-type flip-flop, I put the elements in falstad circuit simulator and it worked, but I am not sure on how would this translate to an actual ...
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4-bit memory serial to parallel memory register circuit question
I am building a 4-bit serial to parallel memory register and I feel like so far I have gotten things right, but I'm unsure of where to connect the CLR connections.
Could someone have a look at my ...
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Design this memory with D Flip-Flops
Design the following memory with D Flip-Flops. (you can use other gates or decoder if needed)
The following memory has 4 one-bit locations and can access 2 locations in each moment and read from ...
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How to trigger a buzzer on a specific time?
Basically, what you are seeing right now is a circuit counter timer in Multisim. I'm using multiple JK Flip-flop here. I'm still confused on how to trigger the buzzer when it counts to 10 minutes (...
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How to simulate flip flop noise
Or is flip flop noisy at all? would you simluate its noise as you would do with a strong arm comparator?
Why is strong arm comparator noisy but not a flip flop?
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1answer
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How to modify D-FF Setup/Hold Times using Verilog?
I am new to Verilog. I need to find a way to modify setup/hold-time and clock to output delay timing parameters. Why I need this is to simulate a problem that changes the timing parameters with some ...
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Understanding complements on inputs
I've got a problem understanding formal writing down of complements on inputs.
During my laboratory exercise I was working with a device that had D flip flop embedded in it. The goal was to ...
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27 views
4 bit synchronous binary counter using T flip-flops
I'm trying to make a 4 bit synchronous counter using T FF. I managed to draw the excitation table and evaluated the functions but I'm unsure what the pin configurations will be. I tried connecting the ...
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Clap switch working on 220 Volts AC
I have made this clap switch.It is working fine presently. I need suggestions for improvement for its long term use.
Specifically I want to know if the capacitor based power supply is okay in this ...
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1answer
78 views
Different implementations of JK flip flop
I know following variants of SR flip flop:
Using NAND-NAND combination
Using AND-NOR combination
I was guessing how we can obtain JK flip flop for each of these variants. I found below approach ...
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1answer
47 views
Different variations of SR latch
Wikipedia gives following circuits of flip flops:
SR latch using NORs
SR latch using NANDs
Note that circuit 1 have R input at top and S below it.
Also note that circuit 2 have active LOW inputs, ...
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1answer
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Forming synchronous SR flip flop from asynchronous SR flip flop
Wikipedia gives following circuits of flip flops:
SR latch using NORs
SR latch using NANDs
Clocked SR latch using NORs:
Clocked SR latch using NANDs:
I understand how circuit 3 is obtained from ...
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45 views
Obtaining D flip-flop mosfet-level schematics from CMOS layout
Could anyone help to derive D flip-flop mosfet-level schematics from the following CMOS layout described in this conference document : Open Cell Library in 15nm FreePDK Technology ?
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45 views
Design a synchronous sequential circuit
I can't figure out how to do this exercise: (sorry for my bad english)
Design a synchronous sequential network according to the Mealy model with an input and an output which must assume the value 1 ...
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Do Clocked/Edge triggered flip-flops have same truth table regardless of whether they are derived from NAND Latch or NOR Latch?
While going through my Basic Electronics textbook, I noticed that NAND Latch gives Q=0 for S=1 & R=0 and Q=1 for S=0 & R=1. N0R Latch gives Q=0 for S=0 & R=1 and Q=1 for S=1 & R=0. ...
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D flip-flop sequencer to light three LEDs up sequentially together and then turn them all off
This circuit should turn on three lights sequentially whenever there is a high logic level until all are lit and then turn them all off, restarting the cycle.
It seems the following sequencing ...
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42 views
Deriving state table /equation confused
A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output z. The flip- flop input equations and circuit output equation are
JA = BX+B'Y' KA = B'xy'
JB = A'x KB = A +...
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CMOS IC Dynamic Edge-Triggered Flip Flop setup and hold time calculation
Before explaining i should point out that i refer to changes of signals in the text as a reference change on which i will calculate these times as 50% change of one signal to 50% change of the other ...
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Flipflop value a long time after startup
After power up in an ASIC, is it save to assume that all flipflops are in a stable state ('0' or '1')? I do not care in which stable state they are, but it is crucial that all metastability has ...
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Home brew CPU register trouble shooting
update
Apparently I’m an idiot. It took me this long (hours) to check the supply voltage of the flip flops, which was at .25 volts from a bad connection. Rookie mistake. Hard lesson learnt.
In the ...
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Creating coder of MFM linear code (Miller) using logic gates
I have a problem with the implementation of my MFM encoder using logic gates (in the CEDAR program). It's not working correctly, and I don't know if this is software problem, or if I'm doing something ...
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Analysis of Sequential Circuits - Derive the state Equations from the Diagram
How can I derive boolean expression for this diagram?
This is my answer:
D0 = Cnt ⊕ Z D1 = ZCnt' + ZQ'Cnt + ZCntQ'
For D1, I don't know what will be the expression if the input came from ...
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1answer
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How to convert asynchronous set FlipFlop Hard macro into asynchronous reset FlipFlop?
My query is, if there is a asynchronous set flop in a library but the implementation or RTL required a asynchronous reset flop, how to achieve this?
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IC 555 as monostable multivibrator
How is the output of a monostable multivibrator affected if the trigger pin is kept at a negative voltage (0V)?
The upper voltage reference comparator will change its output to logic 1, while the ...
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1answer
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monostable Eccles - Jordan multivibrator, theory
I’ve a few problems and questions to the principle of monostable multivibrator’s work. Basic schematic is as below:
What is the reason for D1, C1, R3 elements at input? Why I can’t just tie a ...
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1answer
365 views
How to create a state transition table for a Mealy machine
I'm trying to design the counter shown in the diagram below with the counting sequence 123456 (i.e X1=1, X2=2, ...) as a Mealy machine.
However, I'm having trouble figuring out how to create the ...
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1answer
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Question about SR latch timing
I have a question about how SR latches work:
To my understanding the real-world implication is that one of the two gates will receive power first and produce an output signal, and they aren't going ...
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1answer
62 views
Using 2 Data Flip Flops to create an up counter from 0 to 3 and repeats
I've done most of the legwork. I've got this design working using 2 set reset(SR) flip flops, but I need to make it using 2 data flips, a.k.a D flip flops.
What I did:
Note the numbers not in ...
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1answer
521 views
8-bit synchronous up/down counter [Logisim]
I am trying to create an 8-bit programmable up/down counter using D Flip flops. So far, this is what I have:
The first 3 flip flops function correctly for both up and down, but the 4th doesn't. I ...
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2answers
712 views
Asynchronous Active High SET & RESET D-FlipFlop
I have two pieces of modules as below, may I ask which one is the right verilog to represent an Asynchronous active high set/reset D-flip flop (Rising clock edge)? Are both of them logically ...
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Design a 3-Bit Up Synchronous Counter Using JK Flip Flop (odd vs even numbers)
I have to design 3-Bit Up Synchronous Counter Using JK Flip Flop counters.
The first one should count even numbers: 0-2-4-6-0
The second one should count odd ...
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Clear D flip flop internal logical scheme
I am new in this community and also in logic circuit design and digital electronics. I couldn't find the logical design on the internet for the following D flip flop and i would like to know how it's ...
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1answer
770 views
D FLIP FLOP Cadence
Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments.
But when I tried to take the output from CLKPULSE, ...
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1answer
53 views
Async counter that counts up to 10
I am trying to make a counter that counts up to 10. I have used 4 flip flops and I added an AND port so that when the counter reaches 10 it goes back to 0. The problem is that after 10 it goes ...
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Design asynchrous mod 6 counter using JK flip flop - where those equations come from
I have this exercise "Design mod 6 counter using JK flip flop that uses below table of truth."
My professor solved it at one of his lectures but I don't understand fully where those equations come ...
