Questions tagged [flipflop]

a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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Toggle Flip-Flop for Voltage Higher than Logic Levels

I need a T flip-flop for 24V. The purpose is to take a 24V 50% duty cycle 0.5Hz pulse wave and halve its frequency to 0.25Hz, so that the output wave toggles between 0 and 24V at the input's rising ...
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How does the loopback on a non-retriggerable monostable work?

I understand how to connect a monstable multivibrator to be in the non-retriggerable mode. Just loopback the /Q to the falling edge input or the Q to the rising edge output) as in the following ...
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What's causing a master-slave JK flip flop to get 'stuck'?

I've built a JK master-slave flip flop according to the following schematic: Putting it into Logicly I have the following diagram: However, regardless of which switches I change, the final two NOR ...
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Preset and Clear in SR Flip Flop

In Practical Electronics for Inventors, Paul states the following as the pulse triggered SR flip flop: Of course there are some minor issues in the truth table. (One of the \$Q\$’s must be \$\...
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How is the Truth Table of Positive edge triggered D Flip-Flop constructed?

simulate this circuit – Schematic created using CircuitLab Consider this diagram which represents a positive edge triggered D Flip-Flop. In the analysis of this circuit, my book (Morris Mano) ...
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How do the D flip-flops in SAR logic work?

D flip-flops with set and reset can only work when set = 1 = reset, and the Q value depends on D and clock, but in the SAR logic circuit shown below, we find set and reset aren't equal to 1 at the ...
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VHDL JK Flip-Flop with logic gates

I am trying to make a JK flip-flop in ActiveHDL environment. I want to make it with logic gates. It should look like this: This is my code: ...
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T flip flop from NAND gates

I recently was interested in whether a T flip flop could easily be made from NAND gates. A google search did reveal lots of examples that basically all look like an RS flip flop with two additional ...
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The same Minterm Twice in a sequental D flip flop

So my professor gave me a question that I have to search the answer for, it's a sequential D flip flop circuit with this sequence. I have searched far and wide and still don't understand how to solve ...
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How to make this T-flip-flop circuit

I am trying to make a T-flip-flop circuit with a relay, which would: toggle on a button press (12 V) [default state: off] allow control from an external micro-controller (optocouplers) allow ...
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Ballpark energy consumption per state transition for a D-flipflop in a modern chip manufacturing process?

For a D-flip-flop in a modern yet-not-too-extravagant chip manufacturing process (let's say 28nm or 40nm), what are some ballpark figures for the energy cost per switching H->L or L->H one can ...
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IR reciever somewhow being triggered by cell phone screen?

First time asking a question here. I am curious why the TSOP4838 ir sensor is acting eratically when my Google Pixel 2's screen is facing it. As you can see from the schematic, I have a 555 arranged ...
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Usage of 555/556 Timer as a One shot timer

Im using two 555 timers / one 556 timer IC for a project. I've used it a couple of times before but never in monostable mode. Basically I need to activate a DC Motor in one direction for a set amount ...
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Why can’t we use synchronous counters for high clk frequencies?

My professor said we can’t use synchronous counters for high clock frequencies. Is it because with many flipflops the delay becomes quite big and so the outputs change after the next triggering edge ...
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7474 flip-flop- D simulation

I'm trying to use a D flip-flop 7474 for my project. When I tried to simulate it, this warning appears (see picture.) My parameters for input clock are: OFFTIME = 0.1S ONTIME = 0.1S DELAY = 0 ...
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Recover correct value from unstable memory through read operation

We are given a memory with 32-bit width for each word. it has the length (N - number of rows) which is not relevant for the question. we know that the memory has a problem where at any row, one bit ...
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Is this D Flip Flop positive edge triggered or negative edge triggered?

It is an edge triggered D flip flop where X is input, Y is clock, Q is output. Is this D Flip Flop positive edge triggered or negative edge triggered? ADD (copied from a comment): Actually I am trying ...
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How to implement a negative edge triggered D-flipflop using using level triggered D-flipflops?

Say here's a negative edge triggered D-flipflop with its timing diagram with random binary signal. And on the other hand, here's a level triggered one: How do I implement the negative edge triggered ...
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One-way JK flip-flop using 74xx109

I want to design a flip flop circuit that effectively has one input and one output, as well as a reset trigger, along with clock and power, using a 74ACT109 JK flip flop. Basically, the output and ...
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Devices storing volatile memory

I've hit a bit of a rut in a question on my homework for my computer architecture class (MIPS architecture): what are digital logic devices that can implement 1 bit and 32 bit volatile memory, and ...
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Design this memory with D Flip-Flops

Design the following memory with D Flip-Flops. (you can use other gates or decoder if needed) The following memory has 4 one-bit locations and can access 2 locations in each moment and read from ...
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Which of these is the correct circuit for JK flip-flop

Are both of these correct ? I am seeing both of these in different places
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How to create a state transition table for a Mealy machine

I'm trying to design the counter shown in the diagram below with the counting sequence 123456 (i.e X1=1, X2=2, ...) as a Mealy machine. However, I'm having trouble figuring out how to create the ...
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Make a double-tapping button (ideally without ICs or keeping ICs to a minimum) for a small "tiny cell" powered device

Conditions: small device, extremely space constrained (large caps are a no-go) Powered by a small battery (something like under 120 mah) Thus, adding a few more ICs like the 555 or "TimeBlox ...
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Turning on and off an output with just one button and a FlipFlop

I am trying to make a circuit with the following characteristics: If I press the switch once and then immediately release the circuit activates the output and leaves it activated. If I press it again ...
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Is this a ring counter ? What is its definition?

We can know the ring counter like :0000 -> 1000 -> 0100 -> 0010 -> 0001,it shifts the "1" bit. Here is my schematic,the same as the schematic from the internet,and because my d-flip flop is active ...
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Fibonacci LFSR - polynomial , sequence, phase shift

Hi, it's my first post here. I have a question according this picture. So let's see. IMHO the primitive polynomial for that LFSR will be \$x^4+x+1\$ but I'm not sure if I'm thinking good. I've read ...
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Logisim - Initializing a state on a counter

Full context: I am building a stopwatch / countdown timer. The design is that there will be up/down counters that increment/decrement the time. The counters are then connected to 7-segment displays to ...
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How to design, build and test synchronous sequential circuits using T-Flip Flops?

I want to Use T flip-flops to design the circuit specified by the state diagram of following figure. Zi represents the output of the circuit. This is my school project. I did everything. But I cannot ...
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How to create 4-bit asynchronous counter?

I am new to Multimedia Logic and am trying to create a 4-bit asynchronous counter. I did something like this, but it doesn't work. I'm not sure if everything is properly connected and if I was using a ...
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Advice on SIPO FIFO clock, as well as 555 timer usage

I've made a circuit which involves me entering inputs, and the result being displayed in a seven segment LED. The LED must flash on and off and display the input number at least two times in two ...
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PIC16 Configurable Logic Cell (CLC) - toggle signal

I have a 1Hz square signal (in_1) and a 1/16Hz pulse (in_2) as inputs of a PIC16F1778. The rising edges of the two signals are synchronous as shown in the picture: I want to use the configurable ...
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Flip Flop not flopping

Haven't used a flip flop since week 2 of uni (well over 20 years ago now) but had a requirement for one in a current project. I need an output that toggles after a button press. Seems like a flip flop ...
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Why does the propagation delay need to be greater than the hold time when you have two D-FFs connected like this?

In the above circuit, why does the propagation time Tp > Th? As I understand it, once the first D-FF changes value, it will propagate that value to its output, ...
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Synchronizing a clock enable signal with an input clock

I'm designing a basic PCB for testing equipment in lab. The goal is to take a clock input, a clock enable (from a PC indicating that the measurement is beginning), and then distribute it to a number ...
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To turn a ratioed circuit into non-ratioed circuit, what should be the transistor sizes for proper operation of this circuit?

The circuit is at the bottom. I know it is a ratioed circuit however, how can I convert it to a non-ratioed circuit without adding two more PMOS transistors between Vdd and the other PMOSs. Also, what ...
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Trying to make a mod-10 counter with JK flip-flops in CircuitMaker but my outputs are always coming out HIGH instead of counting, not sure whats wrong

Trying to make a mod-10 counter with JK flip-flops in CircuitMaker but my outputs are always coming out HIGH instead of counting, not sure whats wrong
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I designed neg. edge-triggered jk flip-flop circuit in LTspice XVII. But, it doesn't work

Voltage sources work but, 74HC107(neg. edge-triggered jk flip-flop) doesn't work. Output Q(0), Q(1), Q(2) turn out always 0V. I can't understand what is the problem..... Please help me...... And, ...
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2 answers
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Digital logic/sequential circuit to produce one pulse for every 5 clock pulses

I'm working on a problem where I'm trying to design a digital logic circuit (sequential circuit?) to produce output Y given input A: So the goal is to produce one pulse for every 5 input pulses. What ...
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Standart Retiming circuit with two D type Flip Flops

I am trying to build a button(for adjusting the clock) syncroniser circuit for a seven segment clock. The button signals are of course async inputs so there needs to be retiming to make sure it goes ...
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What kind of flops does state retention synthesis take?

I have designed my own standard cell library using some commercial process technology. I am trying to synthesize a large design that is implemented as a retimed module whose latency is controlled by ...
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flip flop counter design

I need to design a counter count from 0-9 using a 4 bit counter(JK,T,SR and D flip flop). I know the concept of using an excitation table, draw the K-map for each input. But for this case, since this ...
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Circuitry with bistable Flip-Flop

I am trying to build a logic in hardware where a pulse will define the state of two output lines. I believe it should be possible to build this with two or three bistable flipflops. There would be 3 ...
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How to adjust the frequency of the generated PWM signal from a TL494?

From the datasheet of TL494 IC, I have found that the frequency of the generated PWM signal for single ended mode is (f=1/(R×C)). From the following figure, the frequency is constant to 10kHz or 10 us ...
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Is it possible to use the RTC alarm signal on the tamper pin in order to hold that value in a D flip flop? STM32 (bluepill)

I've been doing a lot of research concerning Low power modes for the STM32 (Bluepill) and I was wondering if I could power my board through VDD and then, right after going into sleep mode, I would use ...
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Building edge triggered D flip flop from BJTs

I am trying to make a low speed D flip-flop (positive edge triggered) with idea to save D input state into 100n capacitor, lock it, wait few ms and finally write state to output bistable circuit. It ...
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How to form a 8-Bit bidirectional shift register using two 4-bit bidirectional shift registers?

I really had some trouble with one design question in my homework (the deadline has passed). We were asked to design a 4-bit bidirectional shift register using D-Flip flops and after that to create a ...
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Two pulse to create one pulse circuit

I have two pulse quick outputting of an Op Amp at a particular voltage. What I am trying to do is have an output pulse to trigger at the first rising edge pulse and fall at the second rising edge ...
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74HC5555 triggering

I want to use the 74HC5555 as a long period oscillator for which it seem suited. and I wish to use the internal oscillator (and divider) to determine the Q / not Q transition time of 28 days The ...
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N-Pulse Oscillator

I want to build a circuit which, each time a button is pressed, outputs 'N' pulses from an oscillator. I'm working on a solution which uses a flip-flop to control a switch at the output of the ...
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