Questions tagged [flipflop]
a flip-flop or latch is a circuit that has two stable states and can be used to store state information.
725
questions
51
votes
9answers
243k views
Difference between latch and flip-flop?
What is the difference between a latch and a flip-flop?
What I am thinking is that a latch is equivalent to a flip-flop since it is used to store bits and is also equivalent to a register which is ...
29
votes
8answers
5k views
Why is the output of stateful elements often named Q?
In logic circuit diagrams, I've seen various conventions for naming inputs and outputs of logic gates and combinatorial circuits. However, stateful elements like latches and flip-flops often have ...
25
votes
6answers
7k views
What is a flip flop?
There seem to be a number of different definitions of flip-flops and latches out there, some of which are contradictory.
The Computer Science text book for the course I teach is probably the most ...
20
votes
4answers
10k views
When is using latches better than flip-flops in an FPGA that supports both?
The Question:
When is using latches better than flip-flops in an FPGA that supports both?
Background:
It is a well-known principle that level-sensitive transparent latches should be avoided in ...
19
votes
5answers
33k views
Why do we clock Flip Flops?
I am trying to understand Flip Flops & Latches. I am reading from Digital Logic book by Morris Mano. One thing I am not able to understand is why we clock flip-flops?
I understand why we need '...
18
votes
2answers
40k views
What is the meaning of JK flip flop's J and K ?
In D flip flop, D means DATA. In SR flip flop S means SET and R means RESET. What is the meaning of JK flip flop's J and K ?
17
votes
9answers
46k views
Make a momentary switch control a toggle
What are the simplest, cheapest, smallest ways to make a momentary switch produce a 2-state toggling output (latching momentary switch)?
In other words, the output is continuously low, and when you ...
15
votes
6answers
3k views
Why do cascading D-Flip Flops prevent metastability?
I understand what metastability is but don't understand how linking together flip flops reduces this?
If the output of the first flipflop is metastable, this gets used as input for the second one. ...
14
votes
5answers
24k views
How to understand the SR Latch
I can't wrap my head around how the SR Latch works. Seemingly, you plug an input line from R, and another from S, and you are supposed to get results in Q and Q′.
However, both R and S require input ...
13
votes
4answers
5k views
What is the beginning state for Q in a SR latch?
In this diagram
what would be the beginning state for Q? Since the first NOR for S and R rely on previous results, there must be something for the first iteration?
NOTE:
I'm in a first year ...
11
votes
4answers
5k views
What does it mean to “gate the clock”?
In my lecture notes I keep reading "do not gate the clock". I tried searching on the Internet, but I'm unable to find the exact meaning of this phrase.
10
votes
3answers
25k views
Why is S=1, R=1 state forbidden in RS flip flop?
I have come across the RS flip flop & I have tried implementing that on a simulator & using actual logic gates. But I'm still not sure whether I have correctly understood the unstable or the ...
9
votes
5answers
2k views
Setup and hold time output when violated
Consider a positive edge triggered D flip flop with input signal X with a setup time of 20 ns and a hold time of 0 ns. What will be the output?
C is clock signal with a period of 40 ns....
9
votes
4answers
56k views
SR Flip-Flop: NOR or NAND?
I started studying flip-flops recently and I am stuck at this point:
At some video tutorials, people explain the SR flip-flop like this:
So they use NAND gates, producing a transition table like ...
8
votes
2answers
2k views
SR Latch (Flip Flop) beginning Inputs?
Ok this is probably a basic question, but I understand how SR latches work except one thing.
In the R input and S input you can make them 0 or 1.....but what about the input lines next to them (That ...
8
votes
6answers
2k views
Can someone explain the following flip-flop circuit?
I'm having trouble understand what's going on in this circuit. The question asks "what is the value of Q if \$\bar{R} = 1\$ and \$\bar{S} = 0\$" (as shown).
In this case, how can I determine what Q ...
8
votes
3answers
1k views
How is this CD4013 application supposed to work?
I'm trying to troubleshoot an issue in a synthesizer I have, an early 80s synthesizer from Roland called RS-09. I'm just starting to study logic and am perplexed by what's going on. In this ...
8
votes
2answers
1k views
Why do we need to synchronise asynchronous inputs in FSM?
I have been newly learning digital electronics. I know that there are gates which perform logic functions, I learned about RS-Latch, D-Latch and Master-Slave-D-Flip-Flop. Now that I can perform logic ...
8
votes
5answers
97k views
What is race condition in flip-flops?
I've gone through two of my text books and consulted my teacher but nothing seems to clarify my doubts.
The two versions of race which I've been taught are -
When the S and R inputs of an SR ...
8
votes
1answer
28k views
What are carry-lookahead adders and ripple-carry adders?
I see carry-lookahead adders and ripple-carry adders terms being used often. I have no idea what either means (nor the type of architecture they describe).
Can someone please explain what each one is,...
7
votes
3answers
21k views
What is hold time violation?
I am currently reading about Pulsed Latch Circuit. And there is a frequent mention of "hold time violation". Like:
For latch, "...data must be held for a longer period of time,
increasing the ...
7
votes
3answers
8k views
What is wrong with my D flip-flop toggle switch?
Until a few weeks ago, I had never drawn a circuit diagram in my life, so bear with me. I am currently trying to design (in Logisim) a circuit that acts like a toggle switch, using only basic logic ...
7
votes
1answer
3k views
Understanding Flip Flops
I am trying to better understand how flip flops work. I am asked:
Desing a three-bit up/down counter using T-ff. It should include a
control input called Up(bar)/Down. If Up(bar)/down = 0, then ...
7
votes
2answers
19k views
How 1-bit was stored in Flip flop?
A flip flop is a sequential circuit and it stores a 1-bit value,
but it is designed using only basic, universal gates and a feedback circuit. How then is it able to store or handle a 1-bit value?
I ...
7
votes
1answer
2k views
Turning a microcontroller on with a flip flop
I'm working on debugging a circuit that I've built and am trying to wrap my head around an issue.
I have the following circuit (74LCV is an inverting flip flop and the NCP1400 is a boost converter):
...
7
votes
1answer
907 views
How do I design a clocked synchronous state machine for a combinational lock?
I need help in completing a task, I’m stuck on quite a few things. Since I’m very new to this topic on finite machines.
I’ve attempted the state diagram, state table, transition table, K-map values ...
6
votes
3answers
1k views
Detect the first rising edge of 3 input signals
I have 3 input signals which are pulse waveforms The output is switch to high once once all 3 first rising edges of 3 inputs are detected.
Is there a digital circuit from logic gates, flip flop that ...
6
votes
2answers
3k views
why in some circuit there is use of bubble followed by bar?
It is a circuit of ring counter. The clock here is negative triggered. but for set and clear it use bubble with bar.What is the need of bubble followed by bar. why it can not use a PRE and CLR (...
6
votes
3answers
6k views
What is the purpose of a master-slave flip-flop?
Why is having a 2 stage flip-flop desirable? Are there advantages of having a master-slave compared to a one stage JK flip flop?
6
votes
4answers
13k views
When should I use SR, D, JK, or T Flip flops?
In class I've learned about SR, D, JK, and T flip flops. From what I understand, you can construct any design by using any of them. So my question is when making a design, how does one choose which to ...
6
votes
2answers
984 views
Do the logic gate inputs of 74HCXX integrated circuits exhibit a high impedance?
Do the inputs of the 74HC374-SMD D-type flip flop have high impedance inputs? In datasheet is stated that it has buffered inputs, I assume that means high impedance, right?
In other words, do I have ...
6
votes
4answers
20k views
Rising edge pulse detector from logic gates
The circuits I describe are entirely made of 7400 series logic gates (7402, 7404 and 7408 ic).
I'm trying to build a rising (positive) edge pulse detector using logic gates.
The following circuit ...
6
votes
2answers
2k views
Cross-coupled logic gates and timing
I had a hard time getting a right title for this question since I'm a software guy trying to get the basics of my hardware down. Since all computers basically start with logic gates and go from there ...
6
votes
2answers
753 views
sequential circuits; clocked SR flip-flop
I'm learning about sequential logic and am wondering about the behavior of a clocked SR flip-flop.
If R=S=0, then the AND gates evaluate to 0. In that case, and if the recurrent inputs to the NOR ...
6
votes
1answer
511 views
Latches and Two Phase Clocking in modern ASICs
Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
6
votes
3answers
3k views
Clocked edge-triggered timing (contamination delay)
I'm reading a book about computer architecture, and it says that, in clocked edge-triggered devices, the contamination delay is usually nonzero, and that the contamination delay for registers is ...
6
votes
4answers
37k views
What is the difference between registers, flip flops and latches?
I want the answer to the very basic level. I know what they mean individually, but what I am looking for is connection between them.
5
votes
4answers
2k views
Are D-latches and D-type flipflops volatile?
If there is a power cut to the CPU, will be registers clear or keep their memory?
5
votes
3answers
1k views
I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?
A schematic by Lattice Semiconductor includes the diagrammed D flip-flop. This D flip/flop accepts, among others, a Set/Reset signal.
I would have understood a Set signal. I would have understood a ...
5
votes
2answers
4k views
Slow clock edge causing issues with D flip flop behavior
I'm trying to use a D flip flop and a pushbutton as a simple switch. My goal is this: every time I press the button, the output of the FF will switch state.
I put a circuit together in a simulator ...
5
votes
3answers
746 views
State Machine with D Flip Flops; how to deal with race conditions
Consider a state machine whose entire state is kept in a collection of edge-triggered D flip-flops. The outputs of these are fed into a combinatorial network which fully determines the next state, and ...
5
votes
2answers
2k views
master-slave flip-flops
im having some trouble finding an example of the time-instability that motivates the flip-flop. wherever i look, the explanations are awfully airy-fairy (or at least my understanding is). for example, ...
5
votes
4answers
3k views
What actually happens when both 1 input is given in RS flip flop circuit (physical change)?
This question is somewhat similar to:
Why is S=1, R=1 state forbidden in RS flip flop?
But I am asking what actually happens if both 1 input is given forcefully in R and S terminal of flip flop ...
5
votes
4answers
2k views
Knight Rider design using Flip Flops
I need to find this for a homework as an introduction to designing with flip flops. It must use only JK, D, T or SR flip flops. All the designs I find, are made with transistors or capacitors, and ...
5
votes
4answers
191 views
Clock Dividers with Clock Domain Crossing
I am doing a design in FPGA that looks like this:
100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with ...
5
votes
2answers
823 views
Metastability error propagation with flip flop
I do have a confusion regarding the metastability resolution using flip flops , I know that I should add synchronizer of two or three d-flip flop to guarantee a safe transmission at clock domain ...
4
votes
3answers
1k views
Where does the power supply go in an SR Latch?
I understand how an SR Latch works: is S is 1, it will set Q to 1. If R is 1 it will set Q to 0.
If both S and R are 0, the value of Q should remain unchanged (right?). So the circuit has these ...
4
votes
4answers
11k views
In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?
In a binary counter design using 4 J-K flip-flops, that counts from 0 to 9, the flip flops are reset when the output from the 2nd flip flop NAND the 4th flipflop equals to 0. Since binary 9 is 1001, ...
4
votes
3answers
508 views
The intuition behind RS flip-flop
I'm struggling to wrap my mind behind the concept of RS flip-flop. For me, the diagram seems very non-intuitive.
Whenever I accept, for example, that Q is HIGH and follow signal route (is it even ...
4
votes
3answers
241 views
Using just one output of a J-K flip-flop
If I am using a J-K flip-flop, but only need one of the outputs, what should I do with the other?
Leave it disconnected, or tie it high/low (via a resistor?) Why?
