Questions tagged [flipflop]

a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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Difference between latch and flip-flop?

What is the difference between a latch and a flip-flop? What I am thinking is that a latch is equivalent to a flip-flop since it is used to store bits and is also equivalent to a register which is ...
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32 votes
8 answers
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Why is the output of stateful elements often named Q?

In logic circuit diagrams, I've seen various conventions for naming inputs and outputs of logic gates and combinatorial circuits. However, stateful elements like latches and flip-flops often have ...
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4 answers
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Why aren't resistors being used in this flip-flop used in static MOS RAM?

In the book, Digital Computer Electronics, there is a diagram on page 140 (figure 9-4 a) of a flip-flop used in static MOS RAM to store a bit. The book says that Q3 and Q4 act like resistors, which ...
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27 votes
6 answers
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What is a flip flop?

There seem to be a number of different definitions of flip-flops and latches out there, some of which are contradictory. The Computer Science text book for the course I teach is probably the most ...
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24 votes
4 answers
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When is using latches better than flip-flops in an FPGA that supports both?

The Question: When is using latches better than flip-flops in an FPGA that supports both? Background: It is a well-known principle that level-sensitive transparent latches should be avoided in ...
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21 votes
5 answers
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Why do we clock Flip Flops?

I am trying to understand Flip Flops & Latches. I am reading from Digital Logic book by Morris Mano. One thing I am not able to understand is why we clock flip-flops? I understand why we need '...
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  • 595
19 votes
9 answers
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Make a momentary switch control a toggle

What are the simplest, cheapest, smallest ways to make a momentary switch produce a 2-state toggling output (latching momentary switch)? In other words, the output is continuously low, and when you ...
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19 votes
1 answer
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What is the meaning of JK flip flop's J and K?

In D flip flop, D means DATA. In SR flip flop, S means SET and R means RESET. What is the meaning of JK flip flop's J and K?
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16 votes
6 answers
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Why do cascading D-Flip Flops prevent metastability?

I understand what metastability is but don't understand how linking together flip flops reduces this? If the output of the first flipflop is metastable, this gets used as input for the second one. ...
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15 votes
4 answers
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What is the beginning state for Q in a SR latch?

In this diagram what would be the beginning state for Q? Since the first NOR for S and R rely on previous results, there must be something for the first iteration? NOTE: I'm in a first year ...
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5 answers
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How to understand the SR Latch

I can't wrap my head around how the SR Latch works. Seemingly, you plug an input line from R, and another from S, and you are supposed to get results in Q and Q′. However, both R and S require input ...
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13 votes
4 answers
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What does it mean to "gate the clock"?

In my lecture notes I keep reading "do not gate the clock". I tried searching on the Internet, but I'm unable to find the exact meaning of this phrase.
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12 votes
5 answers
69k views

SR Flip-Flop: NOR or NAND?

I started studying flip-flops recently and I am stuck at this point: At some video tutorials, people explain the SR flip-flop like this: So they use NAND gates, producing a transition table like this:...
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3 answers
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Why is S=1, R=1 state forbidden in RS flip flop?

I have come across the RS flip flop & I have tried implementing that on a simulator & using actual logic gates. But I'm still not sure whether I have correctly understood the unstable or the ...
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12 votes
2 answers
1k views

What is this "flip-flop-like" circuit element from the Apollo Guidance Computer?

I've been trying to condense the pure NOR-gate based Apollo Guidance Computer schematics into a more higher level view of the logic elements and came across this interesting piece: simulate this ...
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10 votes
5 answers
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Setup and hold time output when violated

Consider a positive edge triggered D flip flop with input signal X with a setup time of 20 ns and a hold time of 0 ns. What will be the output? C is clock signal with a period of 40 ns....
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2 answers
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How does electricty flow in a flip-flop circuit? I can't understand how memory bits work with NAND gates

Consider: simulate this circuit – Schematic created using CircuitLab The i bit is what we want to store, and the s bit is ...
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10 votes
3 answers
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What does the D stand for in "D Flip-Flop"?

I'm rather interested in the history of eletrical engineering, and I've seen some discussion here and there about the origin of the names of the various flip flop circuits. Some time ago I took part ...
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10 votes
1 answer
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Falling edge detector sometimes doesn't work

I have a falling edge detector built based on a D flip-flop as shown in the following figure: Components: 74hc74, 74ls04n, 74hc08 A sample output is shown below (I ...
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2 answers
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SR Latch (Flip Flop) beginning Inputs?

Ok this is probably a basic question, but I understand how SR latches work except one thing. In the R input and S input you can make them 0 or 1.....but what about the input lines next to them (That ...
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10 votes
6 answers
115k views

What is race condition in flip-flops?

I've gone through two of my text books and consulted my teacher but nothing seems to clarify my doubts. The two versions of race which I've been taught are - When the S and R inputs of an SR ...
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9 votes
3 answers
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How is the Q and Q' determined the first time in JK flip flop?

My background is in Computer Science, and this is my first time posting in electronics SE. This is a circuit diagram of JK flip flop. I don't understand how it works at the beginning, when the ...
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  • 91
9 votes
6 answers
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Rising edge pulse detector from logic gates

The circuits I describe are entirely made of 7400 series logic gates (7402, 7404 and 7408 ic). I'm trying to build a rising (positive) edge pulse detector using logic gates. The following circuit ...
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9 votes
3 answers
438 views

Analysis of two D flip-flop designs based on D latches

I am trying to create D flip-flops with D latches. Below are 2 possible ones. (Note that they are both rising-edge triggered.) I tried to analyze their behaviors at the clock edges. For D flip-flop 1,...
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8 votes
4 answers
3k views

Why can't I make flip-flops in logic simulators?

I've been playing with a few logic simulators and don't understand why flip-flops are not working. I'm trying to implement a T flip-flop with NAND gates: All the simulators I've tried give the same ...
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  • 191
8 votes
3 answers
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What is the purpose of a master-slave flip-flop?

Why is having a 2 stage flip-flop desirable? Are there advantages of having a master-slave compared to a one stage JK flip flop?
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8 votes
6 answers
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Can someone explain the following flip-flop circuit?

I'm having trouble understand what's going on in this circuit. The question asks "what is the value of Q if \$\bar{R} = 1\$ and \$\bar{S} = 0\$" (as shown). In this case, how can I determine what Q ...
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8 votes
3 answers
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How is this CD4013 application supposed to work?

I'm trying to troubleshoot an issue in a synthesizer I have, an early 80s synthesizer from Roland called RS-09. I'm just starting to study logic and am perplexed by what's going on. In this ...
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8 votes
2 answers
2k views

Why do we need to synchronise asynchronous inputs in FSM?

I have been newly learning digital electronics. I know that there are gates which perform logic functions, I learned about RS-Latch, D-Latch and Master-Slave-D-Flip-Flop. Now that I can perform logic ...
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8 votes
1 answer
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What are carry-lookahead adders and ripple-carry adders?

I see carry-lookahead adders and ripple-carry adders terms being used often. I have no idea what either means (nor the type of architecture they describe). Can someone please explain what each one is,...
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7 votes
3 answers
25k views

What is hold time violation?

I am currently reading about Pulsed Latch Circuit. And there is a frequent mention of "hold time violation". Like: For latch, "...data must be held for a longer period of time, increasing the ...
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7 votes
4 answers
15k views

When should I use SR, D, JK, or T Flip flops?

In class I've learned about SR, D, JK, and T flip flops. From what I understand, you can construct any design by using any of them. So my question is when making a design, how does one choose which to ...
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7 votes
3 answers
9k views

What is wrong with my D flip-flop toggle switch?

Until a few weeks ago, I had never drawn a circuit diagram in my life, so bear with me. I am currently trying to design (in Logisim) a circuit that acts like a toggle switch, using only basic logic ...
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7 votes
1 answer
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Understanding Flip Flops

I am trying to better understand how flip flops work. I am asked: Desing a three-bit up/down counter using T-ff. It should include a control input called Up(bar)/Down. If Up(bar)/down = 0, then ...
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7 votes
2 answers
25k views

How 1-bit was stored in Flip flop?

A flip flop is a sequential circuit and it stores a 1-bit value, but it is designed using only basic, universal gates and a feedback circuit. How then is it able to store or handle a 1-bit value? I ...
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7 votes
3 answers
3k views

Clocked edge-triggered timing (contamination delay)

I'm reading a book about computer architecture, and it says that, in clocked edge-triggered devices, the contamination delay is usually nonzero, and that the contamination delay for registers is ...
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7 votes
5 answers
49k views

What is the difference between registers, flip flops and latches?

I want the answer to the very basic level. I know what they mean individually, but what I am looking for is connection between them.
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7 votes
1 answer
2k views

Turning a microcontroller on with a flip flop

I'm working on debugging a circuit that I've built and am trying to wrap my head around an issue. I have the following circuit (74LCV is an inverting flip flop and the NCP1400 is a boost converter): ...
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7 votes
1 answer
1k views

How do I design a clocked synchronous state machine for a combinational lock?

I need help in completing a task, I’m stuck on quite a few things. Since I’m very new to this topic on finite machines. I’ve attempted the state diagram, state table, transition table, K-map values ...
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6 votes
3 answers
2k views

Detect the first rising edge of 3 input signals

I have 3 input signals which are pulse waveforms The output is switch to high once once all 3 first rising edges of 3 inputs are detected. Is there a digital circuit from logic gates, flip flop that ...
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6 votes
2 answers
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why in some circuit there is use of bubble followed by bar?

It is a circuit of ring counter. The clock here is negative triggered. but for set and clear it use bubble with bar.What is the need of bubble followed by bar. why it can not use a PRE and CLR (...
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6 votes
4 answers
6k views

What actually happens when both 1 input is given in RS flip flop circuit (physical change)?

This question is somewhat similar to: Why is S=1, R=1 state forbidden in RS flip flop? But I am asking what actually happens if both 1 input is given forcefully in R and S terminal of flip flop ...
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6 votes
2 answers
1k views

Do the logic gate inputs of 74HCXX integrated circuits exhibit a high impedance?

Do the inputs of the 74HC374-SMD D-type flip flop have high impedance inputs? In datasheet is stated that it has buffered inputs, I assume that means high impedance, right? In other words, do I have ...
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  • 544
6 votes
2 answers
3k views

Cross-coupled logic gates and timing

I had a hard time getting a right title for this question since I'm a software guy trying to get the basics of my hardware down. Since all computers basically start with logic gates and go from there ...
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  • 163
6 votes
2 answers
875 views

sequential circuits; clocked SR flip-flop

I'm learning about sequential logic and am wondering about the behavior of a clocked SR flip-flop. If R=S=0, then the AND gates evaluate to 0. In that case, and if the recurrent inputs to the NOR ...
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6 votes
2 answers
2k views

master-slave flip-flops

im having some trouble finding an example of the time-instability that motivates the flip-flop. wherever i look, the explanations are awfully airy-fairy (or at least my understanding is). for example, ...
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  • 163
6 votes
1 answer
785 views

Latches and Two Phase Clocking in modern ASICs

Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
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5 votes
5 answers
3k views

What happens if clock cycle is replaced with constant high voltage in a processor?

Would the data in registers change at light speed and maybe become unstable/undefined, or would the processor stop changing state altogether? This post says: To give all the gates time to change ...
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5 votes
3 answers
2k views

Where does the power supply go in an SR Latch?

I understand how an SR Latch works: is S is 1, it will set Q to 1. If R is 1 it will set Q to 0. If both S and R are 0, the value of Q should remain unchanged (right?). So the circuit has these ...
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5 votes
5 answers
466 views

Why are flip flops criss crossed

I want to simulate how a computer works using logic gates, now I am trying to build out the memory aspect of it. After looking at various articles and books I see a lot of them using flip-flops/...
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