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Questions tagged [fpga]

A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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How to program aliexpress Xilink X-SP6-X9 FPGA? [on hold]

I am new to the world of FPGA's. I just bough a Xilink X-SP6-X9 (Spartan 6) board on aliexpress but I don't know how to program it. I got this one: https://aliexpress.com/item/32665068263.html?spm=...
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where can I find list of all Xilinx (FPGA) abbreviations

I am learning FPGA and study some Xilinx documents. My main problem is that Xilinx uses a lot of abbreviations which I have no idea what they mean. For example, DCI (Digitally Controlled Impedance), ...
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37 views

Why doesn't my Ethernet controller work? [on hold]

these are my verilog project. I want to develop a Ethernet Controller by FPGA. My FPGA built-in RTL8201CP(100Mbps, Full duplex) and 25Mhz E_TXC clock input FPGA(4-wire * 25MHz = 100Mbps). But my ...
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2answers
54 views

Fusing electronic platforms into one IC board

I have an insane goal whose possibilities id like to discuss. To start with I am interested in three different electronics platform for edge computing: Edge computer: Like Raspberry pi or Intel ...
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22 views

How to constraint clock on the GPIO of FPGA

I want to implement the JTAG protocol with Verilog HDL in FPGA. The TMS and TCK signals are all connected to the GPIO pins of FPGA, not to the dedicated clock pin. TCK's rising edge is almost aligned ...
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33 views

How does one change Vivado IP signal types?

The Xilinx IP block called Utility Buffer allows the designer to convert one single-ended signal to a differential signal pair (among other things). However, the block expects the input and output ...
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1answer
50 views

which interface to use TBI, GMII or MII? (FPGA)

I am working with the SoC FPGA Smartfusion2 M2S010-MKR-KIT. It is intended to exchange some data between the SoC and the PC. For that reason, I aim to use Ethernet. As far as I understood, in order ...
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30 views

FPGA Timing Constraint for 2 Combinational paths to take the same time

I am trying to do a simple asynchronous FPGA design where I have 2 inputs and 2 outputs, and assign the outputs to the inputs. I need the delay of both assign's to be near identical. What timing ...
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3answers
2k views

VHDL: Why is it hard to design a floating point unit in hardware? [closed]

Floating point calculation basically involves representing units in a scientific notation and then deciding how many bits to devote to the manitssa and exponent. Therefore, all calculations involving ...
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1answer
89 views

Why doesn't my verilog state machine toggle state?

I have written a state machine in Verilog. However, when I try to simulate it with my testbench, it does not advance from the STATUS_IDLE state to the STATUS_READY state. Why isn't the state machine ...
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1answer
42 views

How do I interpret the setup/hold time on this RMII interface?

I'm coding the FPGA (MAC) side of an RMII interface between an Altera FPGA and LAN8720 device. Page 72 of the datsheet (pdf) shows the relevant timing diagram for this interface. The input setup/hold ...
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43 views

“Dynamic” shifter in priority queue implemented on FPGA (SystemVerilog)

I'm implementing a priority queue on FPGA such that if some external signal is up (\$w_r\$) the priorities are evaluated and the priority queue us updated accordingly. The schematic is the following: ...
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1answer
33 views

Zynq 7020 subcomponent equivalent parts [closed]

The Xiling Zynq 7020 has a dual-core ARM Cortex-A9 and an Artix-7 FPGA in it. What is the equivalent part number of these chips independently? (i.e. what individual part numbers have the same ...
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70 views

Reduce overshoot and undershoot of square wave (trigger signal)

I am testing my FPGA board (spartan 6) by taking external trigger signal (square wave 5V 50%.) The rising edge of the signal is shown below with overshoot and undershoot, so my FPGA can not detect ...
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2answers
52 views

How to manage an output to put only one “1” even when entry stay up?

I'm a beginner with VHDL and electronics, I'm trying to do something like this: input list: i_button1 : it's the value of the entry button (1,0) output list : o_button1_sync : it's the value of the ...
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3answers
77 views

XOR all signals of a vector of two dimensions together

I have a vector that contains 15 elements of 8 bits each. I want to XOR each element: $$ out = f_0 \oplus f_1 \oplus \dots \oplus f_{15} $$ where each \$f_i\$ has 8 bits (it's declared as logic [7:0] ...
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1answer
98 views

Design simulates perfectly but won't work on FPGA

First, thanks for the help yesterday. This time I will document my code correctly. So, we were tasked with creating a parking meter that would take 4 inputs, one adding 50 seconds, one adding 150 ...
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2answers
118 views

Inherent Pseudo-Randomness in modern FPGA design tools

Do Place & Route algorithms of modern FPGA design tools ( Qaurtus / Vivado / etc... ) have inbuilt randomness in them ? I.E: Would it be possible to get 2 different results when compiling the ...
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1answer
132 views

What are the minimum FPGA feature requirements for decoding and encoding 4k60 HDMI signal [closed]

I want to build a prototype device that manages to do the following: Take a HDMI signal with at least 4k resolution at 60fps (for simplicity without DHCP for now,) change a few pixels (say a red ...
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2answers
45 views

Can a module be declared inside another module in verilog

module A (input a, input b) ... module B (input a, input b) ... endmodule endmodule Is the above allowed in Verilog?
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3answers
119 views

How do you know if impedance is the same for 2 ICs?

in my last question I got some very interesting answers that made rethink a lot about my design as to whether or not I need termination resistors at all. Additionally, the design proposed in this ...
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2answers
59 views

FPGA/SoC - System Architecture: Independent Block Enables/Resets

For low power design, clock enables can be used to turn off a block, thus reducing dynamic power. For example, if raw ADC data is being obtained and not FFT processed data, then that FFT module could ...
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1answer
37 views

Data transmission from bluetooth module to fpga

I am using an android app which is taking a string and converting it to its ascii values and sending it to bluetooth module hc-05. Now i need to send this data to an UART receiver in an fpga. In what ...
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56 views

How to get a low clocking rate by ARTY 7?

I need to use 8 kHz as a clock signal for my LFSR IP core in my block design. But this low rate can not be implemented in ARTY 7 , as shown in the attached picture ! What are the other choices I have ...
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1answer
51 views

FPGA Element Selection [closed]

I am new to FPGA use. While I can find considerable information on programming them, I would like to know how FPGA manufacturers decided what elements to include? I.e., how is the internal design of ...
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23 views

Systemverilog code reuse, minimizing reuse error, and FPGA internal resource optimization

I'll pose a situation leading to a question as this is a bit nebulous. A module is created where a register width can be selected depending upon the situation. In various FPGA configurations an 8, ...
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1answer
37 views

Access a vector stored in another vector in verilog

I want to access elements (8 bits long) stored in an "array", then do a logic AND with some switches. So far, not working: ...
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1answer
117 views

UART receiver in VHDL for nexys 4 ddr board

I'm trying to program my nexys 4 ddr board to receive 1 or 0 as ASCII charachters via UART and display it on one of its 7segment display ,the LED that shows when its getting data is flashing but it ...
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1answer
43 views

Calculating RPM from Angular Changes

For a project, I have to determine the RPM of a turning resolver. I can correctly read the angular position of the resolver as as a hex number via an RDC. This number is then converted into a 14-bit ...
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56 views

Why my multiplexer doesn't active multiple 7 segments at one time?

First I made a clock divider at VHDL. Then I made a counter based on it. After that I made a multiplexer and I activated one seven segment in each selection case. The selection case of multiplexer is ...
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23 views

AXI Chip2Chip Addressing

I am using a AXI Chip2Chip master (with Aurora) on a MPSoC connected to a Xilinx Virtex UltraScale+ running a AXI Chip2Chip Slave. I have set the Master's to 0x10_0000_0000 with 1G of space, see pic ...
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Probing LPC bus with an FPGA yields gibberish — wiring problem?

I'm trying to repeat the TPM key dumping experiment by Pulse Security using a motherboard with Secure Boot and the same TPM1.2 chip onboard, equipped with Windows 8. However, when I connect the FPGA ...
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4answers
2k views

FPGA - DIY Programming

I've been programming microcontrollers for a few years now, and I've just discovered FPGA's after taking a digital design class. After doing some research into different FPGA's, development boards, ...
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1answer
66 views

Signed Integer Division Optimization

I've implemented a division algorithm on an FPGA using the long division algorithm. My implementation does not use pipelining, but works iteratively and requires very few logic elements since the ...
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35 views

Adding debug changes chip behavior? Reg only updates if debug instantiated

I'm doing a simple seven segment display driver for class, using a MachXO3 dev board connected to 4 displays and 2 buttons on a breadboard. The 4 common-cathode displays have their anodes wired ...
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28 views

regarding bidirectional accessing of array in verilog

Accessing ram logic in Verilog with an initial block gives an error "cannot synthesize initialized RAM logic <name> " A part of the code will be as follows (...
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1answer
51 views

Difference between wire and logic for this particular problem

I've worked this problem before in Verilog and no problem at all. Tried the same problem with SV and the problems started. The idea is to just show numbers on the first 3 7-segments based on switches. ...
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1answer
65 views

How to use different 7-segment for different numbers in FPGA board?

I'm working working with NEXYS4DDR board which has two 4-digit 7 segment displays. Using the proper binary-bcd converter I can display numbers, the problem is... the same number is displayed in all ...
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29 views

Can't import my .sof file to my FPGA

i am new to the whole VHDL/FPGA thing, and i am trying to import a simple AND gate to my FPGA, but i get the failed message everytime, any idea how to fix it? P.S : For some reason the device it ...
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2answers
94 views

FPGA Max PWM Frequency

Trying to find out what is the possible maximum PWM frequency achievable with a low-cost FPGA with at least 2'000 "steps". Being new in FPGA, I quite could not quite figure out how to extract this ...
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1answer
52 views

Shared or separate SPI buses for peripherals in a PCB?

I have four SPI-controlled chips which I want to control from Zynq-7020 via an FMC LPC connector. Each chip/device requires an SCLK, MISO, MOSI and CS line. I'd like to give each device their own ...
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2answers
63 views

Can CML differential signal lines be flipped to act as a NOT gate?

If I want to invert a CML differential D-Flip Flop (Ex: hmc747lc3c) output before entering into a CML Counter(Ex: MC10EP016), is it as simple as flipping the signal lines before entering the counter? ...
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1answer
50 views

Variable PMW generator using Verilog [closed]

I've made a code in Verilog for a variable duty-cycle digitally controlled PWM generator. I will be using it in a system I am designing for controlling a buck-boost converter that will regulate the ...
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1answer
98 views

FPGA too slow for my ripple carry adder?

I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit ...
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1answer
35 views

Full Adder driven by clock [FPGA/VHDL]

I've got Ripple Carry adder (26bit) made from scratch. ...
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1answer
59 views

Timing two parallel lines on FPGA [Beginner]

So let's suppose I want to do certain action based on certain signal. I have signal "nx"; if it's 1, I want to "NOT" an X input(16bit) and if it isn't, I want the X unchanged. My idea was to do both ...
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1answer
78 views

Finite State Machine Reset Signal FPGA

I've already done the datapath for my system using a synchronous reset and now I have to control everything using state machines. What I'm confused about right now is whether or not the reset signal ...
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1answer
53 views

Lattice Machxo3 FPGA configuration using I2C

I have a Lattice Machxo3 FPGA based design / board and currently I am configuring the FPGA using JTAG. As per the datasheet I2C also can used as the FPGA configuration interface. Is it possible to use ...
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27 views

WS2811 flicker to random colors when trying to turn them all off in a 3x3 array

I am trying to do more, but for starters, I am trying to write code to turn all of my WS2811 off that exist in a 3x3 array. Currently, when I run my Arduino project, they are flickering from red, to ...
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1answer
35 views

How does Flash*Freeze reduce power consumption in Microsemi FPGAs?

Microsemi FPGAs are marketed as being low power. They have this flash freeze mode that is supposed to achieve much lower power dissipation, down to micro watts. I am trying to understand how exactly ...