Questions tagged [fpga]
A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".
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Considerations in board layout for different interface speeds
Currently, I'm working on a design that includes four data buses operating at different datarates.
The signals connect various parts of the system to the central FPGA. I have experience in designing ...
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FPGA output timing explained
As a hardware designer you have consider the timing constraints of both the input and output device. Input devices specify a setup and hold time reference to the clock (the time in which the data ...
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Best way to go from 5V to .95V to power an FPGA at max 15A
I need to power the core voltage on an FPGA from a 5 volt supply with a lot of constraints.
This is a rad hard environment so many components are ruled out. I'm only able to find a SMPS that will go ...
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FPGA simulation runs but not hardware Cyclone V De1 Soc [closed]
I have made a block level design on Intel Quartus Prime lite. It is simulating properly but when I check on hardware (Cyclone V De1 Soc) it is not working fine. I am not getting an output similar to ...
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VHDL modular multiplication always resulting 0 in simulation
I'm trying to implement a modular multiplication algorithm in VHDL, but the result "r" is set to 0 on every simulation. I would like to know how to fix it.
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Memory arbiter in SoC
I have got a question about memory management!
I have the OpenRISC 1200 (OR1200) on Flash based FPGA and I'm trying to check the model after synthesis.
To do that I need to realize how to organize and ...
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DDR4 Routing Consideration on pcb (no DIMM)
I need to route DDR4x2(3200MHz) to my FPGA.
my stackup is 12 Layers, TH Via only, and thickness of 2mm PCB.
my question regard which layer to route the FPGA to DDR4, when the two component on the TOP(...
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How to change the FPGA supply voltage (VCCint and VCCBRAM) beyond recommended operating conditions on Vivado?
I am new to the field of FPGAs. The FPGA I am using is Virtex-7 VC707 -2 speed grade. In my research project, I am required to reduce the supply voltage (BRAM's specifically) to a low value, say 0.7 ...
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How to properly constrain this hold time?
I am puzzled, can't get to any seemingly simple and, what's more important, solution looking correctly.
There's a main fast clock, fclk, and I divide it by 4, ...
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SPI read of MAX31856 in Verilog
I am trying to read the K-type thermocouple temperature with MAX31856 in Verilog.
Configured the configuration registers CR0 & CR1.
The conversion result is stored in the registers 0xC, 0XD, 0XE. ...
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Unable to write to MT25QU256 from Arria 10 SOM
I am using module Arria 10 SOM by iWave with IC Flash MT25QU256. I am trying to read and write from NIOS II processor to different sectors of this flash.
Currently, I'm using the IP Core Generic Quad ...
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OpenRISC FPGA implementation
How it is possible to realize data and instruction caches, data and instruction MMUs, multiply and divide instructions, SRAM and all other memories, - as generic flip-flop memory? According to Chapter ...
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How can I achieve a higher precision than 14-bit in an analog to digital conversion (ADC) [closed]
How can I achieve a higher precision than 14-bit in an analog to digital conversion (ADC) without using conventional ICs on the market?
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ECP5: Determining max current an FPGA pin can sink from datasheet
I have a circuit where I want to drive the CS# input on a SPI flash chip from an output pad on an FPGA. The flash IC's datasheet recommends putting an external ...
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How to get a clean clock signal from FPGA to DACs?
I have the VC707 FPGA board and an external reference clock (fairly clean 100MHz), that I want to use as a reference for a 200MHz generated clock on my board. Then using this clock to clock my DACs (...
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USB peripheral not responding to SETUP packets
I'm writing some Verilog on a Spartan S7-50 FPGA to control a MAX3421E (datasheet) over SPI. I've gotten everything working with setting up the chip (full-duplex, Vbus, connection detection, host mode)...
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Different ways of fanning out low jitter clock signal
Recently I'm working on a project that involves a FPGA and two high precision DACs.
The DACs require a low jitter 27MHz clock (RMS jitter < 1ps) to function at their datasheet performance.
There is ...
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Verilog variables updated only when assigned as an output
I am facing a strange issue, and I am not sure what is going on here:
assign output_data = {3'b000, cmd_state[1:0], w_data[2:0]};
Where last 5-bits of output data ...
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VHDL schematic without connections [closed]
I'm learning VHDL and I tried to replicate a circuit that I found surfing in internet. The problem is that the schematic shows without connections in the input ports.
The program is a frequency ...
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Is it possible to know through simulation whether we have the right number of decoupling capacitors?
More decoupling capacitors than a certain amount does not improve the power integrity much. I am not sure if this is a case of diminishing returns or a case of reaching a wall.
How exactly can we ...
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Connecting GPIOs on two boards with independent power supplies
I'm trying to design a board that will accept UART/8N1 input from another board at 3.3V. While the two boards share a common GND (obviously), they otherwise have totally independent power supplies: ...
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FPGA clock only positive lag?
I have an FPGA with the following, simple clock divider, written in VHDL:
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Verilog- Why is my state machine output arriving one clock cycle earlier?
I'm writing a Verilog code for a state machine with 4 states. state 0 is buffer time of 1 microsecond. state 1 is trig pulse for 10 microseconds. in state 2, the input is read. If the input is high ...
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Proper way to make HDL and timing analyzer understanding the clock slowdowns
This is a question spans two fields - HDL synthesis and timing analysis.
In the design I define clock with specific frequency, and if design has
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Implementing DDR In/Out DQ Pin for DDR3 SDRAM on Xilinx Spartan-6 FPGA
I’m currently working on a project that involves interfacing a DDR SDRAM (Micron MT41J128M16) with a Xilinx Spartan-6 FPGA. I have implemented a controller. I’m looking for guidance on how to properly ...
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How can retrive the localtion maximum of an array in hardware design
Suggesting a 200*200 array (Matrix) of registers, which contains unsigned integers.
Is there a better way to locate the maximum number rather than find the maximum and binary search: O(n)* ADC time
It'...
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SDC constraints at the module level
Must be simple question I can't find answer for.
I design Synposys design constraints file, and have a module, let's call it module1. A the top I connect it using
...
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VDHL - Using multiple I2C devices with single IP
I need help with a design that I am currently working on. I am using a Spartan 3 that is on a custom board that checks 6 devices using I2C and these devices all have the same address so I am trying to ...
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SOC booting FPGA configuration file
I have some understanding on embedded system booting process, which includes step wise execution of:
ROM boot loader.
First stage boot loader - internal to SOC.
Second stage boot loader - stored on ...
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How to get load capacitances from an FPGA design for third-party dynamic power analysis?
I would like to perform dynamic power analysis of an FPGA design outside the design tool environment. For this, I need the equivalent load capacitance of every net in the design. How can I get the ...
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Using Atomminer AM01's fpga for purposes other than mining [closed]
I was thinking about Using Atomminer AM01's fpga for purposes other than mining, maybe using vhdl or verilog, I wanted to ascend if it is possible?
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FPGA HDMI Video Lag tester doesn't display on FPV goggles
I've forked this video lag tester Verilog project, which is itself a port of the time-sleuth project to the GOWIN Tang 4K FPGA. My intention is to build something that can test the input lag on FPV ...
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What does it mean for a digital logic signal to qualify another signal?
The wishbone specification refers to signals being qualified by other signals:
The strobe output [STB_O] indicates a valid data transfer cycle. It is used to qualify
various other signals on the ...
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Lattice Diamond timing errors in place and route with large registers
Is there a good way to generate a timer with at least 27bits of precision so the place and route doesn't fail? I've tried breaking up the timers into 4x8 bit timers, but it only makes the slack worse (...
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Verilog Non-Blocking and IF statement mixed
always @(posedge clk)
begin
clk_counter <= clk_counter + 1;
if(clk_counter == divider)
clk_counter <= 0;
end
Will the ...
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Timing constraints for external ADC for clock generated by FPGA
I am using an FPGA to generate a 100 MHz clock to an external 8-bit ADC.
The external ADC is the ADC08100 and the valid sample window is -1.5ns to 4.4ns in regards to the rising edge of the clock. I ...
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FPGA controlled ADC has undefined data
I have an MAX11116AUT-T ADC Controlled by an FPGA at a 6.25MHz clock.
Once the CS signal is set to low, I can see data being returned by the ADC on the falling edge of the clock.
There is, however, a ...
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How can you find the maximum aggregate I/O current supply for a Lattice FPGA?
I want to find the maximum aggregate I/O current supply for the MachXO3D (9400HC) breakout board to ensure that I do not damage it. All pins will be using the LVCMOS33 I/O standard. I have been up and ...
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Ice40 SB_IO primitive input has glitches
I am trying to implement SWD protocol on ICE40 USB stick using Verilog. I have designed the SWDIO as inout in my program whose direction is controlled by a wire ...
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Should I buffer my switch button input?
I have external switch with 24v/open circuit.
I think that I only need voltage divider and drive the FPGA input, but something feels weird for me, maybe I need some capacitor for noise? maybe some ...
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How to do clock signal rising edge detection in Chisel (scala)?
I have encountered in a problem of rising edge detection in writing chisel code. Here is the code I wrote.
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What do these symbols mean in Lattice Diamond software?
These two pin symbols are in the Lattice Diamond Device View, what is the difference between the two? They both say differential I/O pin when I hover over them.
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Parsing variable-sized data in 32-bit datastream
I have a 32-bit datastream coming from a sensor. The data is encoded as a Type-Length-Value encoding. This means the first byte indicates what kind of data there is and the second byte contains the ...
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Substituting an outdated FPGA with another one from the same family
I have a board with an Altera EPF10K30RC240-4N. It has an EPC1 next to it, which I found is the "Configuration EPROM". I assume this stores the "program"?
The FPGA is not ...
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Entire FPGA getting hot evenly, not just a single hot spot
I have a board with an Altera EPF10K30RC240-4N that is not functioning at all. There is a high current draw on the board. The +5V rail is only 2.6V and there is 4.2 ohms between +5V and GND.
The board ...
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Timings constraints when interfacing an external ADC with an FPGA
I am currently using a Trion T8 FPGA to receive and store data from an external ADC, the ADC08100. The FPGA uses the internal PLL to generate a 100 MHz (10 ns period) clock signal, and its logic runs ...
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Entire Perimeter of FPGA Getting Hot - Why?
I have a commercially-produced board with an Altera EPF10K30-series FPGA. There is an abnormally high current draw on the board. Where +5V should be present, there is only +2.6V.
When comparing ...
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Driving LED with PMDXB600UNE MOSFET from FPGA, MOSFET never turns on
LED was placed rotated 180 degrees during assembly.
So now my question is will this circuit work or should I change it in anyway?
I do realize similar questions have been asked, but I think my problem ...
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ADC Timing Problems in FPGA design
I am using a Xilinx Kintex UltraScale FPGA (AXKU040 development board) and an ADC board (FL9616 board). I would like to have a design that provides the ADC data as a data stream inside the FPGA. The ...
