Questions tagged [fpga]
A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".
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Is it possible to use basic networking on an FPGA without an OS?
I need to set up networking (just a basic echo server) on an FPGA board (ZYNQ Ultrascale+) using only the PL side. The end goal is to DSP a large amount of data coming from a receiver through ethernet....
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Top-level HDL File with Libero SOC
I'm using Libero SOC for the first time. I've used Quartus and Vivado before. I notice in the tutorials ways to use the graphical "Smart Design" file type as a top level module. But I can't ...
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Verilog blocking statements in always block [closed]
I need to perform an addition inside an always block (with clock) but one of the operands depends on the previous value, hence I cannot use non-blocking statements as all variables/registers/wires ...
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X-Y-Z video signal to VGA converter using FPGA [closed]
I want to convert X-Y-Z video signal output of a device to VGA format to be displayed on a PC LCD monitor. I need an idea how to this. Maybe Something like Mega_Creamery's Altera Cyclone FPGA project ...
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LVDS vs driver strength in FPGA IO
In the FPGA, there is I/O constraints that can be done to configure the output buffer. Some of these constraints are like setting the output drive strength parameter, on die termination, output delay, ...
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Is Unified Power Format "UPF" applicable for FPGA? [closed]
I just want to reduce the power in my design which I use FPGA, I am aware of UPF, and my question is, can I use UPF in FPGA? if not, so, are there any techniques to reduce power dissipation in FPGA ...
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Vivado constraints wizard suggests a lot of `create_generated_clock` which (seem to) make no sense. Can I ignore them?
I have a Verilog design of a RISC-V CPU + some peripherals, which I'm synthetizing with Vivado for a Basys 3 board.
The Vivado constrains wizard suggests a ton of generated clocks which (in my eyes) ...
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Access register values from a PicoBlaze / MicroBlaze soft processor
We are conducting research on the reliability of registers deployed in embedded RISC processors where the focus is to ensure the reliability of their contents during transient faults. To do this we ...
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Basys 3 FPGA 7 segment display output delay
I have an FPGA design for my Basys 3 that drives the board's 7 segment display to display some numbers. I'm using Vivado.
When I do the timing analysis, the constraint wizard asks me to set the output ...
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Don't understand why this clock interaction is unsafe
I'm starting with static timing analysis. I have a very simple Verilog design that has clock interaction problems, and I don't see why. It just has a counter whose LSB is sent to an LED. Could I get ...
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Hold violation in clock divider in an FPGA
I have a Verilog design for a Basys 3 in which I display a number increasing by 1 each half second in a 7 segment display.
I'm running the timing analysis in Vivado, and I get a hold time violation ...
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In an FPGA, is the input port delay related to the output port delay in the previous block?
Consider the following circuit in an FPGA:
Let's say the output port O1 is constrained to have a min/max delay of 1 and 3 ns respectively. That means the circuit will be optimized for allowing a max. ...
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What is name of the technique where we create modules to help us test our digital design?
In my FPGA design project, I created a few modules that can be used to emulate output from another module. Then there were modules that would inject erronous data or signals that signify errors. By ...
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External frequency as input to an FPGA [closed]
I want to take frequency generated by a function generator as input to an FPGA board (Nexys 3). I am trying to use a square pulse of 10 kHz as input to the FPGA. So to test how to take an input from ...
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Will FPGA synthesis tools ignore unused modules?
In a VHDL/Verilog design, is it a bad practice to define several (related) modules in the same file?
Will the Vivado synthesis tool be 'smart' enough to not book FPGA resources for unused modules?
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Difference in synthesis between bitwise AND (&) and logical AND (&&)
Would these two code snippets synthesize the same way? I know this will be tool dependent because all synthesizers are slightly different. That being said, I think they probably tend to agree on this ...
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Clock network, Unconstrained clock for virtual I/O? Even though bitstream is generated, how does vivado do it even if there is no clock?
Hi, all I am new to fpga and vivado. Any kind of help would be highly appreciated. So, I am using a vio and ila to observe the output of a Ring oscillator (RO) concurrently running with a soft ...
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When are these adder algorithms used in digital circuit design?
Whenever I need to add two numbers, I just write a+b in VHDL. I never have to bother about what is synthesized, as long as timing and area constraint is met I think the objective is achieved.
I have ...
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What's the smallest (quanta) component that can be used for adding signal delay?
I am trying to add some delay to a signal. Currently what I am doing is adding even numbers of NOT gates to the signal. This could add some delay to the signal without changing it.
However, the added ...
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DMA data transfer error with custom IP state machine
I am trying to transfer data via my custom IP AXIS Interface in my Arty Z7-20 FPGA. The data I sent through Vitis should be processed through my custom IP and be sent back to Vitis.
This operation ...
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Do any FPGAs that set undefined values in registers after power up exist?
There is some discussions how to set default values or start an initial sequence in FPGAs design after programming/power-up.
The most reliable method is using a supervisor IC which guaranteed send ...
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How can the ifdef SV macro determines if Quartus has running a simulation or synthesis?
I know that almos every synthesis or simulation tool has an option to define a custom macro before synthesis/simulating starts with the console command. For example:
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FPGA to SDRAM communication
I am working with a DE0-nano board, on which is a Cyclone IV EP4CE22F17C6 FPGA, connected to an ISSI IS42S16160G-7TLI 16Mx16 SDRAM chip. In order to setup the communication between the FPGA, I've ...
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High-frequency signal crossing in different layers
I'm working on a project which should connect an FPGA to some MIPI-CSI2 signals.
There are ten cameras, each one using four differential pairs plus one pair for the differential clock.
I'm routing the ...
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Is there an analog of VHDL "wait-for-until" expression in the SystemVerilog Assertion?
Suppose we have two signals: A and B. And we need to check that the rising edge of signal B is between 7.62ns and 7.77ns after the rising edge of signal A. In VHDL this can be done with two "wait-...
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Why do I get an inferred latch error here?
I've been building a design in the simulator that uses a shift register. It has the following design goals:
if reset_i, then set ...
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How to check for immutability the simulated signal after edge coming in SystemVerilog?
Suppose that we have some module (which simulates FPGA external environment) with an input line (from a FPGA). When an edge (rising/falling) comes from this line the module must test that the logic ...
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Verilog register declaration with "variable index"
I'm trying to create 8 16-bit registers in Verilog that will take 16-bit values from a 128-bit long shift register. Obviously, I have to make use of index variable such as "i" to make this ...
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Is it possible to create crosspoint(crossbar) switches with FPGA?
we have 4 USB type C ports in one of our projects. We are using TPS65988 and TUSB546A-DCI for PD control and crossing USB signals. We want to take design to the next level with the crosspoint switch, ...
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Fast ADC interface with FPGA
I have to interface a fast ADC with an FPGA and then do the data processing. The FPGA used will be Zynq Ultrascale+ RFSoC ZU29DR. I have been given the information that ADC_clk = 4x FPGA_clk. ADC ...
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Verilog generate block error
I have a CORDIC module that I want to instantiate/generate 8 times, basically, I need 8 blocks of CORDIC. So, I have wrote the following statement block, but I get an error:
Error: Syntax error near ...
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Why don't 2 flip-flop synchronizers have a reset?
This is similar to this question, asking if a reset is needed in a 2 flip-flop synchronizer. The answer to that question was: "no, not necessarily".
So, my question is:
Why do almost all of ...
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Why is a reset with asynchronous assert safe?
As far as I understand, a reset with asynchronous assert, synchronous de-assert is considered absolutely safe. I understand that this prevents metastability at the output of a flip-flop using that ...
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Kria KV260 clock doesn't work
I'm trying to run a very basic blinking LED with VHDL on a Kria KV260 board.
led_blink.vhd:
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Do I need a clock crossing circuit for signals clocked by mirrored PLLs?
Assume that within an FPGA, I have two data streams that are being driven by two clocks. The two clocks are generated by 2 physically separated PLLs (still within the same FPGA), both of which have ...
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FPGA-centric timing constraints
I have designed an MMC slave on an FPGA that will interface with many different MMC masters with many different trace lengths, etc.
Most of the timing constraint documentation on how to constrain ...
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Is the place and route tool erroneously inferring a combinatorial loop from VHDL?
The problem is an inconsistency I observed when I compared the result of the synthesis step to the result of the P&R step. The P&R inserts a combinatorial loop which is not present in the ...
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Is there any advantage to specifying the "range" of an integer in VHDL?
Is there any advantage to specifying the range of an integer in VHDL? I know an integer is 32-bit by default.
For example, two counters that will only ever count up ...
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ADC parameters confusion
I want to interface an ADC with an FPGA but I'm confused with some basic terminologies. What is the relation between ADC sampling rate and the output data rate of ADC? For example, if ADC sampling ...
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FPGA I2C master not working
I have written an I2C master for the DE10-Nano FPGA which is meant to communicate with the SSD1306 OLED display driver.
The issue I'm having is that it simply is not working when I actually test it on ...
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Quartus Prime Nios II software build tools error "Failed to execute: wsl dos2unix create-this-bsp"
I am using Quartus Prime Lite 21.1 and am trying to use the Nios II software build tools for Eclipse.
When I try to create a project I get "Failed to execute: wsl dos2unix create-this-bsp; ./...
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Do wire/net type constructs in Verilog map to programmable interconnects/ switching matrix of FPGA?
Reprogrammability in FPGAs comes from 2 building blocks: configurable logic blocks (LUTs) and switching matrix.
It is often said that the HDL code gets translated into the corresponding LUT logic, but ...
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Pipeline stream demux
I'm a software guy who is self-taught using an FPGA, so forgive me if this question is trivial.
Basically I have a stream (data, ready, valid, start, end). Depending on the first data word in the ...
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Giving write enable signal externally by DIP switch to FPGA memory
I have designed a simple internal SRAM memory where I initiate the write enable and read enable via DIP switches.
Verilog input wire has been declared in the simple memory read write which connects to ...
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EMMC standard versions backward compatibility
I am hoping someone can help me debug an FPGA to EMMC interface problem.
Background:
I have designed a board with an FPGA, DDR memory and an EMMC chip (8 bit mode). The FPGA design is working and most ...
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Xilinx ISE on Debian 10+
I have been working for quite some time now with Xilinx ISE 14.7 on Debian development machines. Before the suggestion comes: We use a Virtex-6 FPGA for our research and have no option to switch to ...
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Are FPGA and PC communications possible without a microprocessor i.e. do all FPGA dev boards have processors in? [closed]
I am new to FPGA design. I have worked on a Zedboard, used AXI bus and developed IP. However, I am not clear on some of the basic things. I would like to learn the following questions. My sincerest ...
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Studying the PCIe/CXL/CCIX internals at home
Could anybody recommend me a good starting point for self-studying the PCIe internals?
I imagine some kind of an FPGA-based course, covering PCIe endpoint, root complex and switching functionalities. ...
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Help with "Constraint Wizard" in Vivado
I am new with Vivado and I need help with "Constrain Wizard".
My design has as constraint a "clk" 1ns I added in the "Edit Timing Constraints", and I obtained the ...
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CPLD Programming via Microcontroller
I am new to CPLD's and I have a CPLD connected to the microcontroller via JTAG. Xilinx has an application note (XAPP058) about programming but I could not understand very well. Steps that I understand:...
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