Questions tagged [fpga]

A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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23 views

Where did I code my multiplier wrong?

I've wrote a verilog code for Multiplier (8bit). I'm not getting the right result. Kindly tell me where i went wrong. ...
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Lattice Diamond — How to identify which parts of design take most of FPGA resources?

I have a Lattice FPGA-targeted design which already takes approximately 95% of the SLICEs available on the device; pretty close to the chip capacity. Unfortunately, I need to add some more logic to it,...
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VHDL Comb-filter in decimation

How to implement the following equation in vhdl: Y(n) = X(n) – X(n-4) ? My attempt ...
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58 views

BSS138 level shifter causing problems

I have encountered a problem that I am unsure how to solve. As shown in the image at the bottom of the question, I have an FPGA (Nexys A7-100T) that generates signal to run a motor connected to a ...
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Lattice Diamond assign unconnected poin

I used to work with the Lattice IceCube IDE where I just constrained all pins to the corresponding signal not matter whether they were actually used in the design or not. No I have to create a new ...
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Lattice iCECube2 cannot find clock in .sdc file

I've tried a zillion different ways to get the lattice iCECube2 tools to find a generated clock. How do I specify the .sdc file to see the output of baudgeninst, ...
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STM32 in emmc-slave role. DMA transfer by both edges of external clock

I want to implement emmc protocol in a device role with STM32 (for now I've had ST-Nucleo-F767ZI and ST-Nucleo-F429ZI dev boards). Idea is to have a bridge to real emmc with STM32 as an adapter. STM32 ...
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69 views

Help developing rpm calculation from encoder pulses

I have having a bit of difficulty calculating rpm of a motor using feedback from an encoder. The encoder datasheet is attached here: Encoder datasheet. The encoder has two channels at 1000 PPR, so ...
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44 views

How to create a design that uses specific % of DFF and LUT count in FPGA to measure power dissipation?

I want to create a design which does not perform any specific useful function but utilizes specified amount of logic resource in the FPGA e.g 50% DFF and LUT or 50% DFF and 25% LUT e.t.c. I shall then ...
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LCD 16x2 (I2C) with FPGA (Altera Cyclone II)

this is the question, a few days ago I bought the FPGA Cyclone II development board from altera (I am a big fan of arduino and I have a variety of modules and others) at first I started studying ...
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838 views

I'm trying to measure relativistic speeds with an FPGA — are my results legit?

I've been teaching myself FPGA programming in Verilog over the past year during the COVID-19 lockdown. I found a discussion of whether it was possible to measure the speed of light using an Arduino or ...
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59 views

How to pack oddly sized chunks of data into 128-bit FIFO

In my FPGA project we get a 100-bit wide vector on each 100 MHz clock cycle from a 10Gbps receiver. I can then compress it to 75-bit wide vector due to some particulars of the data. I would like to ...
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Verilog conditional assignments without using procedural blocks like VHDL with/select

I am trying to find a way to conditionally assign values to a signal in verilog similar to the with/select in VHDL. So far I found two ways https://www.chipverify.com/verilog/verilog-4to1-mux. This is ...
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54 views

FPGA to DMA to RDMA

I am trying to send data generated from my FPGA card out to an IB device. I want the latency to be as low as possible, so I am thinking this may be the data path. FPGA --> DMA via scatter/gather ...
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64 views

What is the FPGA with the highest LEs / $?

Well, what is the FPGA with more Logic Elements per Dollar? I already tried to search some sites but the filters for the products do not include that option.
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Understanding delay balancing on a pipelined design with feedback

Trying to find a solution on how a design with an inherent feedback can be pipelined, I came across this resource: https://cas.tudelft.nl/Education/courses/et4054/hls_chp4.pdf (Pipeline Feedback ...
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Displaying a video on VGA using FPGA

I have succeeded in displaying an image on a VGA monitor using FPGA, by generating a ROM loaded with a coe file. But knowing that a video is a succession of images, how can I do that? Any ideas please?...
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How to implement a continuously scanning multi-channel system in Verilog

I currently have a multi-channel system where each channel is receiving a pulse at different times. I want whichever channel receives its pulse first to act as the reference to then measure the time ...
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What's the best cheap FPGA for performing SDR tasks with RF RX and TX? [closed]

I am looking for an FPGA to be able to do SDR tasks with, such as modulation, mixing, etc. I would like to do this stuff with VHDL and Verilog. I have a Nexys2 FPGA, but it has no RF inputs and ...
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105 views

How to make a register in VHDL remember?

I was given the assignment to implement an 18-bit register in VHDL. I used an example from the book "Free Range VHDL" recommended to me earlier. Here's what I got: ...
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65 views

VGA controller Simulation works fine but Post-Synthesis Functional and Post-Implementation Functional Simulations don't

I'm new at VHDL programming and for about 3 weeks I've been struggling just to make a VGA controller and display an image. The behavioral simulation works fine, but post-synthesis functional ...
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73 views

SDC Constraint for reset synchronizer

I have a reset bridge in VHDL which is based on a multi-FF synchronizer chain as depicted below. This reset bridge is used in various instances throughout my design. I want to properly constrain the ...
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31 views

Black bar and red / green swap in OV7670 image

I´m working on my OV7670 interface and I have some issues with the color / image settings. I use the color bar settings of the sensor to check my logic and the color bar looks good: But I´m unsure if ...
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What is the benefit of having dynamic configuration in FPGA PLL?

With PLL it is possible to generate clock signal at different frequencies and phase values. So far I have seen that these settings are done at design time and do not have to be changed during run time....
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70 views

A simple VGA controller in VHDL not working properly [duplicate]

I'm trying to make a VGA controller to display an image on FPGA in VHDL, so I searched and found a code in the book of Volnei A.Pedroni- Circuit Design and Simulation with VHDL in page 432 that I ...
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318 views

ADC Chip Timing Question

When is the best time to read the bit out of a serial data output 12-bit ADC chip. The chip is a AD7476A, and here is the datasheet AD7674A Datasheet. Going by the timing diagram, when is the best ...
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How to view a detailed resource utilization report on an FPGA design when implementation fails in Xilinx Vivado?

I'm using Xilinx Vivado 2020.2 on Windows 10. When I attempt to generate a bitstream, it fails at implementation with this error: So I need to reduce the number of FDCE cells I'm using. That's doable,...
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127 views

Is an opto-coupler fast enough for this application?

I am counting the pulse edges from a quadrature encoder with an FPGA and using opto-couplers as the encoder is powered with 12V and the FPGA inputs are 3.3V. The encoder is 1000ppr with 2 channels and ...
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62 views

Encoder PPR Required Resolution

This question leads on from a question I asked last night, so some people will know it. I am using an FPGA with a 1000 ppr rotary quadrature encoder counting 4x (counting all edges is 4000ppr) and had ...
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75 views

How to implement neural network using FPGA? [closed]

I want to design neural networks using FPGAs and make neuromorphic chip. Is there a tutorial or course to learn how to do that and to implement neural network using FPGA especially for evaluating the ...
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Question about PID control loop timing

For my project I am creating a RISC processing architecture on an FPGA that can perform various basic instructions like adding, multiplying, subtracting, storing and fetching from memory etc. To prove ...
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Why is my FPGA clock so slow

To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this: <...
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120 views

Program FPGA without JTAG?

I write embedded software that runs on a single board computer running Linux and talking to FPGAs. I do not do FPGA design, so I'm at the edge of my knowledge with this question: how do I program an ...
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75 views

Is it a good practice to define TRUE/FALSE constants in SystemVerilog?

Is it a good practice to define TRUE, FALSE, HIGH, LOW, ENABLE and DISABLE constants/defines/parameters in separate file and use them in expression ...
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51 views

Why do we use FIFOs and RAM in an image processing scheme?

I found a cool project (https://www.youtube.com/watch?v=aGCcT7p0-wY&lc=) which I want to replicate. This is the flow: Analog camera -> ADV7180 (it converts the video from NTSC or PAL to 8-bit ...
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484 views

Can't get ADC chip to work

I am connecting a 10k potentiometer to an ADC chip (LTC1273BCN) that has a 12-bit parallel output, like in the diagram at the end of the post. The 12-bits will be connected to an FPGA input bus after ...
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74 views

Single Value range is not allowed in packed dimension

I have been reading about packed and unpacked dimensions in systemverilog from https://www.chipverify.com/systemverilog/systemverilog-arrays, in the following code I just want to use a memory array ...
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99 views

How to parameterize a clock divider?

The best clock divider is a PLL inside a FPGA. But the number of PLLs are limited. And sometimes using of counter to divide a clock is justified: ...
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39 views

Which software tools from LatticeSemiconductor do I need to develop design with iCE40 LP FPGA?

There are a lot of programs that can be found here: https://www.latticesemi.com/en/Products/DesignSoftwareAndIP Which of these do I need for creating a design with iCE40 LP FPGA? The reason for my ...
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115 views

Can an FPGA/ASIC have an Operating System?

I know FPGA/ASIC are for a specific task and they are not microprocessors and an OS is needed mainly if multiple processes(tasks) need to be run concurrently. Just wondering if an FPGA/ASIC can have ...
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70 views

Can I implement FIFO to between requester and arbiter? [closed]

There is multiple requester connected to Arbiter. Requester is placed far from the Arbiter and leading to long nets. Because of this there is a timing violation. So, FIFO can be implemented meet the ...
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85 views

Which type of registers is used in CPU: serial or parallel? And how to implement them in VHDL?

I'm making a CPU in which the memory is represented as a two-dimensional array, using FPGA. I've come to the implementation of registers, and I need the answer to this question. I'm new to electronics,...
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50 views

FDRE with RST tied to 0 to synthesize a value at reset at 1: hardware value not correct, why?

Here is the code of a developer (let's ignore the name of the signals): ...
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Multiple Avalon Data Master in Nios II Custom Instruction Crashes CPU

I am attempting to make a Nios II Custom Instruction which performs the function of summing a floating point array, given the array pointer and length. The custom instruction component has an Avalon ...
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2answers
56 views

Split JTAG Interface

Problem: We design a PCB with an JTAG compatible FPGA that I need to program. Now I want to be able to access the JTAG Interface from either a connector (_A) or an FT2232H USB controller (_B). The ...
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64 views

Why use LFSR on this context?

There is a task in Pong chu's fpga prototyping book which is to basically generate a random number from 0 to 15_000 millisecond. I saw someone's code who used LFSR. (ctto owner) The author used a ...
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83 views

SPI clock signal (SCLK) usage in FPGA SPI slave

I need to design an SPI slave peripheral inside an FPGA that shall be used to communicate with a Microcontroller and configure the behaviour of the FPGA design. I have a few questions. If the FPGA ...
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38 views

SPI communication between FPGA(ZC-706) and Amega128

I'm trying to write a communication protocol between an FPGA and a Microcontroller through an SPI, the µC being the Master here. FPGA: ZC-706 (Zynq-7000) µC: ATmega128 Here is the code which i used ...
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64 views

VHDL Counter Design Question

Can I design a counter to increment on the clock rising edge? For example, I am tying to create a counter that increments on the rising edge of the clock if an input is a logic level 1. If the input ...
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Lattice iCEcube2 “unexpected error”

Not sure if anyone can help me with this... I have a rather large/complex design which so far was syntheziable without problems but with the last (although very simple changes) my iCEcube2 gives me an ...

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