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Questions tagged [fpga]

A Field-Programmable Gate Array (FPGA) is a logic chip consisting of an array of programmable logic blocks and interconnects that is configured by the customer after manufacturing—hence "field-programmable".

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Brand new FPGA burnt?

So, when I plugged in my FPGA for the first time, it started to smell a bit like chemicals, and this showed up. Is it burnt, or is it just some type of residue that popped up once I connected it?
superogg1's user avatar
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2 answers
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Create ROM using Logic Elements vs Block RAM

In FPGAs, one can create a ROM using logic elements and also using block RAM. When using block RAM, we would follow the tool vendor's process to create a ROM. For Quartus, this means that we specify ...
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How to list full path of all FDSE instances in Vivado design?

I want to see the path of all the FDSE instances in the Vivado design. Just to see where are these registers in the design, which .sv files. AS can be seen in first image that the in the utilization ...
Shajeel Iqbal's user avatar
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1 answer
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Hardware driver compiling from Vitis for USRP devices of Ettus

I am new at sdr world. I am willing to work on sdr from ettus (E320) I know about uhd and its usage from gnuradio. However I dont want to use any oot application on my computer and I am not sure about ...
Emre YILDIZ's user avatar
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40 views

Latches Due to Asynchronous Load of a PISO Shift Register

What appears to be a simple problem raises a few questions regarding latches. In trying to replicate a TI SN74HC165 PISO shift register within an iCE40UP FPGA, I've come up against a situation where a ...
toma678's user avatar
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0 answers
30 views

Feeding data stream to FPGA using PCIe [closed]

I am trying to use PCIe with ultrascale+ device and feed the fpga with data stream and send it to another device using PCIe over SFP+ optical cable. However, I don't know how to feed data to the fpga (...
B.jawaher's user avatar
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1 answer
47 views

32 bit Multiplication synthesis in Quartus in VHDL on cyclone V FPGA

I encountered a strange behavior while simulating my ALU. I designed a 32-bit ALU in VHDL to perform addition, subtraction, multiplication, division, OR, AND, and XOR operations. During simulation, ...
UserHomeInit's user avatar
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1 answer
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How AXI is implemented?

From what i understand AXI is interconnect standard, as far as i understand "interconnect" should be somthing like MUX allowing data pass from same port to different end-points. Although i ...
Hitab's user avatar
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50 views

Weird FSM behavior on the start only

I am a vhdl beginner working on this entity that goes through 256 12bits inputs alternating with even index inputs in "a_s" and odd ones in "b_s" and this 16 inputs at a time (8 in ...
Anis Bensidhoum's user avatar
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1 answer
71 views

FPGA direct coaxial output is not working

I am using a Zynq device and trying to create a coaxial output port. To achieve this, I first connected the output of the I/O port to an LED and verified that it works correctly by inputting it into ...
fnclovers's user avatar
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1 answer
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Lattice Diamond PLL Configuration for decimal output

I have been working on a Lattice FPGA to configure a 37.125MHz output for a 24MHz input clock... but the only way I have been able to accomplish getting this is with a 5% tolerance and a big ...
jukebox41188's user avatar
3 votes
3 answers
259 views

Using register after multiplier in the MACC

I am creating a design that must be portable across different tools: Xilinx Vivado, Intel Quartus, Microsemi Libero. The design uses multiplier followed by adder that accumulates the results from the ...
gyuunyuu's user avatar
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1 answer
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Resource consumption of Ettus USRP devices [closed]

I am desiring to work with one of the Ettus USRP devices. I want to learn about resource and power consumption of each default image files? Is there any way to open the RFNoC designs on Vivado with ...
Emre YILDIZ's user avatar
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1 answer
68 views

Finding the largest std_logic_vector in an array (VHDL)

I am trying to create an output layer classifier for a neural network that is implemented on FPGA (in VHDL). The classifier should simply return the array index that contains the largest ...
David777's user avatar
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Yokogawa WT3000 don't boot

I have a Yokogawa WT3000 Power Analyzer which I was using with no problems and then I turned it off to take a break. An hour later, I tried to turn it on and I notice that it shows nothing on the ...
Franco Fischer's user avatar
1 vote
1 answer
46 views

Creating entity/module containing IP from different vendors

In FPGA design often we need to instantiate vendor specific IP. This could be simple things like Block RAM and DSP. It could be more complex things like FPU IP. The 3rd party IP is directly ...
quantum231's user avatar
1 vote
1 answer
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Lattice FPGA - JTAG Programming 6Pin VS 10Pin

I'm using a Lattice MachXO3LF FPGA, specifically the LCMXO3LF-4300E-5MG121I, and I want program it using JTAG and the HW-USBN-2B programming cable from Lattice. In the Programming Cable Users Guide, ...
user373900's user avatar
2 votes
2 answers
440 views

FPGA Block RAM: Does Read Enable being low save power?

I am trying to understand the actual purpose of the read-enable signal on synchronous FPGA Block RAMs. I do not see the actual need of it. But regardless of why it was put there in the first place, ...
quantum231's user avatar
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1 answer
70 views

How to use FPGA system clock for my design in vivado?

Problem is my device don't use system clock generator (what me need) for synchronization,but use clock signal is generated by TestBench what connected via external I/O ports of FPGA. I have ...
Vladislav Butko's user avatar
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1 answer
60 views

Altera FLEX 8000: Extracting "bitstream" from .sof file?

I've acquired an Altera FLEX 8282A FPGA and I'd like to have a bit of a play with it. Yes, I know these are prehistoric parts, but I like playing around with old stuff. :-) I've installed MAX+Plus II ...
Tom S's user avatar
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Problem with two's complement fixed point arithmetic in hardware

I am trying to implement a basic spiking neural network on FPGA, and have came across a problem. The design uses fixed point binary addition and subtraction to sum input values. As weights can be ...
David777's user avatar
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0 answers
16 views

Reset supervisor with PGOOD of other supplies

I'm attempting to use Resetn of some IC device of TI that sense 4 voltages and after some threshold the IC output release the ResetN, but I'm afraid that it is not enough and I want to ensure the ...
Knowledge's user avatar
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2 answers
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Is it possible to use a 2 flip-flop synchronizer for reset?

I have seen designs for asynchronous resets synchronization like in this picture: I think I understand the asynchronous assertion and synchronous deassertion that this design delivers. I am not ...
GuentherMeyer's user avatar
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1 answer
51 views

How does a Lattice MachXO3LF FPGA handle undefined IO states?

In the Lattice MachXO3LF FPGA, if an IO pin voltage is in between the thresholds for VIH min and HIL max, how does the FPGA handle this? How does the FPGA handle if the undefined state was reached ...
user373900's user avatar
2 votes
1 answer
47 views

Lattice MachXO3 FPGA VIL and VIH of Mixed Voltage I/Os

The Lattice FPGA MachXO3 sysIO User Guide, page 12, under section "7. VCCIO Requirement for I/O Standards": it mentions that an: input buffer set up to be a 1.2 V ratioed input can be used ...
user373900's user avatar
0 votes
1 answer
48 views

Lattice MachXO3LF FPGA Internal Clock Accuracy

On the data sheet for the Lattice MachXO3 FPGA family, it shows that the internal oscillator has varying nominal frequencies with +/- 5% accuracy. Does this apply to its entire temperature range ...
user373900's user avatar
0 votes
2 answers
77 views

Defined delay of an asynchronous signal in an FPGA

What's the proper approach to delay a signal which is routed asynchronously from an input to an output pin on an FPGA? The required delay is approximately 5ns and therefore too small to do it ...
po.pe's user avatar
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Simulating a noisy sine wave

I'm trying to simulate a sine wave with white Gaussian noise on my test bench. I have generated 40 values for this signal following @vipin's blog post here and integrated this module into my test ...
nisak's user avatar
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1 answer
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Alignment characters in the JESD204B standard

I have a question regarding the alignment characters in the JESD204B data converter interface protocol. To anyone who is familiar with this protocol. There are certain alignment that are used during ...
fisherman's user avatar
2 votes
1 answer
79 views

Divider Generator handshake is not working

I'm a beginner in FPGA programming and I'm trying to implement a noise filter in Verilog on Vivado. I'm doing calculations on the input signal where division is needed, so I'm using the Divider ...
nisak's user avatar
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1 answer
108 views

Why does multiplication give 1 even though inputs are not 1? [closed]

When I'm doing multiplication inside an always block for my variables K_next_num and ...
user25028310's user avatar
-1 votes
1 answer
42 views

Why does Divider Generator output an unknown x?

I'm a beginner in FPGA programming and I'm trying to implement a noise filter in Verilog on Vivado. I'm doing calculations on the input signal where division is needed, so I'm using the Divider ...
user25028310's user avatar
0 votes
0 answers
33 views

How to fix erased On-Board Usb-Blaster FPGA (MAX II EPM240T100C3 on board Terasic DE10-Lite)

I have Terasic DE10-Lite board (with Altera MAX10 fpga), which use Altera Max II EPM240T100C3N (and usb-b + ftdi chip) for on-board usb-blaster logic. After explore 8 pins jtag holes on the board, i ...
Lion's user avatar
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1 vote
0 answers
92 views

How to view raw image of Image Sensor like OV5640?

I'm using the OV5640 image sensor with an FPGA in JPEG mode with 720p 30 fps. Currently, I can send images via Ethernet and view them on my PC. Now, I want to capture raw RGB images directly from the ...
optiplex91's user avatar
-3 votes
1 answer
107 views

Whats the error?

I'm trying to make a counter but Vivado display an error, and I cannot see what's the problem. As far as I know the design is correct. Someone can tell if I'm missing something, please.
A. V.'s user avatar
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0 votes
1 answer
120 views

How to correctly write and read to/from SRAM on FPGA with VHDL?

I want to write 512KByte data on SRAM(IS61/64WV512).I'm using spartan6 lx9 FPGA. In the program routine, the initial step involves writing all the data. Subsequently, upon completion of the writing ...
MH.AI.eAgLe's user avatar
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0 answers
132 views

Can't solve this Vivado synthesis problem - Any help?

I have a fairly complex design that has been verified on ILA debugger and put together as an IP and it appears to work perfectly. The design is running on a Virtex-7 VC709 FPGA board. It does have a ...
David777's user avatar
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0 votes
1 answer
89 views

How to flash Altera EPM7256E?

I am working on legacy bit of hardware. I see that EPM7256S can be flashed as usual, via JTAG using standard (modern) tools, so this is quite clear. But how to flash EPM7256E? Are the any inexpensive ...
BarsMonster's user avatar
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70 views

DSP VS FPGA for Power electronics Solar inverters

I need some help regarding the use of an FPGA or DSP for the control loop of the three-phase solar inverter. I want to implement a digital feedback system (as shown below) instead of analog and ...
kam1212's user avatar
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-1 votes
2 answers
52 views

What are easic?

I just stumbled on this eASIC AdvantageOptimize your custom eASIC solution for power, performance and fast time-to-deployment. Obtain ASIC level performance whether your application is logic, DSP or ...
user2284570's user avatar
0 votes
2 answers
123 views

FPGA arithmetic implementation

How does an FPGA synthesis tool decide how to implement arithmetic operations on the target hardware? For example, if I implement some integer multiplication and division operations directly in HDL ...
b7031719's user avatar
0 votes
0 answers
49 views

Quartus: too long compilation time problem - Stratix 10

I have a big design the suffering from very long compilation times, The time is about 7hours to 8hours. I would like to know if its normal according to the following details: FPGA Device: Intel ...
Michael Rahav's user avatar
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0 answers
70 views
+50

DisplayPort video into a Cyclone V FPGA

I designed a carrier board that has a Type6 COME module that outputs DisplayPort 2.1 to a Altera 5CGXFC7D6F27I7N Cyclone V FPGA. The FPGA firmware contains DisplayPort IP. I am having problems getting ...
miggyEE's user avatar
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3 votes
1 answer
114 views

Reset issue while issuing commands to SD card

I am busy with a project where I'm trying to make a custom flashcard for the Gameboy (for more details, refer to https://efacdev.nl/projects/ecgc). For the flashcard, I am trying to load games from an ...
elialm's user avatar
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0 votes
3 answers
53 views

When does the tRAMP timing begin for Cyclone 5 Power Supplies?

I am currently designing a power supply setup for a Cyclone 5 FPGA. In the datasheet, it is stated that if power supplies do not reach operating conditions within the maximum tRAMP time allowed (100ms ...
DownInFlames's user avatar
1 vote
2 answers
52 views

Do I need a buck IC to get 3.3 V, or a buck/boost, or an LDO?

The voltage supply of my FPGA and sensors circuit is 3.3 V. If I use a Li-po battery with 3.7 V nominal voltage and 3 V discharge cut-off voltage (the LP-803860 3.7 V, 2000 mAh with PCM), do I need a ...
NihelKh's user avatar
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0 votes
1 answer
60 views

Is it possible to use registers on Intel‑based FPGAs ? If not what’s the alternative for solving the bandwidth issue?

In order to bruteforce a key where the first private’s key bytes are known (leaving 270 possible private key to search) I’d like to do the following: pick up a 64‑bit private key range split that ...
user2284570's user avatar
1 vote
0 answers
185 views

FPGA DDR timing constraints

I have EMMC master for FPGA. Please tell me how to write constraints on ports in DDR mode? I tried to write constraints but I doubt the correctness Specification: JEDEC Standard No. 84-B51 P.S. Here ...
strontiuman's user avatar
0 votes
1 answer
119 views

Xilinx Virtex-7 VC709 FPGA Clock Setup Problem

I am getting started with the Virtex VC709 FPGA board, moving on from a much simpler Digilent FPGA development board. I get critical warnings trying to configure a single ended 100MHz clock from the ...
David777's user avatar
  • 1,555
-1 votes
1 answer
60 views

canonical way to set a reset line at startup in verilog [closed]

(Total noob at FPGA) For real hardware not simulation. I want to assert a global reset / clear signal on the first n clock cycles (maybe just 1)
pm100's user avatar
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