Questions tagged [fpga]
A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".
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When is proper to use <= or = assigments in Verilog
I have not clear at all this part of Verilog when using <= or when =
I have some always blocks that make some adds, subtracts and multiplies an example is like this:
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38 views
Verilog Case Statement evaluating all combinations of a 10-bit ADC sample
I have a (hopefully) pretty easy question on case statements. If I am sampling an incoming signal, which is returned as a 10-bit value, can I evaluate that sample in a case statement and assign a ...
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Verilog - Does a register retain its current value if not explicitly told to do so?
Consider this code:
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Why is there a need for an eNVM and an eSRAM in the same SoC FPGA
SmartFusion2 SoC FPGA is distinguished by containing an embedded Non-Volatile-Memory (eNVM) that is used to store the code needed for the booting process of the FPGA after power up. So in the presence ...
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SPI interface on Xilinx FPGA, clock domains and timing constraints
I am interfacing a Raspberry Pi board to a dev board with a Spartan 6. I want to do this using SPI. Because of the way the dev board is designed, I need to connect SPI CLK and DATA to standard IO pins....
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89 views
How does a CPU interface with GPIO pins?
I am trying to implement a simple mips1 clone in Verilog at the moment, works all fine in simulators but I also want to run it on an actual FPGA.
Basically I would like to send/receive characters to ...
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77 views
What makes Smartfusion2 FPGA clamed as highly secure to ensure secure booting?
Is the FPGA Smatfusion2 claimed to be highly secure by its manufacturer (Microsemi, now Mircochip) because it is a non volatile memory FPGA? Meanwhile the SRAM FPGA like the zynq 7000 are considered ...
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How to use an FPGA on your own PCB
I have been playing alot with FPGAs (or so I thought). I have always been dealing with different evaluation boards etc. which is very handy; you plug in the USB cable, use the development tool and the ...
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Unsused bits on a DDR3 chip
I have 2 DDR3 x16 chips (MT41K256M16xx) interfaced with an FPGA (M2S150TS-1FCS536). I plan on using point to point Data & fly by Address/command topologies.
I'm using ECC with a 16 bits bus, so ...
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49 views
Bus arbiter that can handle multiple concurrent requests vhdl
I am working through a weird problem. We are pin constrained on our FPGA and need to control a common bus. This was all fine and good as all the software was sequential, but now some requests will be ...
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63 views
Cross GNU ARM Toolchain
As a beginner, I am confused with setting the adequate toolchain (the whole concept in new for me). My goal is to program the ARM Cortex-A9 on the board Zynq 7000 using the Xilinx SDK.
In order to ...
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43 views
Pipelined vs Low Latency implementation of cube of a number in Verilog
I was studying about FPGA design and then came across this terms Throughput and Latency. So the author provided an example of a ...
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43 views
Including one module in another module with variable
I need to implement this code to synthesize and do so that xor21 and and21 will work separately.
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79 views
how slow are modelsim free licences?
I know in free licenses of modelsim / questa simulations run slower than the full version.
But how slow? will it be 2x 3x 10x faster in the paid version?
what about actel/microsemi free version ?
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73 views
Unable to figure out VGA [Verilog]
After doing plenty of research on how to generate VGA signals and looking at a few code examples, I attempted to write my a simple VGA signal generator that just displays a single solid color on the ...
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57 views
How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?
I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
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Are floating point numbers denormalised before the processor performs arithmetic operations on them? [on hold]
Does the processor denormalise the numbers in IEEE 754 notation and normalise the result after storing or are the arithmetic operations performed on the numbers as they are?
I'm asking because in case ...
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51 views
How can I connect a USB keyboard to a DE1-SoC?
I recently got a DE1-SoC development board from Intel and I wanted to use it to instantiate a computer design I created while following along the Nand2Tetris course on Coursera. Unfortunately, this ...
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FPGA vs Microcontroller for DVB-T decoding
For an upcoming project, would it be easier to implement a dedicated microcontroller or purchase IP for an FPGA for decoding an MPEG-2 video data stream from a DVB-T demodulator?
Overall the project ...
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3answers
89 views
How does the AXI-Interconnect know where to route the data?
Im interested in where exactly the Addresses (BASE_ADDR) set in the "Address Editor" of a Vivado Block Design come into play in the FPGA-Part. I have multiple Blocks with AXI-Lite connected to a Zynq ...
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83 views
vhdl “wait until” in a loop
I get an error message "Error (10398): VHDL Process Statement error: Process Statement must contain only one Wait Statement" for this code
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Need help understanding an universal pin driver schematic
I was studying a schematic of an universal 48-pin device programmer, and while most of it seems pretty straightforward to me, I have trouble understanding the reasons behind some of the decisions made ...
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Why is there a system controller and a microcontroller in the same FPGA?
I am starting to dig into the FPGA world. While exploring the FPGA SmartFusion2 architecture I found out that there is a microcontroller (ARM Cortex-M3) and at the same time a system controller. Why ...
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67 views
Multiple ADC's interfacing to FPGA [closed]
I am looking for a 32-channel ADC (24-bit resolution) which can simultaneously sample all the signals. But I could find only 8-channel ADC with the above requirements.
So, is it possible that I can ...
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Passing data to 48 Independant SPI slaves
48 separate SPI busses that can run at 30 MHz... but I probably only need 100 Khz, since I just need them to update at a rate of 1Khz... However! I would like to have them run as fast as possible.
I ...
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56 views
Assigning specific bits of vector to outputs in verilog ucf
When I set up my module, I have code like
input signed [7:0] SIGNAL
but in the UCF I want to assign each bit individually. Currently my code in the UCF looks ...
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91 views
Modbus RTU for FPGA
I need to implement Modbus RTU in FPGA (Cyclone 3). Basically I see two ways to do that. The first one is to hardcode it in VHDL and it doesn't seem to be that hard at the begining. But I have looked ...
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34 views
How to turn on LED with PMOD on FPGA
I have a 12 pin PMOD interface on my Nandland Goboard FPGA and I would like to turn on an external LED with it.
I can do it on my using pins 5 and 6 which are GND and VCC but I can't figure out how ...
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47 views
Possible test patterns produced by ATPG Software like Tetramax
I am developing a pattern generator in VHDL for testing ICs. The problem is I need to make it as universal as possible and need to consider a few factors such as output rate, binary or tristate etc. I ...
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43 views
Adding to a sum variable produces a “reals can't be synthesized” error in verilog
First, a disclaimer that this is my first time using verilog and I don't really know anything. My code is as follows:
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how to resolve large combinational logic delay?
I am new to systemverilog. Recently I am working on a project for decoding a data stream from a AVALON_ST. Using systemverilog. My target device is Stratix V and the clock is 200Mz.
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41 views
How to determine phase shift for clock being generated for SDRAM connected to FPGA?
In the reference designs for a few FPGA development boards, I have observed that, there is always a PLL which generates two clocks at the same frequency but not in phase. One clock feeds to the SDRAM ...
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67 views
How to constrain a clock signal out from a multiplexer
How would you constrain this design?
ext_clk and clk_in are asynchronous to each other.
clk_div is derived by clk_in with double period.
clk_out may be driven by either clk_in and ext_clk, ...
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71 views
How does FPGA knows the configuraton file is present in Flash memory during bootup?
Which areas in flash memory are scanned during bootup to make sure that there is configuration file present in the external flash memory?
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75 views
Possible issue with vivado synthesis encoding state machines
I have been working on using the ethernet phy on my Nexys4 DDR for the last few weeks. Over the last few days I have been particularly frustrated with one issue I was having with my rx module. I have ...
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93 views
What's the best internal SoC bus?
As far as I know there are two major buses - AMBA/AXI and Wishbone. While AMBA/AXI has proven itself in almost every ARM chip, I didn't find some numbers for Wishbone. Are there any benchmarks or real ...
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62 views
Problem FIFO in the implementation (VHDL)
I was working in that for the past five days and I don't know what happened. I must implement a FIFO to send some information, I attach the FIFO that I use. As you can see in the code, this FIFO using ...
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verilog code for bitlength operation
What is the Verilog code for bitlength operation. Example: If Y=45897, I need BitLength(Y)=16. verilog code for BitLength(Y) is ? Please help me to write this.
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103 views
Can I use I2C protocol for product with SPI interface ICs?
I am working on FPGA project where I have to configure the onboard ICs with SPI interface specified in their datasheets and few with the I2C interface. I was wondering that, is it possible to bring ...
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1answer
58 views
Is there a way to store matrices in an FPGA?
I just finished a Coursera course on hardware design (nand2tetris) and I want to take the next step and implement the design in an FPGA. Being fairly new to the hardware aspect of computing in general,...
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62 views
FSM was struck between two states only!
I'm writing an fsm which is struck between s1 and s2 and not going to next state. Even if I increase the delay after s3 ( for it to complete operation). I even observed the simulation that the data ...
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1answer
103 views
VHDL Error 10481 : no primary unit
I'm designing a circuit using Simulink to VHDL generator to be burned into a FPGA.
Simulink model works fine on Simulink, however, when I try to compile the VHDL code using Quartus II I get the ...
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How to properly constrain ethernet phy
I am trying to use the ethernet PHY on my Nexys4-DDR. The manual for the phy gives the following timing constraints for the RMII ports.
I am getting confused as to what exactly the constraints for ...
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37 views
Propper way to configure and implement a XADC via DRP for an Arty Z7-10 FPGA with three active channels
I have been working on a project that requires the use of three XADC channels, preferably one true differential with approximately 50ksps and two 1 sps single-ended channels (e.g. Vp/Vn, A0, A1). ...
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62 views
signal generator and clock synchronization with FPGA
I am just a beginner in electronics, so please bear with me.
I am using a signal generator to get two channel output which are then fed to a FPGA based Mojo. The mojo is then connected to a computer ...
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FPGA NIOS II and RS-485
I am doing my first steps in designing an FPGA project with NIOS and RS-485 interface. I have looked through a bunch of tutorials and books, but haven't found useful info about how to add RS-485 ...
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58 views
Verilog intermediate bit precision
I currently have the following verilog expression...
wire [15:0] address_delta = (rx_address_in * 8 + (rx_eof_in ? rx_len_in : 8)) - (seek_address + OUT_BYTES);
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120 views
Initial Block is Sythesizable!
I came across a lot of posts saying that initial block is not synthesizable in Verilog HDL.Even I followed the standard reference (https://link.springer.com/content/pdf/bbm%3A978-81-322-2791-5%2F1.pdf)...
