Newest 'fpga' Questions

0 votes

0 answers

18 views

IS42S16320F-7TL, reset SDRAM from any state without shutting down

I'm trying to make a SDRAM interface for a IS42S16320F-7TL on a FPGA. I'm confused about the reset process for the device after it has been set once already. I understand there is an initialization ...

NRagot

37

asked yesterday

4 votes

3 answers

786 views

Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?

I have a module that takes in a sample, puts it in a large buffer, and sums the buffer. When it synthesizes, Quartus says it requires too many combinational nodes. I tried many things to see what ...

fpga verilog quartus

user2704336

51

asked 2 days ago

0 votes

0 answers

55 views

Verilog state machine, state does not change [closed]

Below is my code in which i want to shift the data serially out from the FPGA in state "transfer". However when I simulate it, the state does not update. It is stuck in "update state.&...

fpga verilog system-verilog

adeel ali

1

asked 2 days ago

-1 votes

0 answers

71 views

FPGA: issues with synthesis and implementation of quad SPI flash controller

I have written a state machine to act as a quad SPI controller for W25Q128JV Serial NOR flash ICs from Winbond. I tested the design in simulation and the waveform looks as expected based on the ...

fpga verilog xilinx vivado tri-state

OM222O

180

asked May 15 at 4:16

1 vote

1 answer

75 views

Array Sum Not Synthesizing

I'm writing a FIR filter in Verilog, but the circuit does not synthesize. I've tried many different things, but ultimately it doesn't seem to want to synthesize the sum of an array. I have tried ...

fpga verilog fir

user2704336

51

asked May 14 at 16:57

0 votes

1 answer

31 views

Change clock frequency from 50MHz to 40MHz using Altera Cyclone IV and Quartus Lite 20.1

I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating ...

fpga frequency intel-fpga quartus cyclone

Yury Euceda

1

asked May 13 at 0:53

0 votes

0 answers

30 views

Suddenly Error (209040): Can't access JTAG chain

I have a board with a 10M04SCE144 FPGA which I have been using for more than a year now. I am using an Altera USB-Blaster II, also for more than a year. I am programming the device using Quartus Lite ...

fpga intel-fpga jtag quartus

user171780

430

asked May 10 at 12:10

0 votes

0 answers

33 views

What causes voltage drop when powering both 8-relay module and DE-10 Nano simultaneously using 5V and 0.84 Amps through a power supply?

I have a robot that have uses DE-10 nano fpga board stacked on top of another pcb board that acts as power distributor to other components such as linear actuator brakes, wheel brakes, spray gun, etc ...

power-supply power relay fpga module

Total-Lecture-9423

1

asked May 9 at 8:33

-1 votes

0 answers

29 views

SystemVerilog indexing issue: Erroneous design and duplicated register/latch removal in Lattice Diamond

I use Lattice Diamond (Linux, 64-bit, Version 3.12.1.454) with Lattice Synthesis Engine (LSE) in SystemVerilog-mode, with a Verilog-only design (not mixed). I was indexing a reg in Lattice Diamond the ...

fpga verilog lattice

bluesceada

9

asked May 9 at 7:26

0 votes

1 answer

27 views

Conditional compilation of Verilog based on parameters

I have created a SPI controller in Verilog and I want to support all 4 SPI modes (clock phase and polarity options). It's easy enough to do this by changing the always block to be posedge or negedge ...

fpga verilog vivado

OM222O

180

asked May 9 at 1:49

3 votes

1 answer

399 views

ADC clock and sampling rate using FPGA

I'm using an FPGA to drive an ADC, let's say AD9226, 12-bit resolution, and 65 MSPS sample rate. I can drive it with a 50 MHz clock - from my understanding, that will give me a 50 MSPS sample rate. ...

fpga adc

Jason Shan

31

asked May 6 at 3:44

0 votes

0 answers

37 views

How Connect XAUI-Core to PC

I want to connect somehow my XAUI -core(xilinx) -> [PHY] to my pc I check my XAUI core with ILA Debugger I have A7 GTP The board wiring is not that easy, I want to focus on XAUI TX first. That ...

fpga

pgapga

13

asked May 5 at 8:18

0 votes

1 answer

67 views

When should we switch from an internal FPGA oscillator to an external one?

I'm about to design a 5Mbps UART on a ICE40U0-5k and I've got a hunch I'll need an external oscillator when I spin my own board after I'm done with the dev board, but I would like to know how I can ...

digital-logic fpga oscillator clock crystal

user42875

1,080

asked May 3 at 15:16

0 votes

1 answer

116 views

STA timing closure for asynchronous FIFO

I have implemented an asynchronous FIFO However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees. Both read_clk and ...

fpga timing-analysis fifo asynchronous

kevin

508

asked May 3 at 7:20

1 vote

1 answer

88 views

>1Mbps UART core on Lattice's ICE40UP-5k FPGA?

I need a UART core able to receive in the ~4-5Mbauds range (the transmitter is able to transmit up to 30Mbauds, over RS422 upstream of the FPGA), but Lattice's 16550 IP core only allows me to ...

fpga uart digital-communications core

user42875

1,080

asked May 2 at 23:49

2 votes

1 answer

73 views

Correct way of estimating delays in FPGAs

What is the correct way of estimating delays when doing operations in Verilog? For example: reg [31:0] a, b; ... wire [31:0] res; assing res = a + b; The above <...

digital-logic circuit-design fpga verilog delay

Martel

913

asked Apr 28 at 12:48

2 votes

1 answer

48 views

VERILOG: why Xilinx AXI Slave declares all output signal as a wires and not reg?

I am reading the code for an AXI Slave provided by Xilinx (here below). I am wondering why they declare all outputs as wire and then assign them to an internal ...

fpga verilog output axi

leopicchio

63

asked Apr 28 at 8:36

0 votes

1 answer

68 views

What are the possible strategies to transfer data from an FPGA accelerator to a hard-core CPU? [closed]

I am beginning with FPGAs and I am working on an accelerator that acquires data from a microphone (Pulse Density Modulation) and extracts a single frequency from the signal. My accelerator is ...

fpga fifo data-transfer

leopicchio

63

asked Apr 26 at 8:58

-1 votes

0 answers

53 views

Finding primes using VHDL state machine

FPGA has become a hobby for me in the last year, meaning I am not much of an expert. Today I show you a code to find the number of primes larger than 1 and lower than a limit: ...

fpga vhdl hdl

emma97

46

asked Apr 24 at 17:27

0 votes

0 answers

108 views

Deserializing NRZ-encoded high-speed serial data

I need to design a USB interface using an FX3 SuperSpeed Explorer Kit (CYUSB3KIT-003) to get a data stream to a PC. Coming in there is a high-speed serial data line with non-polar Non-return-to-zero (...

fpga level-shifting high-speed programmable-logic deserialiser

Fivefold

1

asked Apr 24 at 9:25

-1 votes

0 answers

27 views

How to control write and read data beween SPI slave and wishbone master

I am trying to build a core that includes spi_slave wishbone_master. Now, I am able to read or write data between SPI and wishbone, but I don't know how to do both of them. The SPI is sending and ...

fpga vhdl spi serial-bus

Taha Alars

1

asked Apr 22 at 13:53

0 votes

0 answers

26 views

Quartus IOB Register Packing

I am trying to force Quartus to use a Fast Input Register on an input to my design using the Fast Input Register assignment. However, when I build my project I get the following warnings: ...

fpga intel-fpga quartus

Vance

813

asked Apr 20 at 13:44

3 votes

1 answer

252 views

What does the circle with the “X” and the cross mean?

I am taking a look at a DSP block for a the Xilinx ZCU111 FPGA and I am getting held up on a simple question. I come from physics so I am not too used to looking at block diagrams yet, but what do the ...

microcontroller fpga adc dsp diagram

mintl

33

asked Apr 18 at 15:22

-1 votes

0 answers

59 views

How do I implement half wave symmetry for sine wave generation in Verilog?

I want to generate a sine wave using a look-up table of 1024 points. If I use half-wave symmetry, I only need 512 points in the LUT. I tried implementing this using Verilog but the output is not ...

fpga verilog sine

eldenlord9394

39

asked Apr 15 at 9:40

1 vote

1 answer

78 views

iCE40LP1K FPGA - Performing an analog to digital function (Power monitoring) without an ADC

I'm using iCE40LP1K FPGA and I wanted to create a block that is responsible for doing a fast power down of all devices on the platform when the 12V is shut down due to powercut. Whcih means, when 12V ...

digital-logic pcb-design analog fpga embedded

Xhero39

533

asked Apr 14 at 11:30

0 votes

2 answers

97 views

Lattice Diamond - trying to pipeline but tool is fighting me

I am trying to pipeline a 1-bit signal that has to travel pretty far across the chip (an ECP5 FPGA). The software is Lattice Diamond. The Verilog looks like this: ...

fpga verilog system-verilog

Colin Marcus

465

asked Apr 13 at 22:42

-1 votes

1 answer

53 views

Verilog: Can I chain nonblocking assignments?

I'm trying to find the most human-readable way to pipeline some logic in system verilog. Most of my delays are routing delays. Is it valid to write something like this? ...

fpga verilog system-verilog

Colin Marcus

465

asked Apr 13 at 18:28

1 vote

0 answers

44 views

VHDL - using PORT MAP with FOR LOOP?

Just touching base on one thing. My group and I are making a stopwatch with a lap function for our final project. For the lap function we are using a ROM along with three 32-bit subtractors, which use ...

fpga vhdl adder

Ryan Paye

13

asked Apr 13 at 3:38

1 vote

0 answers

74 views

Amplitude modulation on FPGA

I'm trying to implement amplitude modulation on a Xilinx Vivado using Verilog HDL, but can't seem to get the proper output. Can anyone point out what I am doing wrong? This is in reference to my last ...

digital-logic fpga verilog

eldenlord9394

39

asked Apr 11 at 8:08

2 votes

1 answer

60 views

ISE Design Suite simulation problem

I am new in Verilog language. I am trying to understand the basics. There is this question where the input is a 6-bit number named IN and the output is a 1-bit ...

fpga verilog xilinx ise

Kalamakra

173

asked Apr 9 at 19:35

0 votes

0 answers

42 views

How do I configure the DDR controller in an FPGA?

I am a beginner with FPGAs and I am trying to run a 'Hello world' project on a Zynq Ultrascale+ SoC (my SoC is the ZU3EG). The ZU3EG is mounted on a development-board which contains the following ...

fpga memory vivado controller ddr

leopicchio

63

asked Apr 8 at 15:15

0 votes

0 answers

13 views

Microsemi FPGA Post-Layout Simulation know-hows

I currently want to simulate a big design in the Microchip ProASIC3E FPGA which contains full usage of internal SRAM memory and numerous counters in logic cells. The design is clocked at 40MHz and has ...

fpga simulation modelsim microsemi-fpga emulator

abunickabhi

353

asked Apr 8 at 5:35

1 vote

1 answer

53 views

create_generated_clock quartus for derived clock

I am working in a design that creates a 1Hz clock from 20MHz PLL out. For that purpose, I have created a counter that switches its out when its value arrives to 10 000 000. That 1Hz clock is used as ...

digital-logic fpga intel-fpga timing-analysis sdc

mugurumov

41

asked Apr 7 at 11:32

0 votes

1 answer

70 views

GTP change connections: Cannot set LOC property

I have a PHY-CHIP with XAUI Interface connected to a A7-FPGA-CHIP(GTP). My schematics say I should reconfigure the "polarity and order" of my incoming and outgoing xaui - GTP Pins. Here an ...

fpga

pgapga

13

asked Apr 6 at 9:28

1 vote

1 answer

81 views

Minimum FPGA clock frequency

I currently work with two FPGAs, Microchip/Microsemi ProASIC3E and AMD/Xilinx Zynq-7020. In their datasheets, the recommended minimum operating frequency is 1.5 MHz for the A3PE ProASIC3E chip. The ...

fpga xilinx clock-speed microsemi-fpga

abunickabhi

353

asked Apr 6 at 6:40

0 votes

0 answers

21 views

Lattice ECP5UM5G: receiving TMDS signal with the FGPA tranceivers

I'm trying to implement a DVI/HDMI receiver in the Lattice ECP5UM5G FPGA. This FPGA has four 5 Gb/s transceivers, that seems to be more than enough for high-resolution HDMI video. Unfortunately, the ...

fpga pll hdmi lattice clock-recovery

firegurafiku

247

asked Apr 5 at 1:48

0 votes

0 answers

54 views

Non-Uniformity Correction NUC system ZYNQ FPGA

I am trying to implement the scene-based non-uniformity correction NUC of Infrared Focal Plane Array on ZC706 Evaluation Kit. I understand the algorithm and what should I do, but I don't really ...

fpga embedded video imageprocessing zynq

Max

1

asked Apr 3 at 6:20

2 votes

1 answer

55 views

Xilinx FPGA decoupling cap layout (traces and vias)

I have the decoupling capacitors located close to sparatan 7 (<2000 mil). I'm trying to route these and connect it to the BGA pin. According to xilinx UG393, I shouldn't use same vias. PCB layout ...

pcb-design fpga xilinx layout decoupling-capacitor

Manny

31

asked Mar 31 at 17:56

2 votes

2 answers

68 views

How to use case for continuous assignment?

I get a bunch of these errors on the following code: (VERI-1100) procedural assignment to a non-register 'nextstate' is not permitted The problem is mostly with the ...

fpga system-verilog

Colin Marcus

465

asked Mar 28 at 18:19

0 votes

1 answer

70 views

Interface a CML device with FPGA

I want to interface an IC with an FPGA however I noticed that the datasheet says the digital control inputs are differential and CML standard based. Can someone please guide how to interface this if I ...

fpga interface standard lvds

malik12

123

asked Mar 24 at 11:58

1 vote

1 answer

51 views

Intel FPGA: Source-synchronous input using PHY Lite

I have been trying for several months to get hold of information about how to use an Intel PHY Lite IP (for Arria 10 or Cyclone 10 GX) to implement a source-synchronous input interface: Last December,...

fpga intel-fpga synchronous

Harry

187

asked Mar 23 at 7:20

2 votes

1 answer

124 views

FPGA: Verilog synthesis and Simulation - Open Source Appoach

I've been taking an CS Engineering Course where I've chosen minors in Electrical engineering. I'm a total noob here and no idea what's basically going in chip/FPGA Design process. I wished to ask if ...

digital-logic fpga verilog simulation open-source

Abhas Kumar Sinha

121

asked Mar 22 at 4:50

0 votes

1 answer

105 views

Microchip FPGA Internal Short Circuit

We are using the FPGA ProASIC3E A3PE1500-PQ208. The FPGA got internally short circuited during runtime. The FPGA IO Supply Voltage and FPGA ground are permanently short circuited and it is not ...

fpga microchip floating microsemi-fpga

abunickabhi

353

asked Mar 21 at 11:31

3 votes

2 answers

562 views

Waveform generation on FPGA

Can anyone give me an idea on how to generate this RF waveform on FPGA? I already have the I(cos) and Q(sin) signals generated just need a guide to produce this weird shaped pulse. Edit: This is the ...

digital-logic fpga waveform

eldenlord9394

39

asked Mar 21 at 5:20

0 votes

2 answers

99 views

Checking the signal frequency in FPGA

in a VHDL project where the master clock is 50 MHz, how to check if a signal is 10 MHz or 20 MHz? I have an external device where the default is 10 MHz. I am adjusting its settings via serial port and ...

fpga clock

bLAZ

121

asked Mar 18 at 14:02

0 votes

1 answer

71 views

Help understanding FPGA dimensions

I need some help understanding the dimensions specified in the datasheet of an FPGA. I am trying to figure out the pad/ball dimensions. From looking at the schematic, it looks like theta_b is the ...

pcb fpga datasheet

bchang32

93

asked Mar 17 at 12:48

0 votes

0 answers

38 views

How can I modifiy this Terasic Highspeed AD/DA FPGA thdb-ada card to use the full voltage range?

I have this FPGA daughter card and I want to modify it so I can capture frequencies from DC up to 1MHz. This usually isn't possible as the front-end of the card uses RF transformers with an ...

fpga adc intel-fpga

ChrisD91

561

asked Mar 16 at 12:31

0 votes

1 answer

49 views

Accessing data from a ddr3

I'am working on a new projet where I'm willing to access data from a ram, but the ram's specs is that they work with a frequency up to 667MHz , so I decided to choose an FPGA to work as controller ...

fpga ram ddr3 data-acquisition

nedved simao

1

asked Mar 15 at 14:31

2 votes

2 answers

366 views

Career change: from embedded firmware to FPGA design?

Appologies this isn't really EE question, only related..Don't know though a better forum to ask this on. I've been in embedded firmware engineering for years now, programming CPUs,SoCs,MCUs, etc.. ...

fpga

v01d

47

asked Mar 11 at 3:24

0 votes

1 answer

79 views

Carry bypass adder delay higher than expected with timing analysis

Good evening all! I am facing an unexpected behaviour of the timing analysis of my bypass (or skip) carry adder. In particular, the implementation of the adder looks correct to me, the Modelsim ...

digital-logic fpga vhdl adder timing-analysis

Revo

1

asked Mar 10 at 20:40

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