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Questions tagged [fpga]

A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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Meeting Setup/Hold Time according to time analysis

I am trying to interface an IC with an FPGA. Both the IC & FPGA run at 66 MHz with no clock skew between them and the propagation delay of the data lines is negligible, since the length of the PCB ...
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31 views

What is wrong with my vga code? [on hold]

This was developed on the DE1-SoC board in system verilog. Some of the redundant code was erased. I have a multidimensional array that determines if a spot is occupied or not and determines the player....
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1answer
86 views

VHDL Delimiter Character

I'm trying to define a string in VHDL with a pair of double quotes in the string itself. However I am unable to do so because the IDE (Xilinx ISE 14.7) only recognizes what's in-between the first pair ...
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1answer
26 views

Lattice LCMXO2-256HC-4SG32C CHECK_SECURITY_PROTECT_KEY error

Trying to progamm LCMXO2-256HC-4SG32C with this ebay progammer. The programmer works fine with LCMX02-1200HC-4TG144C, but with LCMXO2-256HC-4SG32C it gives me the following output: ...
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1answer
36 views

Best way to structure Verilog module to allow for simulation clocks

Quick question that I am likely missing an obvious solution for. I have a relatively simple Verilog design which I'll call taco, where the top-level design entity is taco_top (because I'm writing this ...
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43 views

Unexpected behavior on FPGA [closed]

I hope everyone is having a singular week. The issue is that when I run my VHDL design on hardware I get all kinds of aberrant behavior. The attached screenshots are latest example, notice how in ...
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2answers
71 views

How can I execute multiple for loops sequentially in Verilog?

I'm trying to turn on the LED lights on my FPGA Spartan board one at a time until all lights are on and then turn them off in the reverse order. I could easily do this in other OOP languages by making ...
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34 views

HDL implementation of Numerical Analysis Techniques

I am looking for open-source implementations of Numerical analysis techniques (specifically root-finding techniques like the secant method) on FPGA using any HDL. Would also appreciate if anyone could ...
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1answer
52 views

Can I bridge output IO's from an FPGA that is driving a clock source to drive longer tracks?

Scenario I have a motherboard and a daughterboard that couple through two headers. The motherboard has a 16x16 array of ultrasound speakers each with their own drivers, that works. I drive them ...
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1answer
65 views

How are Vivado's projects directories structured?

I'm working with Vivado to program FPGA's in VHDL. Can someone explain me what are the various directories that are created under the project's directory? In my projects, the following folders are ...
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1answer
29 views

Error with reference to scalar wire 'reset' is not a legal reg or variable lvalue

I'm getting an error in Verilog with an input parameter it's not recognized as a legal reg or a variable lvalue. I had the same problem with the output in the module however it was fixed by labeling ...
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1answer
62 views

Sequence of evaluation in the following non blocking code?

I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...
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1answer
35 views

Driving ADC's CONV input at the falling edge of SCK

Trying to makes sense of the following in this LTC1407 datasheet: It is good practice to drive the LTC1407/LTC1407A CONV input first to avoid digital noise interference during the sample-to-hold ...
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2answers
78 views

How much time does it take to increment one bit in Verilog? [on hold]

In my lab I'm supposed to write a program in Verilog that makes a timer which outputs a tick every second. A counter module could be used such that as the counter increments to a specific binary ...
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2answers
41 views

Place Design error when using if/else statements in verilog

I'm trying to do one of the exercises on the book I'm studying from. The idea is to turn on/off LEDS depending on switches. But I got a place design error when tried to run implementation (synthesis ...
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38 views

Implementation of activation function using Xilinx System Generator

I made this design of the sigmoid activation function: $$f(x)=\frac{1}{(1+e^x)} $$ But the scope displays a saturated curve instead of the positive part of the sigmoid: I don't know where exactly ...
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50 views

Generating a specific sequence of signals in Verilog with timing requirements

I am a beginner in Verilog, and as a part of a project, I have to send a sequence of signals to a chip in order to program one of its parameters. This Verilog code will be synthesized on an FPGA, and ...
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53 views

FPGA configuration time and PCI Express

I'm designing a PCI Express board with an Artix-7 from Xilinx. I'm reading through the PCIe block description and on page 199 it says: Section 6.6 of PCI Express Base Specification, rev 1.1 states “...
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2answers
74 views

What are some good tips for handling PCB design for a spartan-6 LX9 microprocessor implementation? [closed]

My team and i are working on a MIPS implementation using Xilinx spartan-6 LX9. We have a short deadline and we want to know what are some useful tips in terms of PCB design that would reduce the risk ...
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21 views

ILA error on Vivado

The question is very silly and I hope it is not too inappropriate. Configuring any Integrated Logic Analyzer on Vivado, it happens to me that the program does not create appropriate files and ...
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1answer
30 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...
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2answers
40 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...
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104 views

algorithm to implement 48bits unsigned integer division in hardware

R = A / (A + B) < r% (A * 100) / (A + B) < r A and B are 48 bits unsigned integer. A and B are retrieved from hardware onchip memory. r is a 5 bits unsigned integer range from 0 to 31 r is ...
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1answer
77 views

Should FPGA interface an IC using more than one IO bank?

I would like to interface a FPGA with a fairly fast IC. My FPGA is MachXO2-7000HC while the IC in question is FTDI's FT601, which is a USB 3.0 to FIFO bridge. The FT601 has quite a few control/data ...
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1answer
97 views

How to increase memory on the FPGA board?

Situation I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...
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40 views

Appropriate driver amplifier to amplify an FPGA pin voltage for RF applications

I'm trying to built a nanoseconds RF transmitter using an FPGA and an up-converter. However I don't know the correct configuration (I prefer a single IC) in order to drive a nanosecond pulse (pulse ...
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1answer
34 views

Unable to diagnose StX fault in Modelsim

I'm unable to figure out why Modelsim is giving me a StX fault for this testbench. I'm just creating a counter and simulating a device that returns the MSB of the counter. Any help in figuring out ...
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2answers
64 views

What does these Verilog line of code mean?

I'm looking at this code: https://github.com/hgeisse/eco32/blob/dfd24eb13387f16b7da99a2285df023f446a676a/fpga/experiments/de2-115/memctrl-32/sim/memctrl-1/ramctrl/ramctrl.v and I've found two lines ...
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1answer
51 views

Burning bin file to FPGA

I have a bin file which contains 8-bit space seperated binary data and I want to load it in memory. In simulation it works fine, the readmemoryb command loads data in reg memory. Is there any way to ...
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47 views

Create a unique file name inside an entity instantiated multiple times

I have a design instantiating a component many times in different situations. I want to trace some internal behaviours it has using text file output. Here is a snippet example I use in a component ...
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1answer
101 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...
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1answer
84 views

How can I check if an IO pin is dead?

I've been playing around with I2C for a couple days now with a DE10-Nano dev board: I'm implementing an I2C master in CLaSH so that I can talk to the HDMI encoder chip, but for now I'm talking to an ...
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2answers
93 views

Why 4 regs to control a FSM? Verilog

I'm studying an SDRAM controller (in Verilog), which uses 4 reg to control a FSM. I couldn't understand why they use 4 regs instead of 2 (state and next_state). Here's the piece of code: ...
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1answer
51 views

ISE Design suite

im extremely new to ISE design suite. In fact, im waiting for my windows PC to arrive so i can actually download it. But i wanted to ask, if i wrote some VHDL for a full adder logic circuit using 2 ...
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30 views

FPGA VCU108 FMC Clock

For a project at work, we are attempting to create sinusoidal signals ranging up to 2 GHz using DDS implemented on an FPGA and DAC. Our current hardware consists of a VCU108 FPGA board from Xilinx ...
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2answers
484 views

Is it possible to connect a peripheral mouse to the USB side of a USB/UART bridge that is controlled by a CP2103 chip already on an FPGA board? [duplicate]

As the title states I want to connect a USB mouse to the USB port on a USB/UART bridge. I want to determine if it is possible to communicate with the mouse using serial commands on the FPGA board then ...
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1answer
91 views

Hardware design

Is there a way to actually build components on something like Xilinx ISE? i.e. MUX's, NAND's, AND gates. From what I've learned so far, one can only use VHDL to describe hardware and the compilation ...
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1answer
129 views

Why is there no latch in this circuit?

So I have come across this code and when I synthesize it I was surprised that there is no latch. ...
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1answer
28 views

warnings “Xst: 1710 or 1895” in ISE14.7

i have a module, written in verilog, that gives me couple of warnings e.g. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed ...
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1answer
63 views

Prevent design to power up when updating firmware in flash memory

I have an FPGA based design using the MachXO2 by Lattice. I wanted a quick, easy and clean way to perform firmware updates, which are frequent, so I decided to use an external flash memory (AT25SF041 ...
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47 views

Why the resource overhead of a design with new functionality (extra logic) is different on different xilinx fpga devices?

I have designed two circuits with VHDL and synthesized them with Xilinx ISE design suite. The first circuit is a controller (autopilot) and the second circuit is the same controller with extra ...
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1answer
43 views

Value of resistor to protect against short circuit

I have a FPGA and a async-sram with OEn, WEn that I want to interface. To protect against short circuit I want to set resistors on the data lines. What is the value that would protect the FPGA and ...
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4answers
94 views

Types of finites state machine in FPGA design

There are 2 types of FSM: 1- block of combinational logic + clocked block that hold only the current state 2- clocked block For example, if we take a look to how an SDRAM controller is made, most ...
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1answer
425 views

Can I program a platform independent PLL in VHDL?

Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom ...
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2answers
62 views

FPGA: possible to use PC as I/O?

I'm a beginner in FPGAs and I would like to implement a basic CPU with a simple VGA display. If I have a FPGA that has USB-UART could I use my own PC monitor as a display? What about sending input ...
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2answers
86 views

Generate one-input pulse in Verilog

I'm attempting to port discrete schematics into a FPGA. In the schematics some AND gates function as short pulse generators, when input goes low output is enabled, until input propagates down an ...
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1answer
91 views

How do I fix “Nios2 software build tools for eclipse” build errors? [closed]

I have a Quartus Cyclone3 project with NIOS2 processor. I have noticed 3 errors while building the eclipse project, though I am pretty sure it should be working well. Description: make[1]: [public....
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30 views

My JTAG connection with Cyclone IV is not working

My FPGA board is not programming. I think I have followed all the guide lines for JTAG connection. Can you see any problems with this connection?
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0answers
49 views

Iterative CORDIC algorithm dynamic shift optimization

I've implemented the CORDIC algorithm on an FPGA using an iterative approach. The component is loaded with a set of values to calculate and then iterates as many CORDIC steps as necessary for the ...
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1answer
72 views

How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my ...