Questions tagged [fpga]
A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".
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Lattice XP2 — Different voltages for different IO banks?
As the subject indicates: can I use different voltages for the different IO banks? (1.8V for some, 3.3V for some others)
Neither the datasheet nor the hardware checklist technical note explicitly ...
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PN9 PRBS sequence checking
I am working on validating a digital link between an ad(AD9255) converter and an fpga with the PN9 PRBS sequence. The converter sends the PN9 pseudo-random sequence in 14 bit packets on a 14 bit wide ...
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3answers
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Are FPGAs for experimentation alone?
I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
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what is logic power, signal power and clock power in FPGA?
I am measuring power of my design in spartan3e kit. When I use Xpower Analyxer, it shows me some thing like the figure below
I don't know what is clock power, logic power, signals power and IOs power....
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Error: Multiple declarations of unsigned included via multiple use clauses
Below is my code for a RAM 6116 module.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
These are the use clauses I have included.
...
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2answers
961 views
Can the “unknown” turn-on state of registers in digital circuit be used as seed for random number sequence?
We always like to reset registers in a synchronous digital circuit just after power up so they are in a known state before device operation begins.
Pseudo random number sequences make use of a seed ...
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1answer
75 views
How to use LFSR to generate random numbers as per this Xilinx application note?
The Xilinx App note XAPP052 "Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators" shows a method on how to use LFSRs to get random bit sequence of maximum ...
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20 views
Meaning of numbers inside parentheses in Lattice Synthesis Engine Utilization Report?
I'm using Lattice Radiant 2.0 to synthesize a design. In the "Synthesis Utilization Report file", I see the following line:
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4answers
125 views
What features should/must be present inside a prototype FPGA board to aid in debug?
When making any prototype PCB it is always a great idea to have features within it that can be used to aid in debug of the design.
A few examples are:
Use the largest FPGA available that has ...
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1answer
60 views
Pipelined Feedback Summation on FPGA, Verilog
I'm working on a project and I need to write a Pulse Integration block for RADAR project.
To do it I using some kind of buffer and in the first loop insert the data input to it: buffer[0]=din.
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30 views
Most efficient adder structure for adding many terms
What is the most efficient digital adder circuitry for adding up more than three terms?
The question stems from my effort to implement the multiple term addition required for SHA256 on an FPGA in a ...
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1answer
61 views
How would I test if my low pass filter works on a remote FPGA?
I am making an example low pass FIR filter design to go on an Intel FPGA. I have an idea about how I'll test it via simulation (by having the input be a sum of sine waves, and the cutoff frequency be ...
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2answers
66 views
Should I use an asynchronous or synchronous reset?
I am programming a Microsemi M2Gl005 FPGA and wondering which type of reset I should use. I currently have an asynchronous reset implemented, but I wanted to make sure that the part didn't prefer a ...
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1answer
65 views
Help identify this SMD oscillator
This oscillator provides clock to an FPGA which powers the ultrahdmi mod for an N64 (https://www.retrorgb.com/ultrahdmi.html).
It's clearly marked
A03ZZ
1414
Clock output is diametrically opposite pin ...
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0answers
20 views
Lattice Diamond/Reveal throws error with Bitstream File programming
I recently started using Lattice MachX03L device for a project. I have a design and with Reveal I wanted to look at the signals. When I program a JEDEC file into the FPGA I can observe the signals in ...
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Lattice FPGAs — How to control skew on signals routed to IO pins?
Working with:
Lattice XP2-30 or XP2-40
Tentatively a BGA484; almost certainly some BGA 1mm-pitch package
Synplify PRO, with SystemVerilog
Skill level: Beginner / early-intermediate.
If I have a ...
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2answers
91 views
Is it feasible to create computer-like hardware designed to execute a specific algorithm? [closed]
Computers take a set of instructions, and execute them sequentially really really fast.
The number of sets of instructions they could be given is vast. However my rudimentary understanding of ...
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2answers
54 views
Verilog and unchanged output registers?
This is probably an absolute newbie question but what happens to "unchanged" output register as in the following example(pseudocode):
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Mico32 Microcontroller on Lattice ECP3 FPGA
Im trying to design an Ethernet Interface on Lattice ECP3 (versa board),
for this I have to use Lattice built in micro-controller on the ECP3 SOC from Lattice:
I cant find any reference for how to ...
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1answer
78 views
Receive Ethernet data to the FPGA [closed]
I have Lattice ECP3 Versa Evaluation Board.
My objective is to connect Ethernet to the FPGA and be able to receive data (and later to send data) successfully. I don't really care on what protocol I ...
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3answers
547 views
How can a SerDes based link be used to replace the age old UART? [closed]
UART is great to transmit log data from a DUT to a PC. However, it is not fast enough. There are many newer things like USB, PCIe e.t.c that can transfer a lot more data and also use serial transfer. ...
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45 views
AXI4 Pipelining
Given that there is no explicit ordering on AR after R has began transfer, is it possible to initiate a new AR handshake during the transmission of R?
Also, does Xilinx IP support this optimization?
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Will RTOS's be displace by FPGA's? [closed]
Will RTOS's be displace by pure FPGA's because of its performance and flexibility?
Does RTOS's have any advantages besides legacy code?
Will the tasks solved with RTOS be solved with FPGAs without the ...
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1answer
70 views
VGA digitizer with FPGA (input, not output)
Producing a VGA signal with an FPGA has been done by so many people it is a common starter project. What I cannot find is information on how to decode a VGA signal with a FPGA for example to capture a ...
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40 views
Synthesis Verilog Delay (#x), syntax question
I used an IP from Lattice FPGA and looked in their code.
they use this bullets of verilog code there:
...
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1answer
106 views
Loading an FPGA pin at 20MHz in parallel
I'm designing a traction inverter controlled by the NI sbRIO-9627, which includes a Zynq-7020 FPGA. I am considering using a single FPGA pin to drive the external clocks of 14x ADuM7701 isolated ADCs ...
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2answers
76 views
Running VHDL process off an input clock higher than the FPGA clock?
I have the following dev FPGA board:
Altera Cyclone II EP2C5T144 FPGA Dev Board
This FPGA has a 50mhz clock. However I want to interface with an external FTDI device that runs at 60mhz. I am driving ...
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1answer
61 views
What is the purpose of this FPGA + microcontroller based motor driver design?
I have used microcontrollers (Arduino, PIC, Atmel etc) so I am familiar with what they are and what they do (e.g I know about polling, interrupts and communication protocols like I2C, SPI, UART) but I ...
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1answer
72 views
Generating error condition randomly inside a digital design inside FPGA
In order to aid in testing of the design, it is required that we put it into a "debug mode" whereby specific type of error conditions will occur at random intervals. We must then monitor the ...
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5answers
142 views
Debounce circuit design in Verilog
I'm trying to design a de-bouncer circuit , which is widely used in digital design . The module that I'm trying to implement is as shown below :-
I've written the following Verilog Module :-
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16 views
Are there command options for Digilent Adept software?
Recently we started using a Digilent Genesys2 board to emulate our SoC design. To program and control the board, we are using the Adept utility on a Windows 10 PC. This utility allows us to download ...
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1answer
48 views
(7,4) cyclic code encoder in VHDL
I am trying to write code for a cyclic code encoder in VHDL, but not able to visualize how to approach the problem. Right now all I have is an entity and a few diagrams showing my approach as too how ...
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57 views
Timing error in place and route report
I am using ECP5 lattice. I have written the following code to toggle the led.
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1answer
70 views
Can FPGA VGA be used as DAC?
Can a VGA output be used to output an analog signal?
I'm using an FPGA to program and control the VGA output.
I want to use it as a DAC to control an external circuit (I'll be doing PID control). ...
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30 views
Median Filter FPGA [duplicate]
I trying to build on my FPGA project median filter for 1-d vector,
I need my median filter to be large, the Internet is full with references for 9 points median filter but didn't saw anything for ...
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2answers
100 views
Sorting array of 2^x words in real-time
I am presented with the following problem:
I have 256 12-bit words. Each of them are initialized to the same (arbitrary) value. At any given time, a subset of these words will either increase or ...
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27 points median filter
Edit:
I successfully made it work, but the algorithm not efficient
I taking the date coming in to my block, pipeline the data for how much points I need to median filter (for example 31), take all ...
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2answers
58 views
Basys 3 400MHz Logic [duplicate]
The Basys 3 advertises "internal clock speeds exceeding 450 MHz," but the default clock pin is connected to a 100MHz oscillator. Is it possible to configure the Basys 3 to use a 450MHz clock?
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Bit flipped and back on FPGA
I have a weird problem on a Xilinx Ultrascale FPGA (although I think the board shouldn't matter). I have an array called logic[2047:0] enabled which is basically a ...
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33 views
Implementation of Synchro in FPGA
Anyone implemented synchro inside FPGA. I am stuck with theta/angle conversion. I am able to convert 3phase to 2 phase using Scott-T formula. Any help is appreciated.
Thanks
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1answer
112 views
Can FPGAs be emulated?
Can FPGAs be emulated on general purpose computers? As per Church-Turing thesis all Turing machines can be emulated on the universal Turing machine. So if the FPGA can emulate processors, can the ...
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71 views
Inferring a pipelined divider in Verilog
I want to synthesize an integer divider in Verilog to divide 16-bit integers by 8-bit integers. I assume that the compiler will be way more clever than me when it comes to implementing the details of ...
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2answers
130 views
How are LUTs in a FPGA filled?
I know there have been a lot of questions about lookup tables and their design, but even after reading them and scouring the web, I still don't quite understand how the LUTs are filled with ...
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0answers
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HDL code for a wrapper or resizer between AMBA APB bus (32-bit) and the FPGA Fabric design (128-bit variable)
The design is implemented on a System On Chip (SoC)
The processor is Cortex-M3 32-bit which is interfaced to an FPGA fabric where a processing of some variables will take place. The variables are ...
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1answer
67 views
How many multiplexers is too much?
This is a general question. I have a specific task that I am working on. For this task, my solution requires around 300 multiplexers with all of them 16 inputs and 16 bits per input, and a single ...
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1answer
25 views
Synchronous Incomplete Assignment or How is Register Retention achieved
I just realised that Latch creation upon incomplemete assignments only happen in a non clocked enviroment.
So far I have written all my synchronous code unnecessary avoiding incomplete assignments ...
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1answer
40 views
Under-clocking an 10gb Ethernet SFP+ module
The Xilinx device on the Picozed board is a version of the Zynq 7030. The 7030 in general has a GTX transceiver, which in principle is rated to 12.5Gb/s SERDES with the relevant line coding for 10gig ...
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2answers
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I am trying to instantiate few modules to work in top level design, but even though there is no error but I am not getting proper output
This is my verilog code. Though I am not getting any output, if any two of the instantiated modules are commented then I am getting proper partial output(For full output I need all of them to work). ...
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1answer
91 views
Altera FPGA (?) Datasheet
I salved a lot of ICs but this one I couldn't find (and is maybe interesting enough to be play with it, since I never used an FPGA).
It's from a semiconductor chip production machine (high likely) ...
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2answers
68 views
Why do block RAMs have synchronous reading instead of async reading?
I'm programming FPGA boards (Artix 7 to be exact) and I recently noticed that, in order to be synthesized into block RAM, an array of storage must have synchronous reading, otherwise it will only be ...
