Newest 'fpga' Questions

0

votes

0answers

5 views

How do I fix “Nios2 software build tools for eclipse” build errors?

I have a Quartus Cyclone3 project with NIOS2 processor. I have noticed 3 errors while building the eclipse project, though I am pretty sure it should be working well. Description: make[1]: [public....

asked 35 mins ago

RKishmar

25118

0

votes

0answers

18 views

My JTAG connection with Cyclone IV is not working

My FPGA board is not programming. I think I have followed all the guide lines for JTAG connection. Can you see any problems with this connection?

fpga jtag cyclone

asked 14 hours ago

Alpha0

82

0

votes

0answers

31 views

Iterative CORDIC algorithm dynamic shift optimization

I've implemented the CORDIC algorithm on an FPGA using an iterative approach. The component is loaded with a set of values to calculate and then iterates as many CORDIC steps as necessary for the ...

digital-logic fpga cordic

asked yesterday

sebi707

1

2

votes

1answer

51 views

How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my ...

fpga timing-analysis constraints sdc xdc

asked yesterday

SDwarfs

40627

0

votes

1answer

51 views

What's wrong with this schematic for powering up Cyclone IV FPGA?

I have followed all the guide lines for powering up the Cyclone IV. However, the 3.3v Regulator is heating too much and also the Cyclone IV FPGA. What's wrong with my schematic? Is there a problem in ...

fpga intel-fpga cyclone

asked 2 days ago

Alpha0

82

0

votes

0answers

37 views

Strange SDRAM Behaviour

i try to use the SDRAM on my DE0 Board. This is the chip: http://zentel-europe.com/datasheets/A3V64S40GTP_v1.3_Zentel.pdf Basically my driver works. i save the value of an upcounted signal in the ...

fpga vhdl sdram

asked 2 days ago

C. Hediger

405

0

votes

0answers

23 views

problem connecting an Arduino Ethernet Shield to FPGA trough SPI

I have an Arduino Ethernet Shield and trying to connect it to my spartan 6 board. I used the ICSP header on the bottom of Arduino Ethernet Shield (MISO/SCK/RST/+5/MOSI/GND) and a wire for SS(pin 10 of ...

arduino fpga spi ethernet

asked Jan 13 at 6:33

javad

11

-1

votes

1answer

32 views

Two modules and two always statements in one verilog program? [closed]

Our prof gave us a Verilog code and we were tasked to explain how the code works. Despite having previous experience with Verilog coding, i was confused on the code our prof gave. My experience with ...

fpga verilog hdl

asked Jan 12 at 13:02

FlibsiFlub

1

0

votes

1answer

26 views

Verilog - Using 'define' to declare a constant created by a 'parameter'

Pardon the wordiness of the question's title. How would you accomplish the following. I have this parameter: parameter BUS_SIZE = 16; And I want to use it later ...

fpga verilog

asked Jan 11 at 1:15

Jet Blue

495314

0

votes

0answers

77 views

UART RX in VHDL

I have to set up a UART transmitter and receiver using a Spartan 3 board. I've got the transmitter set up already and verified it with the arduino terminal using this FTDI breakout.The receiver is ...

digital-logic fpga vhdl uart level-shifting

asked Jan 10 at 7:14

Simeon R

12611

0

votes

0answers

19 views

Using ALTLVDS_TX megafunction with a DS90CR485 Serializer

Using ALTLVDS_TX megafunction with a DS90CR485 Serializer Hello there, First of all I'm a beginner in FPGA programming and i don't know if my whole approach to this is wrong. I'm currently trying to ...

fpga verilog lvds cyclone

asked Jan 9 at 21:45

CptnBeefheart

11

0

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0answers

28 views

how to send data from ALTERA DE2 to computer? [closed]

hello I am currently using ALTERA DE2 and writing on VHDL . my question is simple lets say I connect ADC(analog to digital convertor ) to the altera . so for exmaple my ADC gives me 8 bits resulation ....

fpga uart

asked Jan 9 at 16:12

Tomer Polski

1

0

votes

1answer

66 views

Fpga communicate to pc through usb

I'm currently working on my thesis project on making a secure pendrive. For that I have to design an USB protocol implementation on an FPGA. But I don't know how to physically connect that USB core ...

usb fpga verilog usb-device usb-host

asked Jan 7 at 16:45

Gourav Saini

1

-1

votes

0answers

26 views

Understanding sequential and interleaved burst modes in SDRAMs

I'm studying SDRAM memories. I have read they have 2 burst modes: sequential and interleaved. I don't understand the differences between them, can you please give an explanation? And, when should I ...

fpga sdram

asked Jan 7 at 15:35

Condor

142

0

votes

0answers

32 views

Quartus Prime: Block synthesized away - why?

Doing my very first steps with FPGA. I successfully built an SPI slave (code found somewhere in the web) that receives something and turns an LED (via output SPI_DONE) on my Altera Max10 evaluation ...

fpga quartus

asked Jan 6 at 14:40

mic

62348

2

votes

0answers

76 views

Creating big MUXes and shift registers on FPGA

I'm working on a guitar tuner project on FPGA. For this I have to pass the sound signal (16bit/1024Hz sampling) from the ADC to a FFT block but I want the FFT block to be clocked with much higher ...

fpga vhdl verilog

asked Jan 4 at 2:17

Cezary

141

4

votes

1answer

77 views

Significance of timing simulation for FPGA

I have started to wonder what is the significance of the timing simulation for FPGAs nowadays. I can easily justify what is the idea behind that by quoting some Xilinx materials: Performing a ...

fpga simulation

asked Jan 3 at 18:17

Al Bundy

454311

1

vote

0answers

28 views

Exporting RAM content to text file in ISim

I'm trying to learn about Xilinx IP cores and FFT implementation on FPGA-s. For that I've created a simple project where I instantiate LogiCore FFT 8.0 core, ROM core and a RAM core. The ROM core ...

fpga vhdl ise

asked Dec 28 '18 at 9:06

rongard

115

0

votes

1answer

46 views

Verilog nested for loop not behaving as expected

I am having trouble with a simulation of an 8-bit full adder i wrote in verilog. Basically I have two integers that I feed into the full adder, I add them together and I check if the result is as ...

digital-logic fpga verilog vivado

asked Dec 24 '18 at 16:26

Jure Vreča

94

2

votes

2answers

122 views

Are there special rules for voltage division of a high speed clock?

High speed signals require special care in PCB layout to prevent high speed effects like ringing and overshoot. This obviously applies to clock signals as well. Provided that one has a high voltage ...

fpga voltage-divider clock high-speed

asked Dec 24 '18 at 11:46

quantum231

3,7521354110

0

votes

0answers

37 views

can't send characters using fpga cyclone iv

I'm trying to connect my FPGA Cylone IV (CoreEP4CE6) with Raspberry Pi 3 for communication through UART. The process (uart_rx) for receiving data is working fine, however, when I place another process ...

fpga uart intel-fpga

asked Dec 20 '18 at 18:54

Alpha0

82

-2

votes

1answer

109 views

UART receiver VHDL

VHDL FPGA UART receiver which receives 10 bits via Bluetooth interface. With 8 7-segment displays. Now my problem is the following In the requirements it is stated that I have to write the solution ...

fpga vhdl uart receiver

asked Dec 20 '18 at 11:04

CircuitBender

11

1

vote

1answer

64 views

Creating a Counter in Verilog for Flashing LED on Lattice Starter Kit

I have a lattic X03LF starter board with 6900C FGPA. There are eight LED available on this board and a push button. The goal of my code is to design a 8 bit counter that increments whenever a button ...

fpga verilog counter lattice

asked Dec 20 '18 at 3:14

JYasir

134

2

votes

2answers

103 views

Problem with adding two counters in series on an FPGA

I am using Verilog in Lattice Diamond IDE with a lattice MachXO2 7000HE breakout board. I built a basic counter with a limit input which generates a variable period clock output. It works fine on its ...

fpga verilog counter series lattice

asked Dec 19 '18 at 8:05

amfast

134

0

votes

1answer

114 views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...

fpga vhdl modelsim testbench questasim

asked Dec 18 '18 at 20:03

rooter

32

1

vote

1answer

104 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...

fpga intel-fpga quartus intel max10

asked Dec 18 '18 at 19:42

quantum231

3,7521354110

1

vote

2answers

88 views

Altera has created EPCS and EPCQ devices, can only these be used to store FPGA configuration data?

FPGA configuration data must be stored in external non-volatile memory. Can we use just any flash memory or only specific types? What about EEPROMs or any other nonvolatile memory device? Edit: I am ...

fpga intel-fpga configuration intel

asked Dec 16 '18 at 17:18

quantum231

3,7521354110

-1

votes

0answers

73 views

FPGA timing for FT601

I am trying to interface and FPGA board with the FT601 usb bridge chip and I am having some issue with the timing constrains. In short, the FT601 has a source-synchronous interface with a ...

fpga timing

asked Dec 14 '18 at 11:33

J.G.

11

-1

votes

1answer

119 views

Fixed-point arithmetic

I want to give two input data of my testbench from a file contains bits(std_logic_victor(15 downto 0) to some arithmetic operartion between fixed point and the files but when it starts I see below ...

fpga vhdl

asked Dec 13 '18 at 9:21

elmakhloufi assaad

14

1

vote

1answer

72 views

Are there CPLD / FPGA toolchains and workflows that bypass vendor IDEs? [duplicate]

Custom programming for FPGA boards is a similar and helpful question for any with the same as this, but they are different. In that thread they discuss custom options and building their own. This ...

fpga hdl programmable-logic ide toolchain

asked Dec 12 '18 at 22:15

Pewsplosions

83

1

vote

1answer

64 views

Clock frequency of FPGA circuit and 4-bit counter [closed]

I have implemented a 4 bit counter using HDL. Now I have downloaded the code to an FPGA kit with a 50 Mhz oscillator. This means that the clock period will be equal to 0.02 microseconds and ...

fpga counter hdl

asked Dec 11 '18 at 21:05

John adams

82

-2

votes

2answers

65 views

7 to 128 decoder in Verilog

I'm new to digital electronics and programming in Verilog particularly. I have programmed some basic programs like 2 to 4 decoder, and 4 to 16 decoder. But I am trying to make an image sensor and say ...

digital-logic fpga verilog decoder vivado

asked Dec 11 '18 at 11:23

1upon0

1

0

votes

1answer

57 views

Xilinx Vivado: How are inputs/outputs handled that are not in the constraints file?

Assume I have the following constraints file which specifies only one single input: ...

fpga vhdl xilinx

asked Dec 10 '18 at 18:18

tschaboo

634

-2

votes

1answer

96 views

How to make a system with USB 3.0 slave that provides data to an FPGA? [closed]

I consider making a system with USB 3.0 slave interface that provides data to an FPGA, where the connection should allow full utilization of the available USB 3.0 speed. What external components are ...

usb fpga

asked Dec 6 '18 at 15:16

EquipDev

16518

0

votes

2answers

79 views

Strange behavior in VHDL design (randomly incrementing values)

I have a fairly simple VHDL design that looks like the following: ...

fpga vhdl hdl

asked Dec 6 '18 at 1:43

Michael Kalajian

1

vote

2answers

74 views

Program FPGA using STM32

I am interested in using an STM32 to flash an sof or pof file onto a Cyclone IV FPGA. The sof/pof will be stored in SPI flash memory, and the plan is to use the STM32 as a programmer. I haven't been ...

fpga stm32 intel-fpga

asked Dec 5 '18 at 23:20

jgaro

9217

1

vote

2answers

83 views

Custom programming for FPGA boards

Is it possible to write your own tool to program FPGA boards, or are they locked down to only be programming by the manufacturer's tools? In other words, can I write my own tool to program/flash a ...

fpga

asked Dec 4 '18 at 22:04

Jas

1083

3

votes

1answer

97 views

What is the proper methodology to create portable FPGA designs?

FPGA designs may contain RTL along with IP blocks. These IP blocks most likely shall be from the vendor of the FPGA. Examples of such IP blocks are instantiating dual clock FIFOs, floating point and ...

fpga hdl quartus portable libero

asked Dec 4 '18 at 20:34

quantum231

3,7521354110

1

vote

1answer

64 views

Driving state machine in FPGA directly from input

I'm learning verilog and in the process trying to implement some simple logic circuits (and as everybody, a simple SOC) I implemented a simple UART, and it worked well during simulation and the test-...

fpga

asked Dec 4 '18 at 0:25

dmsc

263

1

vote

0answers

60 views

audio output on my FPGA

I asked a very bad question related to this yesterday, sorry - this is more comprehensive and makes more sense. this is the manual for the nexys 4 FPGA i'm using https://reference.digilentinc.com/...

audio fpga pwm

asked Dec 3 '18 at 17:36

Amy Fawcett

61

0

votes

2answers

82 views

Verilog problem on Spartan 6 board

I'm planning to do a waveform generator using an FPGA board (spartan 6 board from diychips), however I am new to verilog so I am encountering a bit of a problem. I created a sine-wave sequence using ...

fpga verilog

asked Dec 2 '18 at 17:20

Anthropomorphous Dodecahedron

6401517

1

vote

2answers

128 views

USB Softcore for FPGA : Extra resistor on FPGA transmitter pin

Have anyone used this USB softcore before ? Why do we need extra resistance on the tx pin ONLY ? Whichever pins you transmit on need to have resistors after them. The exact values will depend ...

usb fpga impedance-matching softcore

asked Dec 1 '18 at 16:07

kevin998x

364

0

votes

1answer

53 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...

fpga vhdl verilog xilinx intel-fpga

asked Dec 1 '18 at 15:54

Sourabh Tapas

13210

2

votes

0answers

94 views

No output with for loop

I have been working on this issue for a couple days and still cannot figure it out. I wonder if someone can help me with this. You can just focus on the video process at the bottom of the code below. ...

fpga vhdl modelsim

asked Nov 29 '18 at 14:14

Dinh Nguyen

111

0

votes

2answers

64 views

Error implementing IIR filter on FPGA

I want to implement several IIR filters on an FPGA, using VHDL. The filters is for audio. I start out by implementing a single filter with the following transfer function: $$H_1(z)=\frac{304 -304z^{-...

fpga vhdl digital-filter iir

asked Nov 27 '18 at 12:10

keffe

10219

1

vote

1answer

61 views

Sample time of PI controller

I have designed a closed loop current control (PI controller) of a DC-DC converter in continuous time domain and it is working fine. The next task is discreetization of the controller and implement it ...

fpga pid-controller sampling closed-loop

asked Nov 26 '18 at 21:42

Autobot

686

2

votes

2answers

1k views

No Q bar on flip-flop

I'm currently using Quartus and I'm trying to make a 4 bit counter. I noticed that when I imported the built-in flip-flop that there is no Q bar output. It's the same issue with the JK flip-flop as ...

fpga flipflop

asked Nov 25 '18 at 17:59

Neamus

1356

0

votes

1answer

93 views

Data Strobe in DDR memory

In DDR3 memory there is a signal called DQS that I have several question about. What is DQS abbreviated for? specially Q What is the purpose of data strobe in DRAM and why not use simple clock. Is ...

fpga memory ddr

asked Nov 23 '18 at 14:31

pazel1374

312212

0

votes

1answer

31 views

Vivado LOC constraint via Verilog code

I'm trying to set LOC constraint while specified in verilog code (via verilog attribute). Previous research on the internet gave reasons to think that this sort of construction should work: ...

fpga verilog vivado

asked Nov 23 '18 at 13:39

Guillermo. D. S.

31

5

votes

3answers

1k views

I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?

A schematic by Lattice Semiconductor includes the diagrammed D flip-flop. This D flip/flop accepts, among others, a Set/Reset signal. I would have understood a Set signal. I would have understood a ...

fpga flipflop reset lattice

asked Nov 22 '18 at 19:18

thb

377313

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