Questions tagged [fpga]
A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".
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Need help to develop two timers that takes input from keypad and timer can change on the fly in my project Traffic light Controller in VHDL
Here Pmodout is Output that is coming from keypad decoder. I am trying to figure it how to apply two inputs from keypad for different timers TS and TL while running my traffic light controller project....
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1answer
19 views
Using connected PC keyboard input for VHDL Simulation
I am working on a project for school that will involve an input from a push button or related device. We have only a few Spartan boards available, but we have access to Xlinx Vivado to simulate an ...
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1answer
18 views
Convert bit to bin Xilinx file
How can I convert a .bit (output from ISE Project Navigator) into a .bin file?
For what I understand, .bit files are similar to .bin but with a header that specifies things like the board and stuff.
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3answers
41 views
How can I convert the number of DSP48/BRAM to the number of LUTs and FFs in FGPA
I have a trouble with estimation of logic utilization.
I am Ph.D student who research the efficient implementation of signal processing algorithms. So, I have to compare the logic utilization of ...
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1answer
51 views
Implementing a simple counter using VHDL
Hi I'm trying to implement a counter with external control. I'm kinda new to VHDL and I keep getting syntax error for the following code. Can someone help me understand why there's an error here?
<...
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1answer
29 views
Using VHDL with the Mojo V3 FPGA
I was just wondering if there's any way for me to write VHDL code, that I can then upload to the Mojo V3 board?
The Mojo V3 IDE is Verilog/Lucid friendly, both languages that I'm unfamiliar with.
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1answer
45 views
How to display Numbers on the VGA display in VHDL?
I have a code to display block on the VGA display but I want to display numbers on it. I have a slight idea how to design it but Programmatically, I am having a hard time.
I can define it as a ...
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54 views
At the high level of abstraction, does the choice between ASIC, FPGA or microcontroller matters?
I am new at hardware design, and my goal is to be able to implement a circuit. To start, I don't go farther than the 2nd level of abstraction, but I am supposed to write both the behavioural and ...
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19 views
How to solve the problem 'ModelSim(vsim) is not on the path'?
Now I am trying to initializing Intel HLS(high level synthesis) compiler, and I have downloaded Quartus, VS 2010 professional and ModelSim.
When I input the command in the command prompt, something ...
4
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1answer
55 views
Nexys 4 DDR doesn't load bitstream from microSD card?
Following the lower half of page 6 of this PDF, I formatted a 2 GB microSD card to FAT32 filesystem using mkfs.fat on Ubuntu and copied ...
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0answers
44 views
Which FPGA devices support I/O Voltage as low as 1.0 V Single Ended [closed]
I am looking for an FPGA, similar to Max 10 from Intel, which also supports an I/O voltage of 1.0 V.
I have some 1.0V i/o on the board which should interface with the FPGA, and I dont' want to ...
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34 views
How to convert mirror mode into camera mode on FPGA image?
I have connected a camera with Cyclone V FPGA by Video and Image Processing Unit and the image is displayed on monitor successfully.
But the image received now is a mirror, which means its image ...
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42 views
Pin strength configuration
Please, help me understand the specsheet on page 2-22. The table says that 3.3V standard supports 12mA drive strength, but there is also a "software" defined strength. What is it? There is also a "...
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1answer
40 views
How to convert raw radar sensor data into custom compressed data format for efficiently storing and archiving on file system
The binary raw data from the SAR sensor is processed in fpga and outputted as hex. Now, this data we currently store as ASCII in .txt files. However, it takes lots of space in storing.
Is there an ...
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2answers
75 views
Brute-force convolution reverb in FPGA
I'm completely new to the world of FPGAs, and would like to get a sense of what is possible to achieve, and since I happen to have an interest in convolution reverb algorithms, I will use that example....
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1answer
28 views
How to design a module that counts logic 1s in multiple inputs in Verilog?
For example, I have two inputs, whose value can be either St1 or St0. The changes of states are synchronous to the same clock, say 1MHz of frequency. I want to design a Verilog module that counts how ...
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1answer
54 views
Timing Constraints for Forwarded Generated Center-Sampled Clocks?
Problem Description
I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
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1answer
54 views
Code parts encapsulation method
I have a prototype of a simple monostable multivibrator components like this:
...
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4answers
7k views
Why are FPGAs so expensive?
I mean compared to ICs (ASICs) with similar complexity, speed etc. Let's compare Ethernet switches to Kintex FPGAs (note that the most expensive switch from the list is circa as expensive as the ...
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4answers
3k views
Why are SRAM based FPGA used more than NVM based FPGA?
SRAM based FPGAs need to load the bitstream again after power off. Meanwhile the Non-Volatile based one don't need that.
I wonder, why are more experiments and security research done on the SRAM ...
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1answer
67 views
How can I implement a digital clock in Logisim?
I'm trying to simulate a 12h-digital clock in Logisim. Here's the logic diagram:
I could simulate BCD to 7 Segment but I don't know how to create a CTR DIV 10 and CTR DIV 6 in Logisim, so I tried to ...
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1answer
68 views
verilog code for 2bit * 2bit multiplier [closed]
There will be two 2 bit inputs (0 to 3 in binary), binary multiplication is to be done on these inputs, the output should be a 4-bit binary number, this output will be fed to a 7 segment display on an ...
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1answer
39 views
Vivado : constraints setup for SPI interface with common clock
I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below.
The Artix-7 FPGA (on the motherboard) ...
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1answer
30 views
APB PENABLE stays only for one PCLK regardless of PREADY signal
I followed the AMBA 3 APB specification to design my APB slave. Reading from slave requires several clock cycles to make the data ready for the bus, so I set my PREADY signal for one clock cycle ...
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1answer
76 views
Why can't I implement a frequency divider using a mux in this way?
I found an interesting interview question for FPGA engineer online - Implement a counter with Mux, so I decided to try to do that. I tried to keep it simple and so implement a counter with two bits, ...
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2answers
48 views
Question on output of an FPGA
I have been trying to solve this basic FPGA problem with multiplexers, but I cannot garner the meaning of the notation 0/1. Can someone throw some light in this regard? What do notations like 0/1 mean?...
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1answer
61 views
VHDL multiplication for std_logic_vector
When simulating I get a run time error, so I'm trying to run a RTL analysis in Vivado to see if the schematic of the component can be created at least. The code is the following
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1answer
50 views
FPGA CAN Bus Test Bed
I don't have familiarity with FPGAs and I haven't used VHDL for 21 years, so starting from scratch.
I am wondering if the following is possible/sensible.
FPGA running n "small" independent ...
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1answer
58 views
At both posedge and negedge in Verilog?
In Verilog, I can use an always block and make it trigger on a positive or negative edge.
Is it possible to trigger the block on both the positive and negative edge, and thus have it basically ...
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2answers
116 views
Package detection in datastream on FPGA
Hardware:
I have an asic-"sensor" which sends me 32-bit packages (serial). I need to detect this packages with an FPGA.
When I start the readout, the sensor is sending me data-packages until I stop ...
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1answer
59 views
How to measure a 100 ohm differential signal on a spectrum analyzer?
I have a pair of 1.5V PCML differential signals coming out of an Altera Cyclone V GX FPGA, terminated on the FPGA in 100 ohms with common mode voltage = 0.65V (also provided on the chip).
I need to ...
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1answer
57 views
Avalon-ST PCIe root port in an FPGA
A buddy of mine and I have a project in which we have to implement a PCI Express rootport. I haven't read the entire specification, nor do I have the Mindshare book that everyone recommends, but I ...
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1answer
60 views
DRAM in a FPGA - Image Sensor design
I am designing the simplest form of a camera: an FPGA that interfaces an image sensor and sends the acquired data to the host device via USB 3.0. There is no processing on the FPGA, it is used for ...
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2answers
48 views
Verilog inout port
I have a doubt question. I know that I can use "inout ports" to connect to a pin, but can I use "inout ports" to connect internally 2 modules?
I'm asking this because I have written an SRAM ...
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3answers
61 views
Verilog router design and best way to handle variable size packets in verilog?
I have a synthesizable Verilog/logical design question. My question is more logical than syntax.
I wish to implement some sort of router that has three input/output ports of full-duplex UART RS232, ...
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4answers
240 views
Choosing an FPGA based on ADC sampling rate
I have a project involving an ADC sampling at 500 MHz. I need to take this ADC data and boil it down into something a cheap CPU can process. I believe this is a good application for a low-grade FPGA, ...
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1answer
36 views
Connect FPGA without FMC connector to external ADC board [closed]
I'm working on a project to sample signal at 500MSPS with FPGA and ADC. Since I cannot design IC myself, I want to find one external ADC board that can be directly connected to my FPGA board. I have ...
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1answer
100 views
2D convolution on 32x32 grayscale image on FPGA using verilog for inference of CNN
Hi I am new to the world of convolutional neural networks and would like to implement a 2D convolution operation using the sliding window approach on a xilinx FPGA. The input to the image is a 32x32 ...
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0answers
21 views
Measuring non-linearity in carry-chain based FPGA TDC
I'm trying to check the non-linearity of field programmable gate array(FPGA) delay-chain based time-to-digital converter(TDC). I used the code density test in the article below to measure differential ...
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1answer
36 views
SDC constraints for reusable component
I have a simple register based clock divider component I can drop in when I don't have a spare PLL:
...
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1answer
190 views
How to improve hardware programming skills? [closed]
I am a newly graduated electrical engineer with little knowledge about microprocessors. I have studied with PIC, Arduino, STM and TI processors and even with fpga boards. The problem is my work ...
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0answers
23 views
Can I constrain data output to clock output, or just both relative to internal clock?
I have a small test design in an Altera CycloneIV GX, where I'd like to output data synchronous to a gated clock.
AN433 gives a lot of examples, but they all define output path constraints relative ...
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0answers
63 views
FPGA/VHDL: Branching Input Signals
I was curious if it's possible, or if there is any harm, might be a better question, in branching an input signal within an FPGA design for multiple uses? What I was looking to do in my design is this:...
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2answers
110 views
How many LUTs are needed to implement a CPU? [closed]
I am looking to start my first FPGA based project, but as I am a complete beginner, I have very little idea how big an FPGA I need to implement my idea.
My project will be something similar to a CPU, ...
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3answers
1k views
What does nm mean in FPGA [duplicate]
When I read articles, FPGA comes with a specification-nm.
For example, Xilinx 28nm Virtex 7 or 20nm UltraScale FPGAs.
What does -nm means in FPGA?
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1answer
61 views
How to write constraint file for the divided clock in Verilog?
I am using FPGA Basys 3 board in my college, having 100MHZ clock frequency, i divided the default clock (clk) by 216 and got ...
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1answer
148 views
Altera Cyclone II Quartus II JTAG Programming Error
I'm trying to program a Cyclone II I bought here using Quartus II 13.0sp1 on Arch Linux. I'm trying to program it with a very simple Verilog program with three inputs and two outputs and a few simple ...
3
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2answers
91 views
How do you cast an integer as a time in VHDL?
For the purposes of simplifying a test bench, I would like to set various delays by changing numerical values at the top of the file. I'd like to do something like:
...
2
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1answer
64 views
How to properly constrain generated clock and synchronizer in Altera Quartus?
In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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2answers
23 views
Verilog :Range must be bounded by constant expression
I have one doubt..... The error is came like Range must be bounded by constant expression when Compile the below line
X=in[i+2 : i] +1'b1;
In[i]=-1;
Please tell how to resolve it?
