Questions tagged [fpga]

A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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“Register is illegal in left-hand side of continuous assignment” in modelsim but not verilator

module foo (A, B, C, Y); input A, B, C; output Y; reg Y; assign Y = (A && B); endmodule ...
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39 views

Shared bus in FPGA (arbiter + perypherial bus) [VHDL]

I am trying to implement shared bus in my fpga design. I am thinking about something similar to the microcontroller bus. I see two possibilies: Second option is easier to implement but if bus is ...
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UFS 2.1 read/write interface

I want to read/write a Universal Flash Storage (UFS 2.1) chip. I haven't been able to find readers/programmers online aside from JTAG-rigs from shady websites. A fist look at the JEDEC Standard seems ...
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53 views

FPGA and high speed ADC devepoment board [closed]

We are interested in buying a Development board with FPGA and ADC's that is capable of receiving analog inputs up to 3-4GHz. As much I have checked I was not able to find a board that resides both the ...
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63 views

FPGA counter reset

I am attempting to design a DPIM modulator and demodulator. Essentially, what the code is supposed to do is take 4 bit data, send zeros equal to the number in data and then a single one and repeat. ...
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What are MGT pins used for in fpga and what devices can they be connected to? How can I connect them on fgpa system planner?

Basically, I want to know the how to connect the MGT pins of fpga to any device. And which devices can I connect it to. I am working on fpga system planner.
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64 views

Do unintended latches only happen for signals in the process sensitivity list?

I read in one book that an unintended latch requires you to have a process section where there is a signal in the process sensitivity list but don't assign to in every path. But that doesn't make ...
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Does SRAM need PCB track length/impedance matching

Well, for educational purposes I've decided to make an FPGA-based board with PCIe, HDMI and other high-speed stuff. I've usually used relatively slow (35-45 ns) SRAM and having traces routed in 'hit ...
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48 views

FPGA dsp-slices highest sampling rate possible

DSP slices (following Xilinx’s terminology) have certain speed grades (extracted from the switching characteristics of the device) that span up to some hundreds of MHz. Those DSP slices are heavily ...
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1answer
83 views

Interfacing Wiznet W5300 with a Spartan 3 FPGA?

I have to interface Wiznet W5300 chip with a Spartan 3 FPGA for sending packets over Ethernet using the Hardwired TCP/IP feature of Wiznet. I am planning to interface using the direct/indirect bus of ...
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Is it inefficient or bad style to build std_logic_vector out of std_logic inputs?

I'm learning VHDL, and there are a lot of exercises where they give you an entity and you have to write the architecture, where a lot of the inputs are separate: ...
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60 views

Why does it take 2 clock cycles to move to the RESET state in my state machine?

I'm writing a finite sequence encoder in Verilog. Basically, an output Z will be activated if the input W is on for at least four clock cycles, or if its off for at least 4 clock cycles. See the ...
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41 views

VHDL “can't match slice type array type”

I'm new to VHDL and I'm trying to use code off a teacher's slide that doesn't seem to work as is, and I can't tell what's wrong: ...
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34 views

Who sends the USB SYNC/EOP fields, host or device?

I'm currently studying the USB spec and I have a question about who sends the SYNC and EOP fields in a packet. A typical GET_DESCRIPTOR transaction (say) consists of SETUP and DATA0 packets sent from ...
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1answer
79 views

Embedding data in RAM during synthesis

I have designed a CPU that works in simulation using Verilator, and would now like to test it in hardware on an FPGA. A quick way to get to the testing phase would be to embed a program to run on the ...
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Unresolved inclusion: xuartlite_l.h in Xilinx SDK

I am following Xilinx Lab Workbook. On Lab 3 (page 60) I am supposed to have resolved all errors but I cannot get rid of an unexpected error. "fatal error: xuartlite_l.h: No such file or directory ...
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Ghosting in VGA signal generation

So, I'm generating a 1280x1024 (native screen resolution) VGA signal using a Lattice HX8K > Yosys, according to these timings, and a PLL of 107.812Mhz of Pixel Frequency. I then pass it through a ...
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72 views

Lowpass Audio Filter on FPGA

I am trying to establish a low-pass filter to Audio Demo code of Nexys A7 board. I have implemented a filter however I hear just a noise. If you share your time, I will be happy. I have added the ...
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Why is this Verilog RAM modification better in terms of resource usage?

I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm ...
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68 views

VHDL test bench for input port assignment

I am trying to depict port 3 of microcontroller which acts a I/O and as special functions like timers interrupts in VHDL. The code is as follows: ...
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37 views

Unary-type input to binary output in Verilog?

I've built an FPGA-based circuit which outputs to \$n\$ ordered bits strings which take on the form of either \$k<n\$ \$1\$'s followed by \$n-k\$ \$0\$'s, or \$k\$ \$0\$'s followed by \$n-k\$ \$1\$'...
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62 views

Very high fanout net not being replicated by Vivado

I have a high fanout (~2300) write enable going into a RAM block. The RAM is distributed (hence the high fanout), and I am unable to use block RAM because of area limitations. The ...
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Why is propagation delay a function of supply voltage?

In the context of FPGAs, it was brought to my attention today that propagation delay varies with supply voltage. When I asked why this was so, one of the FPGA designers stated that a logic gate is ...
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Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...
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223 views

How does programming FPGAs and CPLDs differ? [closed]

I am learning to program programmable devices using a XC9572XL CPLD. I would like to know how much knowledge from programming CPLDs (in Verilog, VHDL) will be transferable to programming FPGAs (not ...
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Why would this cause a latch?

I'm reading ZipCPU's tutorial and got confused. Specifically, I'm referring to this page. To transcribe the Verilog code: ...
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104 views

Xilinx FPGA “X” state in simulation and didn't find the bug

I wrote an ASRAM in VHDL and simulate it. I get many "X" if I try to read. I know that this problem is caused by too many drivers on one net but I didn't find the problem nor solved it. Appreciate ...
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87 views

Strategy against Side Channel Attack

I am newbie to Hardware Security. While studying Side Channel Attack, I realized that power consumption profile of electronic control unit is a key to encrypt what algorithm runs on it. I thought ...
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79 views

Does a program exist to draw logic signal waveform from csv data?

Assuming that I want to collect several seconds of activity of digital signal on multiple pins of a device, one way is to create a simple FPGA design that buffers all that information and then ...
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45 views

PIN Placement Errors In Quartus

So I am writing a simple blinking LED Verilog code that will be run on a Cyclone10 LP (Device is called 10CL025YU256I7G) and will be tested on a Cyclone 10 Evaluation Kit (6XX-44504R-0D) All code is ...
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39 views

Setting Pin Assignments For Quartus

So I have written a simple Verilog module which works well in the ModelSim emulator. I would like to now program my Cyclone 10 Dev board to perform this simple task, but I need to set up the pin ...
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42 views

Input CLK Keeps Showing As Hi-Z on ModelSim

I am writing some basic verilog code that blinks an LED at some frequency. The code for the design file is the following: ...
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I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...
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42 views

Accessing RAM on TERASIC DE0 Nano

I'm just wondering how to access more than 32Kb on a TERASIC DE0 nano. It is based on an Altera Cyclone IV FPGA. https://www.ti.com/lit/ug/tidu737/tidu737.pdf It has 32Mb DRAM but there are 12 ...
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External clock with Arty Z7 FPGA development board

I have a digital audio source that is basically I2S. I need to run the FPGA at the exact clock as the I2S provides. I've got four such inputs required, but I am assuming that the clocks are the same. ...
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33 views

Software Driver for custom AXI-stream IP in Xilinx SDK

I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "...
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143 views

data storage, FPGA to mass storage device

For a project I am working on I need to transfer, without loss of information, continous data bursts at a maximum of 48 MB/s from an FPGA to a mass storage device. An SD card device (with appropriate ...
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40 views

TinyFPGA A series board programmer compatibility

Since the programmer writes configurations to the flash of the fpga can I use the TinyFPGA programmer for A series boards on any lcmxo2 chip? Or can I at least use it for the same chip with a ...
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62 views

VHDL - Inferred Latch With Reset - FSM

I have an issue with this process where if I include a reset statement, I get an inferred latch. However, if I do not include the reset statement, I do not get an inferred latch on duty_cycle_triangle....
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Is it easier to implement sigma delta modulator in FPGA by filter or state space model?

Sigma delta modulation is extensively used in quantization to reduce quantization noise. In the literature one can see different architecture for example python-deltasigma to implement a modulator. ...
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Fast Arbiters for On-Chip Network Switches

For "Fast Arbiters for On-Chip Network Switches", what is the difference between Proposed-I and Proposed-II topologies?
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found '0' definitions of operator “*”

I have this error when trying to compile my VHDL code. The purpose of the code is to multiply a 2 bit constant K by some 4-bit number in memory. There are some similar posts here with the same error, ...
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Can a non-enumerated device conduct DMA operations?

PCIe devices can read or write to memory, i.e. can do DMA without requiring a device driver. For example: pcileech (The PCIe FPGA device is controlled by another computer). If I remember correctly, if ...
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49 views

PCI based system debuging

I've came across some products that help you troubleshoot a computer that won't POST, with listening and capturing traffic on PCI bus during system startup. They essentially know the normal procedure,...
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67 views

VHDL - signed vs unsigned adder

I have made a four bit adder with carry-in & -out that contains an unsigned and signed architecture: ...
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88 views

Is using a register chain feeding into a LFSR sufficient to generate “true random numbers” inside an FPGA?

One way to generate random numbers is to pseudo-random numbers. Otherwise, one would need a special mechanism to generate them using dedicated hardware. However, (For FPGAs specifically) why not just ...
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50 views

How to read data from an .mif file in Vivado?

My knowledge on the subject is bare-bones. I created a .coe file and used Block Memory Generator to get an .mif file. I need to store the contents in the block memory and then use it. Following is my ...
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185 views

royalty free embedded processor [closed]

I got into FPGA design last year for a project, and had some success with a Xilinx Spartan 6 dev board using ISE. I could do everything with this low cost board and ISE 14, which is free. I needed an ...
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Write received character from PS/2 keyboard to LCD1602

I am trying to read a pressed key from a PS/2 keyboard and display it on a LCD1602 display. I wrote one entity and architecture which detects a pressed key. If it received the 11 bits (1 start bit, 8 ...
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FSM modeling when outputs are not simple functions of input and current states

All the two/three process block modeling style(the recommended style) examples for FSM have logic for nextstate that is a function of current state and inputs. The outputs in these examples also take ...