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Questions tagged [fpga]

A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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Strange SDRAM Behaviour

i try to use the SDRAM on my DE0 Board. This is the chip: http://zentel-europe.com/datasheets/A3V64S40GTP_v1.3_Zentel.pdf Basically my driver works. i save the value of an upcounted signal in the ...
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23 views

problem connecting an Arduino Ethernet Shield to FPGA trough SPI

I have an Arduino Ethernet Shield and trying to connect it to my spartan 6 board. I used the ICSP header on the bottom of Arduino Ethernet Shield (MISO/SCK/RST/+5/MOSI/GND) and a wire for SS(pin 10 of ...
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1answer
31 views

Two modules and two always statements in one verilog program? [on hold]

Our prof gave us a Verilog code and we were tasked to explain how the code works. Despite having previous experience with Verilog coding, i was confused on the code our prof gave. My experience with ...
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26 views

Verilog - Using 'define' to declare a constant created by a 'parameter'

Pardon the wordiness of the question's title. How would you accomplish the following. I have this parameter: parameter BUS_SIZE = 16; And I want to use it later ...
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75 views

UART RX in VHDL

I have to set up a UART transmitter and receiver using a Spartan 3 board. I've got the transmitter set up already and verified it with the arduino terminal using this FTDI breakout.The receiver is ...
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19 views

Using ALTLVDS_TX megafunction with a DS90CR485 Serializer

Using ALTLVDS_TX megafunction with a DS90CR485 Serializer Hello there, First of all I'm a beginner in FPGA programming and i don't know if my whole approach to this is wrong. I'm currently trying to ...
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28 views

how to send data from ALTERA DE2 to computer? [on hold]

hello I am currently using ALTERA DE2 and writing on VHDL . my question is simple lets say I connect ADC(analog to digital convertor ) to the altera . so for exmaple my ADC gives me 8 bits resulation ....
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66 views

Fpga communicate to pc through usb

I'm currently working on my thesis project on making a secure pendrive. For that I have to design an USB protocol implementation on an FPGA. But I don't know how to physically connect that USB core ...
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Understanding sequential and interleaved burst modes in SDRAMs

I'm studying SDRAM memories. I have read they have 2 burst modes: sequential and interleaved. I don't understand the differences between them, can you please give an explanation? And, when should I ...
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31 views

Quartus Prime: Block synthesized away - why?

Doing my very first steps with FPGA. I successfully built an SPI slave (code found somewhere in the web) that receives something and turns an LED (via output SPI_DONE) on my Altera Max10 evaluation ...
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75 views

Creating big MUXes and shift registers on FPGA

I'm working on a guitar tuner project on FPGA. For this I have to pass the sound signal (16bit/1024Hz sampling) from the ADC to a FFT block but I want the FFT block to be clocked with much higher ...
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76 views

Significance of timing simulation for FPGA

I have started to wonder what is the significance of the timing simulation for FPGAs nowadays. I can easily justify what is the idea behind that by quoting some Xilinx materials: Performing a ...
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28 views

Exporting RAM content to text file in ISim

I'm trying to learn about Xilinx IP cores and FFT implementation on FPGA-s. For that I've created a simple project where I instantiate LogiCore FFT 8.0 core, ROM core and a RAM core. The ROM core ...
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1answer
46 views

Verilog nested for loop not behaving as expected

I am having trouble with a simulation of an 8-bit full adder i wrote in verilog. Basically I have two integers that I feed into the full adder, I add them together and I check if the result is as ...
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2answers
121 views

Are there special rules for voltage division of a high speed clock?

High speed signals require special care in PCB layout to prevent high speed effects like ringing and overshoot. This obviously applies to clock signals as well. Provided that one has a high voltage ...
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37 views

can't send characters using fpga cyclone iv

I'm trying to connect my FPGA Cylone IV (CoreEP4CE6) with Raspberry Pi 3 for communication through UART. The process (uart_rx) for receiving data is working fine, however, when I place another process ...
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1answer
108 views

UART receiver VHDL

VHDL FPGA UART receiver which receives 10 bits via Bluetooth interface. With 8 7-segment displays. Now my problem is the following In the requirements it is stated that I have to write the solution ...
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1answer
60 views

Creating a Counter in Verilog for Flashing LED on Lattice Starter Kit

I have a lattic X03LF starter board with 6900C FGPA. There are eight LED available on this board and a push button. The goal of my code is to design a 8 bit counter that increments whenever a button ...
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2answers
103 views

Problem with adding two counters in series on an FPGA

I am using Verilog in Lattice Diamond IDE with a lattice MachXO2 7000HE breakout board. I built a basic counter with a limit input which generates a variable period clock output. It works fine on its ...
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1answer
112 views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...
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1answer
102 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...
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2answers
86 views

Altera has created EPCS and EPCQ devices, can only these be used to store FPGA configuration data?

FPGA configuration data must be stored in external non-volatile memory. Can we use just any flash memory or only specific types? What about EEPROMs or any other nonvolatile memory device? Edit: I am ...
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73 views

FPGA timing for FT601

I am trying to interface and FPGA board with the FT601 usb bridge chip and I am having some issue with the timing constrains. In short, the FT601 has a source-synchronous interface with a ...
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1answer
119 views

Fixed-point arithmetic

I want to give two input data of my testbench from a file contains bits(std_logic_victor(15 downto 0) to some arithmetic operartion between fixed point and the files but when it starts I see below ...
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1answer
72 views

Are there CPLD / FPGA toolchains and workflows that bypass vendor IDEs? [duplicate]

Custom programming for FPGA boards is a similar and helpful question for any with the same as this, but they are different. In that thread they discuss custom options and building their own. This ...
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1answer
64 views

Clock frequency of FPGA circuit and 4-bit counter [closed]

I have implemented a 4 bit counter using HDL. Now I have downloaded the code to an FPGA kit with a 50 Mhz oscillator. This means that the clock period will be equal to 0.02 microseconds and ...
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2answers
62 views

7 to 128 decoder in Verilog

I'm new to digital electronics and programming in Verilog particularly. I have programmed some basic programs like 2 to 4 decoder, and 4 to 16 decoder. But I am trying to make an image sensor and say ...
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1answer
56 views

Xilinx Vivado: How are inputs/outputs handled that are not in the constraints file?

Assume I have the following constraints file which specifies only one single input: ...
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1answer
96 views

How to make a system with USB 3.0 slave that provides data to an FPGA? [closed]

I consider making a system with USB 3.0 slave interface that provides data to an FPGA, where the connection should allow full utilization of the available USB 3.0 speed. What external components are ...
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2answers
78 views

Strange behavior in VHDL design (randomly incrementing values)

I have a fairly simple VHDL design that looks like the following: ...
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2answers
72 views

Program FPGA using STM32

I am interested in using an STM32 to flash an sof or pof file onto a Cyclone IV FPGA. The sof/pof will be stored in SPI flash memory, and the plan is to use the STM32 as a programmer. I haven't been ...
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2answers
82 views

Custom programming for FPGA boards

Is it possible to write your own tool to program FPGA boards, or are they locked down to only be programming by the manufacturer's tools? In other words, can I write my own tool to program/flash a ...
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1answer
96 views

What is the proper methodology to create portable FPGA designs?

FPGA designs may contain RTL along with IP blocks. These IP blocks most likely shall be from the vendor of the FPGA. Examples of such IP blocks are instantiating dual clock FIFOs, floating point and ...
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1answer
64 views

Driving state machine in FPGA directly from input

I'm learning verilog and in the process trying to implement some simple logic circuits (and as everybody, a simple SOC) I implemented a simple UART, and it worked well during simulation and the test-...
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60 views

audio output on my FPGA

I asked a very bad question related to this yesterday, sorry - this is more comprehensive and makes more sense. this is the manual for the nexys 4 FPGA i'm using https://reference.digilentinc.com/...
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2answers
82 views

Verilog problem on Spartan 6 board

I'm planning to do a waveform generator using an FPGA board (spartan 6 board from diychips), however I am new to verilog so I am encountering a bit of a problem. I created a sine-wave sequence using ...
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2answers
128 views

USB Softcore for FPGA : Extra resistor on FPGA transmitter pin

Have anyone used this USB softcore before ? Why do we need extra resistance on the tx pin ONLY ? Whichever pins you transmit on need to have resistors after them. The exact values will depend ...
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1answer
53 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...
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94 views

No output with for loop

I have been working on this issue for a couple days and still cannot figure it out. I wonder if someone can help me with this. You can just focus on the video process at the bottom of the code below. ...
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2answers
63 views

Error implementing IIR filter on FPGA

I want to implement several IIR filters on an FPGA, using VHDL. The filters is for audio. I start out by implementing a single filter with the following transfer function: $$H_1(z)=\frac{304 -304z^{-...
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1answer
61 views

Sample time of PI controller

I have designed a closed loop current control (PI controller) of a DC-DC converter in continuous time domain and it is working fine. The next task is discreetization of the controller and implement it ...
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2answers
1k views

No Q bar on flip-flop

I'm currently using Quartus and I'm trying to make a 4 bit counter. I noticed that when I imported the built-in flip-flop that there is no Q bar output. It's the same issue with the JK flip-flop as ...
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1answer
87 views

Data Strobe in DDR memory

In DDR3 memory there is a signal called DQS that I have several question about. What is DQS abbreviated for? specially Q What is the purpose of data strobe in DRAM and why not use simple clock. Is ...
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1answer
31 views

Vivado LOC constraint via Verilog code

I'm trying to set LOC constraint while specified in verilog code (via verilog attribute). Previous research on the internet gave reasons to think that this sort of construction should work: ...
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3answers
1k views

I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?

A schematic by Lattice Semiconductor includes the diagrammed D flip-flop. This D flip/flop accepts, among others, a Set/Reset signal. I would have understood a Set signal. I would have understood a ...
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2answers
71 views

PN sequence verifier

I have a AD9253 ADC connected to an FPGA. I want to verify the design, so I use the ADC in PN sequence short mode. (See p.28 in the datasheet.) Here is a table (...
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43 views

Need help to develop two timers that takes input from keypad and timer can change on the fly in my project Traffic light Controller in VHDL

Here Pmodout is Output that is coming from keypad decoder. I am trying to figure it how to apply two inputs from keypad for different timers TS and TL while running my traffic light controller project....
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1answer
36 views

Using connected PC keyboard input for VHDL Simulation

I am working on a project for school that will involve an input from a push button or related device. We have only a few Spartan boards available, but we have access to Xlinx Vivado to simulate an ...
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1answer
68 views

Convert bit to bin Xilinx file

How can I convert a .bit (output from ISE Project Navigator) into a .bin file? For what I understand, .bit files are similar to .bin but with a header that specifies things like the board and stuff.
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How can I convert the number of DSP48/BRAM to the number of LUTs and FFs in FGPA

I have a trouble with estimation of logic utilization. I am Ph.D student who research the efficient implementation of signal processing algorithms. So, I have to compare the logic utilization of ...