Newest 'fpga' Questions

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Is there a proper way in VHDL/Verilog to access block RAM given a multi-hot vector?

I am currently trying to learn how to program in VHDL with the goal of implementing an LDPC decoder in hardware. My understanding is that log-likelihood ratios (LLRs) serve as inputs to the decoder. ...

asked 22 hours ago

Austin

132 bronze badges

0

votes

1answer

43 views

What kind of FPGA board for sha-256 algo [closed]

I am newbie in VHDL and FPGA, i was searching for an answer to my question but didn't find any good answer. In my projet i have a .txt file containing a ...

fpga vhdl

asked yesterday

Hamita

31 bronze badge

-1

votes

1answer

25 views

Can propagation delays be simulated in Active-HDL?

I'm using the Lattice Diamond licensed version of Aldec Active-HDL. The logic circuits I'm working with are complex enough that I believe propagation delays could have an impact on the actual function ...

fpga verilog lattice activehdl

asked 2 days ago

Gacekky1

194 bronze badges

0

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25 views

Best courses/books on FPGAs? [closed]

At college we have studied digital electronics and VHDL, and by the end of next semester we will have studied VLSI design. In the summer I want to spend time on learning embedded systems design with ...

digital-logic fpga vhdl programmable-logic books

asked 2 days ago

Billbob

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19 views

Mapping unused bits of a bus in VHDL to a signal to avoid partial mapping error: Is there an alternative?

I have a VHDL design containing a module that is reused frequently. This module has an output port that is 32 bits wide. The output of the submodule needs to be connected to other modules with input ...

fpga vhdl

asked Jan 12 at 22:31

David

1747 bronze badges

0

votes

1answer

67 views

Using DDR4 RAM instead of SRAM

Currently I am using the internal BlockRAM from a FPGA to safe the samples I am getting from an ADC with a frequency of 200MHz. In the future, I want to use equivalent time sampling to get a virtual ...

fpga ram

asked Jan 12 at 15:44

Yoomo

1055 bronze badges

1

vote

1answer

41 views

Why does FPGA PCI Express Tx output have on-chip termination of 100 Ohm?

The Intel Cyclone IV FPGA supports PCI Express (PCIe) generation 1, and the IO standard for the Tx output is PCML at 1.5 V. The Cyclone IV Device Handbook volume 2 page 1-13 describes that the Tx ...

fpga signal-integrity pcie termination

asked Jan 12 at 10:23

EquipDev

3313 silver badges10 bronze badges

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0answers

42 views

Generate smooth sine wave from ZYNQ Analog to Digital Converter(ADC)

I have system built on ZYNQ SoC. The ADC of the ZYNQ Soc is fed with 10KHz sine wave and I am getting below wave as the output of ADC. This signal is further processed by further modules. As this ...

fpga adc filter vhdl zynq

asked Jan 11 at 22:06

karthik

213 bronze badges

0

votes

1answer

31 views

Need help with timing in Verilog functions

I'm doing a filtering project and I'm writing a module that feeds a lot of data to some compute units. There's a lot of really repetitive code and I was wondering if there was any way to condense it, ...

fpga verilog programming dsp

asked Jan 11 at 0:41

George Yu

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34 views

How to write a linear interpolator in VHDL?

I have to create a linear interpolator in VHDL.My interpolator has to take 2 known values and using a factory level of 2 in interpolation return the interpolated value.Our signal is campionated with a ...

fpga vhdl programmable-logic

asked Jan 10 at 14:00

velectron

273 bronze badges

-1

votes

0answers

59 views

Thesis Inspiration [closed]

I am a student working towards an Ms in electrical and computer engineering. I love AI, fpga's and circuitry design. I'm at the part of my degree where I need to start seriously looking into choosing ...

fpga

asked Jan 9 at 0:09

CakeMaster

11

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1answer

50 views

Test benches in VHDL

I have a question about the 'correct' way to use test benches to test VHDL components in Vivado. To give you an idea of my task, I have a source file called Top_Level which is going to be the highest ...

fpga vhdl register

asked Jan 8 at 20:43

David777

5323 silver badges15 bronze badges

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votes

0answers

38 views

How to crop/resize images in video stream on frame grabber with FPGA?

I am attempting to simply crop or resize the images as they are streamed to the frame grabber using the FPGA onboard this Euresys Coaxlink Quad CXP-12 frame grabber. The frame grabber has an XCKU035 ...

fpga xilinx vivado imageprocessing vivado-hls

asked Jan 8 at 7:16

Ryan F

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votes

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31 views

Digilent Arty A7 Bypass Capacitors

Looking through the Digilent Arty A7 evaluation board's schematic and noticed that there are two capacitors banks connected to the core supply voltage of the FPGA (VCCINT pins). I was curious about ...

fpga xilinx bypass-capacitor

asked Jan 7 at 19:18

dby

334 bronze badges

0

votes

0answers

21 views

Determining jitter for Vivado clocking wizard?

I have an Artix-7 FPGA AC701 board. In the documentation, it says that it has a 2.5V LVDS differential 200 MHz oscillator (model name: SiT9102AI-243N25E200.00000). I went into SiT9102 datasheet and it ...

fpga oscillator clock xilinx vivado

asked Jan 6 at 13:42

Topa

1

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0answers

36 views

Lattice FPGA: Mach X02 7000 Can it be used for DSP?

I have a MachX02 7000 having 6800 LUT's. I want to implement DSP algorithm involving floating-point DSP algorithm on 2 14 bit ADC input data. Is it possible to perform on this FPGA with low LUT's, No ...

fpga dsp lattice

asked Jan 6 at 7:10

yash jain

111 bronze badge

0

votes

0answers

41 views

Timing issue about DSP Parallel I/O

I want to use DSP's parallel I/O to communicate with FPGA synchronously but find an issue with the timing. In this design, DSP writes data to FPGA through its parallel IO. The CLKOUT is generated from ...

fpga verilog dsp texas-instruments timing

asked Jan 6 at 6:37

Ross

4582 silver badges14 bronze badges

-2

votes

1answer

50 views

How does signal aggregation work? [closed]

I just wanna know how signal aggregation works. For example, there is an IC which can aggregate more than two interfaces(I2C, SPI .etc). Thanks.

pcb-design fpga integrated-circuit signal-processing interface

asked Jan 4 at 14:23

ssabassaba

32 bronze badges

0

votes

0answers

56 views

FPGA multiplication using DSP hardware, signed vs. unsigned

I'm using the DSP unit (just a fancy name for the multiplier/accumulator unit) of the Gowin GW1N devices to do some fairly simple math. These units accept two 18 bit inputs for the multiplier adding ...

fpga dsp computer-arithmetic multiplication

asked Jan 3 at 9:11

gnuarm

797 bronze badges

0

votes

0answers

23 views

Unable to generate device simulation libraries from Quartus Prime

I am using Quartus 18.1. I am trying to generate device simulation libraries as per the procedure here: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/...

fpga simulation quartus library

asked Jan 2 at 0:00

Quantum0xE7

1,0562 silver badges16 bronze badges

1

vote

1answer

180 views

Xilinx FPGA and DDR3 Memory. Confusing Impedance combinations

Currently I'm planning on doing a PCB with DDR3 memory and an Artix7 FPGA. During my research a few questions accumulated. When looking at the reference manual of the Arty7 board, I see that I have to ...

fpga impedance xilinx ddr3 artix-series-fpga

asked Dec 31 '20 at 19:54

GNA

1,3879 silver badges12 bronze badges

1

vote

0answers

64 views

Calling a function that's defined in an interface

I defined an interface and a function inside it as follows: ...

fpga system-verilog vlsi

asked Dec 31 '20 at 12:06

shaiko

3131 silver badge7 bronze badges

1

vote

1answer

68 views

Output waveform of TCS3200

I am trying to use TCS3200 color sensor for my project with De0 nano FPGA board. The output of TCS3200 is a square waveform and i am confused how to use that waveform for a particular task. I searched ...

fpga verilog intel-fpga quartus

asked Dec 31 '20 at 10:27

Ayush Sharma

213 bronze badges

2

votes

2answers

99 views

Signed number multiplication on FPGA

I am trying to multiply signed numbers on a Nexys A7-100T FPGA development board with VHDL. See Reference manual webpage link for the FPGA board hardware information. Also see this link (begins page ...

fpga vhdl

asked Dec 30 '20 at 20:18

David777

5323 silver badges15 bronze badges

0

votes

0answers

30 views

Serial I/O Not working on DE5-Net

I'm porting a circuit from DE0-Nano to DE5-Net. I'm currently implementing a simple test circuit for the DE5-Net. So far I can program the user LEDs and the two Hex Displays. However, I don't seem to ...

fpga serial io

asked Dec 30 '20 at 16:19

Joey

32 bronze badges

0

votes

1answer

31 views

How to view the implementation on Vivado

im very new to FPGA programming. Is there a way to view the implementation of a digital logic design on the selected hardware device? For example exactly how an arithmetic operation is implemented ...

fpga vivado

asked Dec 28 '20 at 16:56

Tech Visionary

174 bronze badges

3

votes

1answer

113 views

questions about up-sampling and moving from slow to fast clock domain in FPGA

I encountered some questions and problems I asked myself lately and hoped I can get a nice lead here before I start reading long articles without even be sure if it's the right way. Let's assume I ...

fpga adc dsp cdc

asked Dec 28 '20 at 7:25

Michael Astahov

4292 silver badges9 bronze badges

0

votes

2answers

61 views

Gigabit transceiver with MHz reference clock

I've some experience with Xilinx FPGA generating 10Gb/s over SMA loopback with on-off keying modulation (what scope shows) to perform BER test but the documentation shows it uses a reference clock in ...

fpga xilinx clock-speed transceiver gigabit

asked Dec 27 '20 at 16:30

LifeIsBeatiful

31 bronze badge

0

votes

0answers

9 views

Can Quartus help the user find out power saving if one uses clock control block to disable clock?

The clock control block can be used to disable clock to a section of the design thereby achieving clock gating. Can Quartus help the user find out how much saving such a measure will help achieve in ...

fpga power-dissipation quartus clock-gating

asked Dec 26 '20 at 22:08

Quantum0xE7

1,0562 silver badges16 bronze badges

0

votes

0answers

38 views

FPGA design xilinx

The ASMBL architecture breaks through traditional design barriers by: Eliminating geometric layout constraints such as dependencies between I/O count and array size. Enhancing on-chip power and ...

fpga artix-series-fpga

asked Dec 26 '20 at 8:47

Tech Visionary

174 bronze badges

0

votes

2answers

62 views

Sending data to FPGA [closed]

If I send 160bit message to an FPGA using TCP/IP Do I need to store the message in BRAM first ? Not sure how the FPGA receives data and gets to work on it yet.

fpga xilinx input tcp-ip bram

asked Dec 24 '20 at 17:33

Jay

31 bronze badge

0

votes

1answer

38 views

AD7626 interfacing with Zynq or Kintex

I want to connect an AD7626 with a Zynq FPGA or a Kintex. Which bank should I choose? Let say the for case Chosen Zynq FPGA has only HR bank Kintex has HR and HP bank. How should I choose a bank ...

fpga adc xilinx zynq kintex-series-fpga

asked Dec 22 '20 at 17:36

case sel is

11 bronze badge

2

votes

1answer

57 views

Power dissipation calculation for FPGA-ADC interface

An FPGA can be interfaced with an ADC using CMOS or LVDS. Is there a way to use simulation to predict the power dissipation of the I/O blocks for a given operating frequency for this interface? If so, ...

fpga simulation power-dissipation lvds

asked Dec 21 '20 at 15:46

Quantum0xE7

1,0562 silver badges16 bronze badges

0

votes

3answers

90 views

How can the FPGA design induce a system wide reset?

FPGAs have a reset signal that is spread across through the global routing. If the user logic needs to carry out a system reset for whatever reason, how should this be done? Can the user logic ...

fpga

asked Dec 18 '20 at 23:57

Quantum0xE7

1,0562 silver badges16 bronze badges

0

votes

4answers

119 views

Problem mapping VHDL onto development board

I have a very frustrating problem and would really appreciate some help. I am trying to test a RAM block using the switches and LED's on board the Nexys A7-100T FPGA development board. My code is ...

digital-logic fpga vhdl clock flipflop

asked Dec 18 '20 at 21:17

David777

5323 silver badges15 bronze badges

0

votes

1answer

67 views

Storing Program Instructions on FPGA

I am creating a basic RISC processing core on a FPGA development board (Nexys A7-100t). I created a RAM block that will be used to store the instructions that my basic processor will execute to run a ...

fpga vhdl ram

asked Dec 18 '20 at 8:06

David777

5323 silver badges15 bronze badges

1

vote

0answers

15 views

Tracing boolean functions using a TUL PYNQ Z2 board

I am trying to trace the output of a simple XOR gate using a PYNQ Z2 board. But the documentation and related tutorials are not helping. My boolean function is as follows: ...

fpga xilinx

asked Dec 17 '20 at 20:43

Mohammed Arshaan

1511 silver badge10 bronze badges

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votes

0answers

35 views

Counter increment inside FSM

I am using the fsm to count both rising and falling edges of a slow clock The counter i have incremented inside fsm. I gave used master and slave for counter I.e whenever edge is detected i increment ...

fpga xilinx fsmc

asked Dec 16 '20 at 21:44

Manish Kumar Kushwaha

1

vote

2answers

87 views

Easier way to implement a large look-up table in Verilog?

I am designing the FPGA-based control for a power-electronic AC/DC converter. This converter has five output voltage levels, so it has 8 switching instances. The levels are given by ...

fpga verilog ac-dc programmable-logic

asked Dec 16 '20 at 18:08

CaptainFantastic

776 bronze badges

0

votes

1answer

92 views

How to monitor FPGA signals on the simulator

I have an FPGA project on Vivado in VHDL that contains lots of components, let's call them 'blocks'. I am testing these 'blocks' individually before integrating them together for the final design. ...

fpga vhdl

asked Dec 14 '20 at 12:47

David777

5323 silver badges15 bronze badges

0

votes

1answer

88 views

Can anyone spot my mistake (VHDL)

I have been scratching my head with this one for a while. Probably a simple problem to people familiar with VHDL on Vivado. I have inserted all my code below. I am creating a 32 bit register from D ...

fpga vhdl code

asked Dec 12 '20 at 22:21

David777

5323 silver badges15 bronze badges

1

vote

1answer

68 views

How to make a HDMI signal be identified as HDMI instead of DVI?

I am experimenting with the HDMI port of an ULX3S FPGA board. I have been able to properly generate DVI signals with a resolution of 800x600 and framerate of 60 Hz. I am now trying generate actual ...

fpga video hdmi

asked Dec 12 '20 at 19:54

Eduardo

351 silver badge4 bronze badges

7

votes

3answers

559 views

How to write scalable VHDL code

I have a question about writing scalable code in VHDL. I have a structural VHDL project that contains a lot of components. I would like a method of changing the bit size of all components by just ...

fpga vhdl

asked Dec 12 '20 at 14:38

David777

5323 silver badges15 bronze badges

0

votes

0answers

53 views

Opto-coupler IC internal voltage drop

I have a circuit where an 12 bit ADC IC is outputting 5V logic levels, which are going to be read by an FPGA inputs. The FPGA voltage is 3.3V so the 5V outputs from the ADC chip will switch the 3.3V ...

fpga opto-isolator

asked Dec 12 '20 at 9:48

David777

5323 silver badges15 bronze badges

2

votes

2answers

99 views

Booting multiple FPGAs using a single SPI Flash

I am using 3 Artix-7 FPGAs in my design. Is it possible to use single SPI configuration Flash to program 3 FPGA device. I have found information about multiple boots for one FPGA but not multiple FPGA ...

fpga spi xilinx bootloader configuration

asked Dec 9 '20 at 12:40

Shifali

715 bronze badges

0

votes

3answers

51 views

Internal and external storage for a FPGA

I want to store at least 2Mbits on a FPGA. What is the normal practice for storing data on a FPGA internally? Also, if I wanted to store 4GBytes externally, how would I go about doing this? Is it ...

usb fpga ram storage

asked Dec 9 '20 at 1:29

SaltSolutionPromo

1

3

votes

3answers

970 views

Beginner question: what does it mean for a TinyFPGA BX to be sold without pins?

This might come across as a really silly question for some of you, but to give more context - I want to buy a gift for someone else and I have found a TinyFPGA BX, but it says "without pins"....

fpga buying

asked Dec 8 '20 at 10:05

NewToCoding

392 bronze badges

0

votes

0answers

31 views

CMOD A7 Seeing Input Even When There is None

I've created a quantum-random number generator which is outputting random pulses to 8 IO pins on my FPGA. I've implemented the following input component to lengthen the ~10ns pulses to something my ...

fpga vhdl artix-series-fpga

asked Dec 6 '20 at 16:18

Persistence

839 bronze badges

1

vote

1answer

44 views

How to improve timing on this design using so much BlockRAM?

I'm building a small RISC FPGA CPU on an Artix-7 (Arty A7-100 (xc7a100tcsg324-1) board. It runs fine, most instructions take three clocks (non-pipelined), but due to crazy net delays, can only run at ...

fpga verilog xilinx artix-series-fpga

asked Dec 3 '20 at 23:29

TomServo

7335 silver badges14 bronze badges

2

votes

1answer

98 views

Clock domain crossing between OV7670 interface and AXI4-Stream

Update 1: My first approach is to use the xpm_cdc_handshake macro in the following way: ...

fpga vhdl clock xilinx cdc

asked Dec 3 '20 at 11:41

Kampi

2501 silver badge10 bronze badges

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