Newest 'fpga' Questions

1

vote

3answers

64 views

“Register is illegal in left-hand side of continuous assignment” in modelsim but not verilator

module foo (A, B, C, Y); input A, B, C; output Y; reg Y; assign Y = (A && B); endmodule ...

asked 2 days ago

Joseph Garvin

1273 bronze badges

1

vote

1answer

39 views

Shared bus in FPGA (arbiter + perypherial bus) [VHDL]

I am trying to implement shared bus in my fpga design. I am thinking about something similar to the microcontroller bus. I see two possibilies: Second option is easier to implement but if bus is ...

fpga vhdl bus

asked Jan 17 at 13:27

kolumb

334 bronze badges

0

votes

0answers

23 views

UFS 2.1 read/write interface

I want to read/write a Universal Flash Storage (UFS 2.1) chip. I haven't been able to find readers/programmers online aside from JTAG-rigs from shady websites. A fist look at the JEDEC Standard seems ...

fpga flash read

asked Jan 16 at 16:39

LeDoggo

1

0

votes

0answers

53 views

FPGA and high speed ADC devepoment board [closed]

We are interested in buying a Development board with FPGA and ADC's that is capable of receiving analog inputs up to 3-4GHz. As much I have checked I was not able to find a board that resides both the ...

fpga adc board

asked Jan 16 at 13:28

user3302780

293 bronze badges

1

vote

1answer

63 views

FPGA counter reset

I am attempting to design a DPIM modulator and demodulator. Essentially, what the code is supposed to do is take 4 bit data, send zeros equal to the number in data and then a single one and repeat. ...

fpga

asked Jan 16 at 9:13

Faisal Khaskheli

112 bronze badges

0

votes

0answers

17 views

What are MGT pins used for in fpga and what devices can they be connected to? How can I connect them on fgpa system planner?

Basically, I want to know the how to connect the MGT pins of fpga to any device. And which devices can I connect it to. I am working on fpga system planner.

fpga cadence

asked Jan 16 at 4:52

Haripriya

1

0

votes

1answer

64 views

Do unintended latches only happen for signals in the process sensitivity list?

I read in one book that an unintended latch requires you to have a process section where there is a signal in the process sensitivity list but don't assign to in every path. But that doesn't make ...

fpga vhdl

asked Jan 15 at 3:39

Joseph Garvin

1273 bronze badges

3

votes

3answers

141 views

Does SRAM need PCB track length/impedance matching

Well, for educational purposes I've decided to make an FPGA-based board with PCIe, HDMI and other high-speed stuff. I've usually used relatively slow (35-45 ns) SRAM and having traces routed in 'hit ...

pcb pcb-design fpga high-speed sram

asked Jan 10 at 22:56

batyastudios

334 bronze badges

0

votes

1answer

48 views

FPGA dsp-slices highest sampling rate possible

DSP slices (following Xilinx’s terminology) have certain speed grades (extracted from the switching characteristics of the device) that span up to some hundreds of MHz. Those DSP slices are heavily ...

fpga xilinx dsp

asked Jan 9 at 16:47

Rizias

614 bronze badges

1

vote

1answer

83 views

Interfacing Wiznet W5300 with a Spartan 3 FPGA?

I have to interface Wiznet W5300 chip with a Spartan 3 FPGA for sending packets over Ethernet using the Hardwired TCP/IP feature of Wiznet. I am planning to interface using the direct/indirect bus of ...

fpga ethernet

asked Jan 7 at 6:26

Candy

634 bronze badges

1

vote

2answers

80 views

Is it inefficient or bad style to build std_logic_vector out of std_logic inputs?

I'm learning VHDL, and there are a lot of exercises where they give you an entity and you have to write the architecture, where a lot of the inputs are separate: ...

fpga vhdl

asked Jan 6 at 4:37

Joseph Garvin

1273 bronze badges

0

votes

1answer

60 views

Why does it take 2 clock cycles to move to the RESET state in my state machine?

I'm writing a finite sequence encoder in Verilog. Basically, an output Z will be activated if the input W is on for at least four clock cycles, or if its off for at least 4 clock cycles. See the ...

fpga verilog clock state-machines sequence-detector

asked Jan 5 at 4:55

user3308807

535 bronze badges

0

votes

2answers

41 views

VHDL “can't match slice type array type”

I'm new to VHDL and I'm trying to use code off a teacher's slide that doesn't seem to work as is, and I can't tell what's wrong: ...

fpga vhdl

asked Jan 4 at 20:28

Joseph Garvin

1273 bronze badges

1

vote

1answer

34 views

Who sends the USB SYNC/EOP fields, host or device?

I'm currently studying the USB spec and I have a question about who sends the SYNC and EOP fields in a packet. A typical GET_DESCRIPTOR transaction (say) consists of SETUP and DATA0 packets sent from ...

usb fpga usb-device usb-host

asked Jan 3 at 4:03

Mark Feldman

2051 silver badge4 bronze badges

1

vote

1answer

79 views

Embedding data in RAM during synthesis

I have designed a CPU that works in simulation using Verilator, and would now like to test it in hardware on an FPGA. A quick way to get to the testing phase would be to embed a program to run on the ...

fpga verilog synthesis

asked Dec 31 '19 at 16:21

VivaDaylight3

1851 silver badge6 bronze badges

0

votes

0answers

17 views

Unresolved inclusion: xuartlite_l.h in Xilinx SDK

I am following Xilinx Lab Workbook. On Lab 3 (page 60) I am supposed to have resolved all errors but I cannot get rid of an unexpected error. "fatal error: xuartlite_l.h: No such file or directory ...

fpga xilinx vivado xilinx-sdk

asked Dec 30 '19 at 3:43

Maxsash

1334 bronze badges

10

votes

2answers

313 views

Ghosting in VGA signal generation

So, I'm generating a 1280x1024 (native screen resolution) VGA signal using a Lattice HX8K > Yosys, according to these timings, and a PLL of 107.812Mhz of Pixel Frequency. I then pass it through a ...

fpga display vga timing-analysis

asked Dec 27 '19 at 18:28

Hugo Sereno Ferreira

5041 gold badge3 silver badges18 bronze badges

0

votes

0answers

72 views

Lowpass Audio Filter on FPGA

I am trying to establish a low-pass filter to Audio Demo code of Nexys A7 board. I have implemented a filter however I hear just a noise. If you share your time, I will be happy. I have added the ...

audio fpga vhdl low-pass convolution

asked Dec 25 '19 at 5:51

layout789

3212 silver badges10 bronze badges

16

votes

2answers

1k views

Why is this Verilog RAM modification better in terms of resource usage?

I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm ...

fpga verilog optimization lattice yosys

asked Dec 23 '19 at 23:36

Hugo Sereno Ferreira

5041 gold badge3 silver badges18 bronze badges

0

votes

1answer

68 views

VHDL test bench for input port assignment

I am trying to depict port 3 of microcontroller which acts a I/O and as special functions like timers interrupts in VHDL. The code is as follows: ...

fpga vhdl xilinx testbench

asked Dec 19 '19 at 17:24

karthik

11 bronze badge

0

votes

0answers

37 views

Unary-type input to binary output in Verilog?

I've built an FPGA-based circuit which outputs to \$n\$ ordered bits strings which take on the form of either \$k<n\$ \$1\$'s followed by \$n-k\$ \$0\$'s, or \$k\$ \$0\$'s followed by \$n-k\$ \$1\$'...

fpga verilog counter binary

asked Dec 18 '19 at 21:24

T. Zaborniak

11 bronze badge

0

votes

0answers

62 views

Very high fanout net not being replicated by Vivado

I have a high fanout (~2300) write enable going into a RAM block. The RAM is distributed (hence the high fanout), and I am unable to use block RAM because of area limitations. The ...

fpga xilinx vivado

asked Dec 18 '19 at 19:25

Eugene Wu

1131 silver badge8 bronze badges

7

votes

2answers

1k views

Why is propagation delay a function of supply voltage?

In the context of FPGAs, it was brought to my attention today that propagation delay varies with supply voltage. When I asked why this was so, one of the FPGA designers stated that a logic gate is ...

mosfet fpga delay propagation

asked Dec 18 '19 at 18:58

pr871

9123 silver badges16 bronze badges

1

vote

0answers

33 views

Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...

fpga verilog intel-fpga quartus

asked Dec 14 '19 at 23:26

user3818491

133 bronze badges

5

votes

2answers

223 views

How does programming FPGAs and CPLDs differ? [closed]

I am learning to program programmable devices using a XC9572XL CPLD. I would like to know how much knowledge from programming CPLDs (in Verilog, VHDL) will be transferable to programming FPGAs (not ...

fpga vhdl verilog programming programmable-logic

asked Dec 14 '19 at 18:43

luanoob

511 bronze badge

0

votes

2answers

122 views

Why would this cause a latch?

I'm reading ZipCPU's tutorial and got confused. Specifically, I'm referring to this page. To transcribe the Verilog code: ...

fpga verilog latch register hdl

asked Dec 12 '19 at 13:36

nalzok

2471 silver badge9 bronze badges

0

votes

1answer

104 views

Xilinx FPGA “X” state in simulation and didn't find the bug

I wrote an ASRAM in VHDL and simulate it. I get many "X" if I try to read. I know that this problem is caused by too many drivers on one net but I didn't find the problem nor solved it. Appreciate ...

fpga vhdl simulation driver xilinx

asked Dec 5 '19 at 15:59

Marcel Skywalker

91 bronze badge

1

vote

1answer

87 views

Strategy against Side Channel Attack

I am newbie to Hardware Security. While studying Side Channel Attack, I realized that power consumption profile of electronic control unit is a key to encrypt what algorithm runs on it. I thought ...

microcontroller fpga hardware security

asked Dec 3 '19 at 8:43

emre iris

1071 silver badge7 bronze badges

0

votes

1answer

79 views

Does a program exist to draw logic signal waveform from csv data?

Assuming that I want to collect several seconds of activity of digital signal on multiple pins of a device, one way is to create a simple FPGA design that buffers all that information and then ...

fpga signal-processing datalogger

asked Dec 1 '19 at 21:01

quantum231

7,96116 gold badges66 silver badges138 bronze badges

0

votes

1answer

45 views

PIN Placement Errors In Quartus

So I am writing a simple blinking LED Verilog code that will be run on a Cyclone10 LP (Device is called 10CL025YU256I7G) and will be tested on a Cyclone 10 Evaluation Kit (6XX-44504R-0D) All code is ...

fpga verilog intel-fpga pinout quartus

asked Nov 27 '19 at 18:31

Coder Motor

111 bronze badge

1

vote

1answer

39 views

Setting Pin Assignments For Quartus

So I have written a simple Verilog module which works well in the ModelSim emulator. I would like to now program my Cyclone 10 Dev board to perform this simple task, but I need to set up the pin ...

fpga pins intel-fpga quartus

asked Nov 26 '19 at 21:47

Coder Motor

111 bronze badge

0

votes

1answer

42 views

Input CLK Keeps Showing As Hi-Z on ModelSim

I am writing some basic verilog code that blinks an LED at some frequency. The code for the design file is the following: ...

fpga verilog quartus modelsim

asked Nov 26 '19 at 20:15

Coder Motor

111 bronze badge

0

votes

1answer

36 views

I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...

fpga verilog timing quartus modelsim

asked Nov 25 '19 at 20:59

Coder Motor

111 bronze badge

0

votes

1answer

42 views

Accessing RAM on TERASIC DE0 Nano

I'm just wondering how to access more than 32Kb on a TERASIC DE0 nano. It is based on an Altera Cyclone IV FPGA. https://www.ti.com/lit/ug/tidu737/tidu737.pdf It has 32Mb DRAM but there are 12 ...

fpga ram

asked Nov 24 '19 at 22:37

cup

1234 bronze badges

2

votes

3answers

117 views

External clock with Arty Z7 FPGA development board

I have a digital audio source that is basically I2S. I need to run the FPGA at the exact clock as the I2S provides. I've got four such inputs required, but I am assuming that the clocks are the same. ...

fpga xilinx zynq

asked Nov 21 '19 at 4:59

jamie

735 bronze badges

0

votes

1answer

33 views

Software Driver for custom AXI-stream IP in Xilinx SDK

I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "...

fpga xilinx vivado zynq axi4

asked Nov 20 '19 at 0:35

user3219492

7583 silver badges9 bronze badges

0

votes

2answers

143 views

data storage, FPGA to mass storage device

For a project I am working on I need to transfer, without loss of information, continous data bursts at a maximum of 48 MB/s from an FPGA to a mass storage device. An SD card device (with appropriate ...

fpga data-storage

asked Nov 19 '19 at 13:15

simo-zz

1011 bronze badge

0

votes

1answer

40 views

TinyFPGA A series board programmer compatibility

Since the programmer writes configurations to the flash of the fpga can I use the TinyFPGA programmer for A series boards on any lcmxo2 chip? Or can I at least use it for the same chip with a ...

fpga programmer

asked Nov 18 '19 at 15:19

urw7RSeeh8FR

394 bronze badges

0

votes

2answers

62 views

VHDL - Inferred Latch With Reset - FSM

I have an issue with this process where if I include a reset statement, I get an inferred latch. However, if I do not include the reset statement, I do not get an inferred latch on duty_cycle_triangle....

fpga vhdl

asked Nov 15 '19 at 1:02

Nate

1

0

votes

2answers

103 views

Is it easier to implement sigma delta modulator in FPGA by filter or state space model?

Sigma delta modulation is extensively used in quantization to reduce quantization noise. In the literature one can see different architecture for example python-deltasigma to implement a modulator. ...

fpga signal-processing

asked Nov 13 '19 at 0:51

Creator

1159 bronze badges

0

votes

0answers

34 views

Fast Arbiters for On-Chip Network Switches

For "Fast Arbiters for On-Chip Network Switches", what is the difference between Proposed-I and Proposed-II topologies?

digital-logic fpga logic-gates

asked Nov 10 '19 at 0:36

kevin

3862 silver badges15 bronze badges

1

vote

2answers

103 views

found '0' definitions of operator “*”

I have this error when trying to compile my VHDL code. The purpose of the code is to multiply a 2 bit constant K by some 4-bit number in memory. There are some similar posts here with the same error, ...

fpga vhdl

asked Nov 7 '19 at 15:54

Eric Navarrete

235 bronze badges

3

votes

1answer

75 views

Can a non-enumerated device conduct DMA operations?

PCIe devices can read or write to memory, i.e. can do DMA without requiring a device driver. For example: pcileech (The PCIe FPGA device is controlled by another computer). If I remember correctly, if ...

fpga bus pcie

asked Nov 7 '19 at 12:45

Jordan T.

333 bronze badges

0

votes

1answer

49 views

PCI based system debuging

I've came across some products that help you troubleshoot a computer that won't POST, with listening and capturing traffic on PCI bus during system startup. They essentially know the normal procedure,...

fpga computers pcie pci

asked Nov 5 '19 at 21:13

Solid State

11 bronze badge

0

votes

0answers

67 views

VHDL - signed vs unsigned adder

I have made a four bit adder with carry-in & -out that contains an unsigned and signed architecture: ...

fpga vhdl adder

asked Nov 5 '19 at 8:37

user164324

175 bronze badges

0

votes

0answers

88 views

Is using a register chain feeding into a LFSR sufficient to generate “true random numbers” inside an FPGA?

One way to generate random numbers is to pseudo-random numbers. Otherwise, one would need a special mechanism to generate them using dedicated hardware. However, (For FPGAs specifically) why not just ...

fpga random-number

asked Oct 29 '19 at 15:35

Quantum0xE7

977 bronze badges

0

votes

1answer

50 views

How to read data from an .mif file in Vivado?

My knowledge on the subject is bare-bones. I created a .coe file and used Block Memory Generator to get an .mif file. I need to store the contents in the block memory and then use it. Following is my ...

fpga verilog vivado

asked Oct 24 '19 at 3:35

Maxsash

1334 bronze badges

0

votes

4answers

185 views

royalty free embedded processor [closed]

I got into FPGA design last year for a project, and had some success with a Xilinx Spartan 6 dev board using ISE. I could do everything with this low cost board and ISE 14, which is free. I needed an ...

fpga embedded xilinx processor spartan

asked Oct 23 '19 at 21:32

danmcb

2,0965 silver badges13 bronze badges

1

vote

0answers

83 views

Write received character from PS/2 keyboard to LCD1602

I am trying to read a pressed key from a PS/2 keyboard and display it on a LCD1602 display. I wrote one entity and architecture which detects a pressed key. If it received the 11 bits (1 start bit, 8 ...

fpga vhdl lcd character-lcd ps2

asked Oct 23 '19 at 15:54

Xhendos

191 bronze badge

0

votes

1answer

44 views

FSM modeling when outputs are not simple functions of input and current states

All the two/three process block modeling style(the recommended style) examples for FSM have logic for nextstate that is a function of current state and inputs. The outputs in these examples also take ...

fpga design system-verilog asic rtl

asked Oct 23 '19 at 7:24

Pramod

448 bronze badges

Questions tagged [fpga]

Related Tags