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Questions tagged [frequency-divider]

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Verilog code for three-storey building

Ground, first and second floors and the inputs are r0 for ground, r1 for first floor, and r2 for second floor. The output will be d1, d2, up1, up2, and n (no action). Frequency is 215 Hz. State ...
had's user avatar
  • 63
0 votes
3 answers
209 views

What is the difference between an integer frequency divider and a fractional frequency divider?

Let's say I have a 5-bit integer frequency divider first. Does this mean that I can divider my input frequency anywhere from 1 to 2^5 (or 2 to 2^5+1 as dividing by 1 doesn't make much sense)? Now let'...
sj1234's user avatar
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0 votes
1 answer
134 views

What might be killing the output to my amp, with every modification I try to make to my audio circuit?

I’ve been working on an audio project connected to a unique Stylophone-type keyboard (that I designed), using a 555 timer for the main circuit. I built a really cool box with 5 little powered outlets ...
Explorer's user avatar
1 vote
0 answers
199 views

Clock divider/ multiplier ( 3/4, x6/4, x8/4) with CD4017s and CD4046

(UPDATED SCHEMATIC) I want to make a clock divider to add to a drum machine. I made this schematics, can anyone confirm it does what it s meant to (multiply the clock from the drum machine by 3/4,6/4,...
Fuzzywill's user avatar
1 vote
4 answers
578 views

How can I change the frequency of a sine wave from 5 MHz to several smaller ones, e.g. 1kHz, 100Hz and 1Hz? [closed]

5 MHz is the frequency of the quartz based oscillator. I get a clean, sine wave output. I would like to (divide) this signal into several, lower frequencies in steps, e.g. 1kHz, 100Hz and 1Hz. I don't ...
Jerzy Przezdziecki's user avatar
1 vote
1 answer
70 views

Custom frequency divider (/timer) question [closed]

How can I make a frequency divider with multiple outputs with these conditions: no microcontroller can use up to 4 SOIC-16 chips or up to 8 SOIC-8 (or any combo) can use one crystal/oscillator 9v ...
Bikay's user avatar
  • 73
2 votes
4 answers
823 views

0 to 999 Hz frequency counter

I'm trying to build a frequency counter with a resolution of 1 Hz that will count any frequency between 0 and 999 Hz and hold that value. I've built the following in Multisim but I'm having trouble ...
Licentia's user avatar
2 votes
2 answers
697 views

CD4018 divide by 11

I am making a circuit that creates various subdivisions of input frequency by integer values from f/2 down to f/12. Division by 2, 4, 8 are straightforward using JK flip flops. Divisions by 6, 9, 12 ...
Ivan Demyachenko's user avatar
0 votes
2 answers
121 views

Why will clock signals have different phases after a frequency divider?

I have a question about data transport between two chips with series format. I have two chips. Chip 1 will sent 8-bits data to chip 2. The picture shows a solution. I will provide a 100MHz clock from ...
Alex's user avatar
  • 3
0 votes
1 answer
589 views

Flip Flop frequency divider by 17

I have a task to make frequency divider by 12, 17, 30. I have figured out how to make divider by 12 using staging dividers by 6 and staging dividers by 10. But 17 is odd number and i can't make it ...
FgSFDW's user avatar
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0 votes
2 answers
353 views

Divide Hall effect sensor input

I've made a circuit which is supposed to take the output of a Hall effect sensor and divide by 5, so that I get one pulse per revolution of a motor. The motor is a Nidec FY9S40 variant. Since the ...
Niclas's user avatar
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2 votes
1 answer
213 views

Why is the 14-stage SN74HC4020/CD74HC4020 binary counter missing 2 output pins, leaving 2 bits inaccessible?

I purchased a few SN74HC4020 ICs, which is a 14-stage ripple-carry binary counter. The SN74HC4020 datasheet shows output pins for bit 1 (pin QA) and bits 4-14 (pins QD-QN). So in other words the ...
acker9's user avatar
  • 353
0 votes
1 answer
85 views

Trying to understand clock circuit (wall clock, not signaling clock)

First of all, electronics is a new hobby for me. I don't have any formal training, so please be patient with me. Probably like many people, I picked up the interest after playing with Arduinos. I ...
nw47978's user avatar
0 votes
0 answers
53 views

N-Pulse Oscillator

I want to build a circuit which, each time a button is pressed, outputs 'N' pulses from an oscillator. I'm working on a solution which uses a flip-flop to control a switch at the output of the ...
Giesbrecht's user avatar
0 votes
0 answers
242 views

How to select between different PLL and divider configurations with same result

I'm new to STM32 and totally ARM. I'm learning STM32 by a NUCLEO-L053R8 board and currently working on clock configurations. I want to clock CPU, USB and RNG all by PLL connected to HSI16 so there is ...
AmirSina Mashayekh's user avatar
0 votes
2 answers
751 views

How can I turn ON-OFF this oscillator circuit?

On my prototype board I used an integrated oscillator which gave me the desired frequency without any extra component. Then it's being divided by a divider ic. The clock pulse going from the ...
Fredled's user avatar
  • 2,360
1 vote
1 answer
232 views

Dividing down a VHF signal in a 4046 based PLL loop

I've decided to build a a PLL based synthesiser to produce the Local Oscillator(LO) signal for my DIY transceiver. My aim is to try to use commonly available (preferably inexpensive) parts in what is ...
Buck8pe's user avatar
  • 1,694
0 votes
2 answers
217 views

Unpowered clock divider

I am not a professional in this area, so I hope I am asking questions correctly. I have a 5 V clock pulse with 50-200 Hz (square wave) and would like to build a simple unpowered clock divider. Output ...
Denis Zarubin's user avatar
1 vote
0 answers
244 views

Clock divide by 5 - All ICs obsolete?

I've got an obsolete part in a design (SY100S839VZG) that is being used to take a single 100MHz clk and divide it down into two PECL p/n pairs. For the life of me, I cannot seem to find a single ...
Daniel's user avatar
  • 39
1 vote
4 answers
179 views

Using a 555 timer and 14-stage binary divider for 2 hour timing circuit

I am researching how to design a timing circuit that will activate a relay with a push button and deactivate the relay after two hours. My understanding is that I can feed the output of a 555 timer to ...
gahigg1's user avatar
  • 13
1 vote
1 answer
95 views

Review of my LED spinner Schematic

After a few months of questions and modifications to my design. I have what I believe to be a LED Spinner that can change the speed of the spinning LED. Before I send this design off to get printed on ...
Francois landry's user avatar
-1 votes
1 answer
3k views

Clock frequency divider circuit (divide by 2) using D flip flop

I was trying to implement frequency divider by 2 using D flip flop with the logic connection of ~Q to D input. I provide 2x clock frequency of 50% Duty cycle in the hardware where D flip flop is made ...
kundrapu tarunkumar's user avatar
3 votes
1 answer
180 views

Frequency Divider Analog Circuit issue

I am trying to implement a divide-by-two circuit quoted from the book "Low power CMOS circuits : technology logic design and CAD tools" by Christian Piguet Could anyone advise about the spice error "...
kevin998x's user avatar
  • 413
2 votes
3 answers
810 views

Why include frequency dividers in this PLL circuit?

I found replicated in few sites this PLL diagram and I'm wondering why the authors included frequency dividers on the input and output signal, since the two signals to be compared have the same ...
Gianluca G's user avatar
1 vote
0 answers
678 views

How to cascade frequency dividers

I'm implementing some modules using VHDL and for some of them I need the FPGA's global clock signal, and for some others I need to update to two different frequencies. A common solution to this is ...
SrJaimito's user avatar
  • 191
-1 votes
2 answers
444 views

How to correct voltage overshoot in clock divider output?

I am trying to make a quadrature phase divide-by-6 clock divider circuit in cadence. I managed to complete the circuit and obtained the correct waveform; however, due to some reason I am getting a ...
viliyar's user avatar
  • 123
-2 votes
1 answer
457 views

Verilog code for frequency divider 2 [closed]

I have to write a code for frequency divider from 161.24MHz to 8KHz in Verilog. Please help to write a code.
SAURAV's user avatar
  • 1
2 votes
1 answer
790 views

CD4521 frequency divider warms up while RESET is HIGH

I have a peculiar problem involving the CD4521 frequency divider of which I use two in a redundant configuration as shown in my schematic snippet below: I noticed that while the devices are held ...
wheezardth's user avatar
0 votes
0 answers
1k views

is it possible to use the CD4013 IC inverted output while in frequency divider setup ?

I am not having success with using the "not Q" output of the CD4013 http://www.ti.com/lit/ds/symlink/cd4013b.pdf when the CD4013 is connected for frequency dividing as below: I need both Q and "not Q"...
Manu de Hanoi's user avatar
2 votes
3 answers
3k views

Why is a 15 stage binary counter/divider so cumbersome?

There seem to be many ways to take a 32.768kHz signal and turn it into 1Hz. I can use a CD4060, but still have to add a flip-flop... so 2 "large" chips with excess (potentially) unused functions ...
Jay's user avatar
  • 359
4 votes
1 answer
77k views

Divide clock frequency by 3 with 50% duty cycle by using a Karnaugh Map?

In this document, On semiconductor describe how to design a divide by 3 system using a Karnaugh Map: ...
nettek's user avatar
  • 1,055
0 votes
2 answers
5k views

What is the difference between 7474 and 7479 ICs? How do they differ from 4013?

I am hobbyist and am looking to reduce signal frequency using D type flip flops. I have a circuit diagram for a 4013 IC but I would like to use a 74HC74 instead and I do not understand if it is ...
Greg's user avatar
  • 123
-1 votes
1 answer
282 views

Sequential Clock divider

I'm new to VHDL programming. I want to have frequency divider of an input clock signal by 2 consecutive integer x, y each of them last for 2 cycles. Actually I wrote it only for x. How can have ...
Ehsan's user avatar
  • 1
0 votes
3 answers
176 views

draw out as frequency divider from circuit

I have this circuit and I have to get the out "S" but have no idea how The initial condition is D0 and Q1 = 0 And i just have what I guess is q0, and with that i supposse S is 0 and then all 1, but ...
user3810795's user avatar
1 vote
1 answer
472 views

FPGA Frequency Divider

I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? ...
Min_ah's user avatar
  • 23
0 votes
2 answers
418 views

High-voltage frequency divider

How can a frequency divider for high voltages be implemented? Is it possible to make it cheap and compact? An application would be to mount it between the output of fluorescent lamp ballasts (...
Mehdi's user avatar
  • 113
2 votes
1 answer
645 views

Simple logic circuit to filter out the even numbered pulse?

I need a logic circuit to have a function as shown in the figure: An input signal applied to the input end, I want it to only output the odd numbered pulse and output 0 for the even numbered pulse. ...
Jing's user avatar
  • 123
5 votes
3 answers
5k views

Odd number frequency divider

Important note: You are not helping me do my homework. This is for a competition for engineering students, that encourages you to "use your network" ;) I've got this pattern for a frequency divider ...
LasseValentini's user avatar