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Questions tagged [hdl]

HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

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Why we need non-blocking assignments in Verilog?

I understand the basics of blocking and non-blocking assignments in verilog. I understand that blocking assignments execute in a sequential manner,whereas it is possible to assign values concurrently ...
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52 views

Verilog if else if construct

I have verilog code that looks like this begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end ...
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1answer
46 views

Why is 7:1 video serialization required?

I am trying to migrate portions of a ZYNQ design from one platform to another. Part of the project is based on Avnet's ALI3 touchscreen kit. From the docs: The 7-inch Zed Touch Display Kit includes ...
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1answer
59 views

Too many ports expected in verilog? [duplicate]

I get an error saying i have to many port connections when I try to model sim, but clearly I have the right amount. Whats wrong with my design ?? As you can see the error appears in line line 16 of ...
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69 views

Are nested modules allowed in Verilog?

module A (input a, input b) ... module B (input a, input b) ... endmodule endmodule Is the above allowed in Verilog?
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35 views

Instantiating modules in SystemVerilog

This is a picture of a system that I am building: (original) I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
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1answer
250 views

Unknown Formal Identifier in VHDL

I am facing an error with my VHDL code. I am new in it. After putting so much of my time I am even unable to resolve this error. I am using ModelSim software for it. Here is my code: ...
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107 views

Can I use 8 bits out of 16 bits as signed bits in verilog?

Generally Verilog takes the first bit of any bit pattern as signed bit. I know that -4 can be represented in signed representation as ...
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1answer
67 views

Can I use custom data types to exchange data between modules in VHDL?

I'm new to VHDL and currently try to get more complex data types working, so that code becomes more readable... However, it seems that I cannot define a type in VHDL before the ...
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104 views

I write this module to arithmetic shift to left and right in verilog

this is my code: module zero(out,A,B); output signed[5:0] out; input signed[5:0] A,B; assign out = A[5:0]<<<2 + B[5:0]>>>1; endmodule ...
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98 views

HDL code convention for register resets

When it comes to (synchronously) resetting registers in HDL (I'll use Verilog), is it considered bad practice to code the reset combinatorially? As far as I can tell, the following two snippets are ...
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1answer
98 views

Are there CPLD / FPGA toolchains and workflows that bypass vendor IDEs? [duplicate]

Custom programming for FPGA boards is a similar and helpful question for any with the same as this, but they are different. In that thread they discuss custom options and building their own. This ...
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1answer
81 views

Clock frequency of FPGA circuit and 4-bit counter [closed]

I have implemented a 4 bit counter using HDL. Now I have downloaded the code to an FPGA kit with a 50 Mhz oscillator. This means that the clock period will be equal to 0.02 microseconds and ...
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86 views

Strange behavior in VHDL design (randomly incrementing values)

I have a fairly simple VHDL design that looks like the following: ...
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1answer
26 views

Can specific pipeline latency arithmatic block be inferred when using * or / operator in VHDL?

When using the * or / in VHDL, the synthesis tool shall infer the appropriate IP block to carry out that operation. If we open the actual GUI for that IP block we can find a lot of options e.g select ...
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1answer
107 views

What is the proper methodology to create portable FPGA designs?

FPGA designs may contain RTL along with IP blocks. These IP blocks most likely shall be from the vendor of the FPGA. Examples of such IP blocks are instantiating dual clock FIFOs, floating point and ...
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110 views

(System)Verilog: extracting a smaller bus/vector from a larger bus?

What is the best practice for creating a bus, which is just extraction of certain bits of a larger bus. I do not want to store the index numbers to make the lookup in the generate-for if it could be ...
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1answer
143 views

How to compare a re-writable 4 bit value to a given 4 bit input in Verilog?

The goal of this project to design a computational lock alarm in Verilog to be run on an Altera board (note on the board 0 is actually ON and 1 is OFF). Based on the design criteria I created a state ...
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2answers
108 views

How to get the MSB into a logic gate which will check if a number is negative or not?

I need to create a logic gate which will find out whether a number is negative or not. The input is 8 bits and the output is 1 bit, and if the input is 1 (i.e. negative number) then the output ...
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317 views

Variable input MUX in Verilog

What's the best way to make an N:1 multiplexer in Verilog (NOT SystemVerilog), where the maximum N is 64? Each input is 32-bits wide and there are N such inputs. Verilog doesn't allow two-dimensional ...
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1answer
76 views

How to have an in-system check in an FPGA based system that it has been reset?

I have a system based on Altera's MAX10 device that is doing the following tasks: receives the data and stores it on an on-chip flash memory only once. reads all the data from on-chip flash, stores ...
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1answer
534 views

Vivado simulation stuck at 0 fs

I am trying to simulate a D flip flop using Vivado 2018.2.2. But upon running the simulation a window pops up stating Current time: 0 fs. The program doesn't freeze, it just doesn't progress. Here is ...
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215 views

Net type, variable type, data type and data objects

I am really confused by the conception of net type, variable type, data type and data objects in SystemVerilog. I am using the simulator inside Xilinx Vivado 2018.02 for all the following codes. <...
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1answer
59 views

Can demultiplexers be synthesized?

In my digital design module involving HDL (Verilog) and a ton of RTL diagrams, our lecturer always said never to use demultiplexers because they do not exist. Why is that?
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68 views

How exactly does $cast work

When a $cast is executed between a base and a derived class objects, does it allocate more memory for the derived class handle? ...
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3answers
143 views

What exactly lies between an HDL and a circuit?

I'm trying to learn basics of hardware design process to get a better understanding of how CPUs, microcontrollers etc work and how are they made. My googleing gave me many articles with info like "...
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75 views

how to trigger another clk in mainclk (verilog)

I wrote somekind of prescaler in verilog to make sclk_adc signal from clk_i. by now my code looks like: always @(posedge clk_i) begin //generation of sclk_adc end ...
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191 views

Xilinx ZYNQ/ARTIX7 Invert Clock without inducing skew

For HDL design I'm currently developing for a zynq SoC, I need to invert a clock signal because of a swapped differential pair on board level. Using "NOT" to invert adds a LUT in the path and as ...
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1answer
165 views

Using compiler directives and macros in verilog, how to use multiple macros conditionally in verilog?

I have 2 macros in verilog used them as below. ...
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2answers
85 views

How to model electric power consumption in verilog-a?

I am modeling an analog device using verilog-a (to which I am quite new). I would like the model to match the power consumption of the physical device, for which the energy cost associated with state ...
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0answers
75 views

FSM was struck between two states only!

I'm writing an fsm which is struck between s1 and s2 and not going to next state. Even if I increase the delay after s3 ( for it to complete operation). I even observed the simulation that the data ...
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1answer
179 views

Problem relating to FSM machine

I am trying to write a verilog code for a Fibonacci sequence generator. It's output will be nth Fibonacci number where n is the output of the count. The code works for count = 2. But when the count ...
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3answers
93 views

Generate if-for statement

Can we declare Generate if-for statement? ...
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1answer
257 views

Initial Block is Sythesizable!

I came across a lot of posts saying that initial block is not synthesizable in Verilog HDL.Even I followed the standard reference (https://link.springer.com/content/pdf/bbm%3A978-81-322-2791-5%2F1.pdf)...
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209 views

Will temp variable in always_comb create latch

I have following code snippet where a temp variable is used to count number of 1s in an array: ...
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4answers
202 views

Generation of non overlapping clocks on FPGA using VHDL

I am trying to implement switched capacitor circuits and I hence need to generate a two-phase non-overlapping clock. I have been trying to use an FPGA for the same. Unfortunately, my synthesis tool- ...
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1answer
120 views

Best practice for synchronizing VHDL stimuli with circuit

What is the best practice or method for synchronizing stimuli input and output with a sequential logic block in VHDL? I am currently running only behavioral simulations, but I want to make sure my ...
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1answer
79 views

VHDL does not have built in capability to read binary files, do Verilog and SystemVerilog have it?

Reading and writing binary files in VHDL is not straightforward, I am not sure why this is so. I think that Verilog and SystemVerilog are more closer to C. Do they have built in capability to read/...
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Verilog-A Current/Voltage/Power Inconsistency

I'm simulating a phase change material in Verilog-A and need to calculate the power across the material. The material is a resistor, so it satisfies Ohm's Law. Therefore, P = IV = (I^2)R = (V^2)/R ...
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3answers
651 views

iverilog unable to bind parameter

When using iverilog to compile a script I get the following error: ...
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2answers
62 views

Change memory content of FPGA SoC (DE1-SoC) using software while .sof (EPCQ) is running on FPGA

I am new to FPGA and FPGA-SoC world. I have a DE1-SoC board. I am doing a project. Hardware design of the project contains a memory block which is initialized using .mif file. I know that we can use ...
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5answers
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Will the High-Level Synthesis (HLS) design approach for FPGAs reduce the demand for RTL designers? [closed]

I'm a senior electrical engineering student who's very interested in FPGAs and RTL design. But recently after learning what HLS compilers are capable of I had to consider the possibility that ...
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1answer
98 views

VHDL - Can you produce an output corresponding to the input if the input changed in the same clock cycle?

In VHDL, if we have a system where the output changes depending on a variable that changes with the input. Say the output has 2 modes and an input switches between them. In the same clock cycle, can ...
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1answer
66 views

Cannot extract expected values in VHDL at first clock cycle

The VHDL design below is supposed to extract the Nth bits from the four values x_0, x_1, x_2 and x_3 and create a new value at every clock but this is not happening. Find below the design and the ...
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1answer
259 views

Can I connect all my components in my top level entity

I have finished writing a project with separate VHDL files. Most of the components have connections directly to the FPGA ( which I have instantiated and connected in the top level file) but a few do ...
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2answers
347 views

in what order does a VHDL program run in an FPGA

I am trying to wrap my head around exactly what goes on in an FPGA when I program it, specifically using VHDL. I know all code outside processes run concurrently but what about processes in different ...
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1answer
192 views

How to modify input wires before sending them as input in another modules?

I want to design a 8 bit adder-subtracter in verilog. when cin is 1, it should add 2 numbers, when 0, it should subtracts. For performing subtraction, I said to add number1 and ~number2 and 1. here ...
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0answers
56 views

Structure Identification in HDL codes

I wanted to automatically Identify some structures in HDL code (Verilog/VHDL), let say an adder. I need to automatically detect how many adders in the design. I am not sure from where to start, should ...
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1answer
123 views

Altera HDL design techniques

Some many years ago my teacher taught us to program Xilinx Spartan II development board. He taught us to think of the hardware element we wanted to invoke (logic gate, adder, shift register, etc) and ...
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1answer
551 views

using generate statement in verilog

I am using nested for loops using generate module for creating multiple instances of sub-modules in verilog this is for finding 4x4 determinant. I generated the sub-modules with inputs given ...