Questions tagged [hdl]

HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

Filter by
Sorted by
Tagged with
0
votes
2answers
53 views

Clock usage in the always block and in the event

In general, if we are working on a sequential circuit, say a Flip Flop (e.g. D Flip Flop) The code we write for the always block part is: ...
0
votes
0answers
48 views

Synchronizing an asynchronous interface without a clock

I am trying to implement a custom bridge between a clocked synchronous interface and an asynchronous interface which is not clocked. I am having difficuties in synchronizing the asnychronous interface....
1
vote
1answer
55 views

Is this the correct truth table to determine whether or not to execute an interrupt in a RISC V system?

I'm working on implementing the privileged RISC V ISA, which can be found here. I'm looking at the bottom of page 20, and the interrupt conditions are stated very confusingly: Global interrupt-...
0
votes
0answers
31 views

HDL code for a wrapper or resizer between AMBA APB bus (32-bit) and the FPGA Fabric design (128-bit variable)

The design is implemented on a System On Chip (SoC) The processor is Cortex-M3 32-bit which is interfaced to an FPGA fabric where a processing of some variables will take place. The variables are ...
0
votes
1answer
61 views

How does assignment work in Verilog?

I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...
0
votes
0answers
37 views

VS Code with Lattice Diamond (FPGA)

a little diffrent question, Have here someone who using Lattice Diamond software together with VS Code or maybe its relevant to any external text editor. I changed the default text editor to VS ...
1
vote
2answers
46 views

Is it possible to have a register with multiple drivers?

This is just a theoretical question I have. Imagine we have a register (a reg signal in Verilog for example) and two possible inputs that have to write to that register. I am assuming all signals are ...
1
vote
3answers
75 views

Using too many Modules in Verilog affect timing?

I have a straightforward quest about HDL and FPGA design. If I seperate my code to a lot of modules, by modules I mean verilog files which do specifig things instead of writing close to the top ...
0
votes
0answers
19 views

Process does not work as it should (VHDL)

As far as I know, in order to change the output, one of the inputs in the sensitivity list should be changed too. If one of the inputs is left out of the sensitivity list, then the FPGA board should ...
0
votes
3answers
48 views

Why to use signal in this VHDL code?

Here is my code for 4 to 1 mux: ...
0
votes
1answer
48 views

Help on writing test bench for up counter in verilog

preamble: I think I have enough understanding of logic circuits and enough experience in programming from other languages(C, python, etc.) However, I am very new at Verilog and also have never used ...
0
votes
1answer
63 views

Open source CPU HDL decriprion? [closed]

I'd like to get familar with an implemebtaion of modern CPUs. Are there Amy processors with an open-source Hardware Decriprion Language? Perfectlt, I'd like to take a look at Intel/AMD implemebtaion, ...
-3
votes
2answers
66 views

Verilog: Can't resolve multiple constant drivers for net

I am writing a code sung Quartus IDE: The following is my code: ...
1
vote
3answers
131 views

Verilog code “always @” block not working as expected

My Verilog code samples the input (Vin) at fixed intervals using a counter. The counter is a 2-bit register whose value increments at every positive edge of a clock ...
1
vote
1answer
54 views

3-Stage Shift Register using Blocking assignment in Verilog - Differences among simulators

Simulation of a 3-stage shift register using blocking assignment statement in Verilog gives different simulation results across simulators: The RTL code is as follows: ...
0
votes
0answers
43 views

Dynamic Huffman Compression FPGA: How to implement

I wanted to create a dynamic huffman decoder that has data formatted according to RFC 1951 and output decoded data for an LZ77 module. So far, after getting the lengths for the code length alphabet, I ...
-1
votes
1answer
144 views

How is AI being used these days in designing ASIC? [closed]

Is AI used in HDL synthesis or design? For example, I would imagine that the process of place-and-route could benefit tremendously from the past decade developments in AI and Deep Learning. How do ...
0
votes
1answer
81 views

How to generate signal who have value less then one clk in vhdl? [closed]

How to generate signal who have value less then one clk in vhdl? Signal req is generate base on input signal dat1 and dat2. If they are equals, signal req have value of 1 less then one clk. On ...
0
votes
2answers
164 views

Why would this cause a latch?

I'm reading ZipCPU's tutorial and got confused. Specifically, I'm referring to this page. To transcribe the Verilog code: ...
0
votes
1answer
107 views

What kind of FSM is it, if outputs depend on internally generated signals?

The classical definitions are that in a Moore machine the outputs depend only on the state, while in a Mealy machine they are also allowed to depend on inputs. But what if outputs and/or state ...
0
votes
0answers
17 views

Finding duplicate reference designators in Design Entry HDL Schematic

This is related to Allegro Design entry HDL schematic. we have imported few pages from other design to current design and Integrated to current design. Because of that we saw few reference ...
0
votes
1answer
161 views

How to implement 32-bit adder logic using two 16-bit adders?

I've been trying to implement a 32-bit adder by instantiating two 16-bit adders. The code is compiling but failing some test cases. I don't know what is going wrong in this. verilog code ...
0
votes
2answers
160 views

Verilog latch occurring with instantiating modules with in a generate statement

I am trying to create a register file in Verilog. To do this, I am instantiating multiple instances of a register module I designed in a generate statement. Each module uses a different input and ...
2
votes
3answers
369 views

Verilog: negative value in brackets of vector signal definition

I am looking at the code in the following website. https://www.csee.umbc.edu/~tinoosh/cmpe641/slides/05-Memories.pdf In their code, they claims something like input signed [7:-12] c_in; I am ...
0
votes
1answer
50 views

Two questions about testing with HDL designer

I hope it's okay to ask about specific programs here. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through ...
2
votes
2answers
83 views

“Increase” of a register in VHDL and hardware synthesis

Suppose you have already defined a register (for instance called "reg") in VHDL, for instance as a vectors of 4 bit. Now consider the operation: reg <= reg + 0001; it is like reg ++ in C. My ...
3
votes
3answers
351 views

VHDL process' sensitivity list

I do not understand the precise role of the sensitivity list in a process in VHDL. For instance, consider an architecture with 3 input signals: a, b, c. I read that if we write: PROCESS (a, b) we ...
0
votes
1answer
211 views

SystemVerilog FIFO problem with 6 bits in and 4 bits out

I was trying to induce the following functionality into SystemVerilog but i cant think of any efficient ways: So above is a picture of two 6-bit input packets that come one after the other (triggered ...
0
votes
4answers
216 views

How to avoid big mux in RTL design?

When doing rtl design, mux is always used to select the input of a block/module, for example: ...
0
votes
1answer
140 views

How to automate Instantiation of modules in Verilog? (permutation)

Consider this file tb_sr_latch.v: ...
0
votes
1answer
43 views

create sr_latch from gates in verilog

consider this file : tb_sr_latch.v ...
0
votes
1answer
150 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in ...
4
votes
3answers
800 views

VHDL: is there a way to create an entity into which constants can be passed?

Lets say we want to create a generic t flip flop counter, the structure of this kind of counter is perfectly repetitive, and you can synthesize one with arbitrary length just using a ...
0
votes
2answers
862 views

Are Verilog if blocks executed sequentially or concurrently?

I'm learning Verilog with some background in VHDL and C. I would like to know if Verilog if blocks are executed concurrently or not, and if this is IDE- or vendor-dependent. For example, are the ...
1
vote
2answers
244 views

Why we need non-blocking assignments in Verilog?

I understand the basics of blocking and non-blocking assignments in verilog. I understand that blocking assignments execute in a sequential manner,whereas it is possible to assign values concurrently ...
1
vote
1answer
161 views

Verilog if else if construct

I have verilog code that looks like this begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end ...
0
votes
1answer
108 views

Why is 7:1 video serialization required?

I am trying to migrate portions of a ZYNQ design from one platform to another. Part of the project is based on Avnet's ALI3 touchscreen kit. From the docs: The 7-inch Zed Touch Display Kit includes ...
-2
votes
1answer
196 views

Too many ports expected in verilog? [duplicate]

I get an error saying i have to many port connections when I try to model sim, but clearly I have the right amount. Whats wrong with my design ?? As you can see the error appears in line line 16 of ...
1
vote
2answers
686 views

Are nested modules allowed in Verilog?

module A (input a, input b) ... module B (input a, input b) ... endmodule endmodule Is the above allowed in Verilog?
0
votes
2answers
127 views

Instantiating modules in SystemVerilog

This is a picture of a system that I am building: (original) I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
-1
votes
1answer
2k views

Unknown Formal Identifier in VHDL

I am facing an error with my VHDL code. I am new in it. After putting so much of my time I am even unable to resolve this error. I am using ModelSim software for it. Here is my code: ...
-1
votes
2answers
582 views

Can I use 8 bits out of 16 bits as signed bits in verilog?

Generally Verilog takes the first bit of any bit pattern as signed bit. I know that -4 can be represented in signed representation as ...
1
vote
1answer
387 views

Can I use custom data types to exchange data between modules in VHDL?

I'm new to VHDL and currently try to get more complex data types working, so that code becomes more readable... However, it seems that I cannot define a type in VHDL before the ...
0
votes
1answer
220 views

I write this module to arithmetic shift to left and right in verilog

this is my code: module zero(out,A,B); output signed[5:0] out; input signed[5:0] A,B; assign out = A[5:0]<<<2 + B[5:0]>>>1; endmodule ...
1
vote
3answers
124 views

HDL code convention for register resets

When it comes to (synchronously) resetting registers in HDL (I'll use Verilog), is it considered bad practice to code the reset combinatorially? As far as I can tell, the following two snippets are ...
1
vote
1answer
272 views

Are there CPLD / FPGA toolchains and workflows that bypass vendor IDEs? [duplicate]

Custom programming for FPGA boards is a similar and helpful question for any with the same as this, but they are different. In that thread they discuss custom options and building their own. This ...
1
vote
1answer
118 views

Clock frequency of FPGA circuit and 4-bit counter [closed]

I have implemented a 4 bit counter using HDL. Now I have downloaded the code to an FPGA kit with a 50 Mhz oscillator. This means that the clock period will be equal to 0.02 microseconds and ...
0
votes
2answers
132 views

Strange behavior in VHDL design (randomly incrementing values)

I have a fairly simple VHDL design that looks like the following: ...
0
votes
1answer
30 views

Can specific pipeline latency arithmatic block be inferred when using * or / operator in VHDL?

When using the * or / in VHDL, the synthesis tool shall infer the appropriate IP block to carry out that operation. If we open the actual GUI for that IP block we can find a lot of options e.g select ...
3
votes
1answer
142 views

What is the proper methodology to create portable FPGA designs?

FPGA designs may contain RTL along with IP blocks. These IP blocks most likely shall be from the vendor of the FPGA. Examples of such IP blocks are instantiating dual clock FIFOs, floating point and ...

1
2 3 4 5