The Stack Overflow podcast is back! Listen to an interview with our new CEO.

Questions tagged [hdl]

HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

Filter by
Sorted by
Tagged with
2
votes
3answers
55 views

Verilog: negative value in brackets of vector signal definition

I am looking at the code in the following website. https://www.csee.umbc.edu/~tinoosh/cmpe641/slides/05-Memories.pdf In their code, they claims something like input signed [7:-12] c_in; I am ...
0
votes
1answer
44 views

Two questions about testing with HDL designer

I hope it's okay to ask about specific programs here. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through ...
2
votes
2answers
76 views

“Increase” of a register in VHDL and hardware synthesis

Suppose you have already defined a register (for instance called "reg") in VHDL, for instance as a vectors of 4 bit. Now consider the operation: reg <= reg + 0001; it is like reg ++ in C. My ...
2
votes
3answers
70 views

VHDL process' sensitivity list

I do not understand the precise role of the sensitivity list in a process in VHDL. For instance, consider an architecture with 3 input signals: a, b, c. I read that if we write: PROCESS (a, b) we ...
0
votes
1answer
84 views

SystemVerilog FIFO problem with 6 bits in and 4 bits out

I was trying to induce the following functionality into SystemVerilog but i cant think of any efficient ways: So above is a picture of two 6-bit input packets that come one after the other (triggered ...
0
votes
4answers
88 views

How to avoid big mux in RTL design?

When doing rtl design, mux is always used to select the input of a block/module, for example: ...
0
votes
1answer
97 views
0
votes
1answer
35 views

create sr_latch from gates in verilog

consider this file : tb_sr_latch.v ...
0
votes
1answer
67 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in ...
4
votes
3answers
774 views

VHDL: is there a way to create an entity into which constants can be passed?

Lets say we want to create a generic t flip flop counter, the structure of this kind of counter is perfectly repetitive, and you can synthesize one with arbitrary length just using a ...
0
votes
2answers
177 views

Are Verilog if blocks executed sequentially or concurrently?

I'm learning Verilog with some background in VHDL and C. I would like to know if Verilog if blocks are executed concurrently or not, and if this is IDE- or vendor-dependent. For example, are the ...
1
vote
2answers
93 views

Why we need non-blocking assignments in Verilog?

I understand the basics of blocking and non-blocking assignments in verilog. I understand that blocking assignments execute in a sequential manner,whereas it is possible to assign values concurrently ...
1
vote
1answer
68 views

Verilog if else if construct

I have verilog code that looks like this begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end ...
0
votes
1answer
57 views

Why is 7:1 video serialization required?

I am trying to migrate portions of a ZYNQ design from one platform to another. Part of the project is based on Avnet's ALI3 touchscreen kit. From the docs: The 7-inch Zed Touch Display Kit includes ...
-2
votes
1answer
73 views

Too many ports expected in verilog? [duplicate]

I get an error saying i have to many port connections when I try to model sim, but clearly I have the right amount. Whats wrong with my design ?? As you can see the error appears in line line 16 of ...
0
votes
2answers
211 views

Are nested modules allowed in Verilog?

module A (input a, input b) ... module B (input a, input b) ... endmodule endmodule Is the above allowed in Verilog?
0
votes
2answers
46 views

Instantiating modules in SystemVerilog

This is a picture of a system that I am building: (original) I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
-1
votes
1answer
637 views

Unknown Formal Identifier in VHDL

I am facing an error with my VHDL code. I am new in it. After putting so much of my time I am even unable to resolve this error. I am using ModelSim software for it. Here is my code: ...
-1
votes
2answers
172 views

Can I use 8 bits out of 16 bits as signed bits in verilog?

Generally Verilog takes the first bit of any bit pattern as signed bit. I know that -4 can be represented in signed representation as ...
1
vote
1answer
144 views

Can I use custom data types to exchange data between modules in VHDL?

I'm new to VHDL and currently try to get more complex data types working, so that code becomes more readable... However, it seems that I cannot define a type in VHDL before the ...
0
votes
1answer
143 views

I write this module to arithmetic shift to left and right in verilog

this is my code: module zero(out,A,B); output signed[5:0] out; input signed[5:0] A,B; assign out = A[5:0]<<<2 + B[5:0]>>>1; endmodule ...
0
votes
3answers
109 views

HDL code convention for register resets

When it comes to (synchronously) resetting registers in HDL (I'll use Verilog), is it considered bad practice to code the reset combinatorially? As far as I can tell, the following two snippets are ...
1
vote
1answer
140 views

Are there CPLD / FPGA toolchains and workflows that bypass vendor IDEs? [duplicate]

Custom programming for FPGA boards is a similar and helpful question for any with the same as this, but they are different. In that thread they discuss custom options and building their own. This ...
1
vote
1answer
93 views

Clock frequency of FPGA circuit and 4-bit counter [closed]

I have implemented a 4 bit counter using HDL. Now I have downloaded the code to an FPGA kit with a 50 Mhz oscillator. This means that the clock period will be equal to 0.02 microseconds and ...
0
votes
2answers
97 views

Strange behavior in VHDL design (randomly incrementing values)

I have a fairly simple VHDL design that looks like the following: ...
0
votes
1answer
26 views

Can specific pipeline latency arithmatic block be inferred when using * or / operator in VHDL?

When using the * or / in VHDL, the synthesis tool shall infer the appropriate IP block to carry out that operation. If we open the actual GUI for that IP block we can find a lot of options e.g select ...
3
votes
1answer
115 views

What is the proper methodology to create portable FPGA designs?

FPGA designs may contain RTL along with IP blocks. These IP blocks most likely shall be from the vendor of the FPGA. Examples of such IP blocks are instantiating dual clock FIFOs, floating point and ...
0
votes
2answers
195 views

(System)Verilog: extracting a smaller bus/vector from a larger bus?

What is the best practice for creating a bus, which is just extraction of certain bits of a larger bus. I do not want to store the index numbers to make the lookup in the generate-for if it could be ...
0
votes
1answer
243 views

How to compare a re-writable 4 bit value to a given 4 bit input in Verilog?

The goal of this project to design a computational lock alarm in Verilog to be run on an Altera board (note on the board 0 is actually ON and 1 is OFF). Based on the design criteria I created a state ...
0
votes
2answers
169 views

How to get the MSB into a logic gate which will check if a number is negative or not?

I need to create a logic gate which will find out whether a number is negative or not. The input is 8 bits and the output is 1 bit, and if the input is 1 (i.e. negative number) then the output ...
0
votes
0answers
513 views

Variable input MUX in Verilog

What's the best way to make an N:1 multiplexer in Verilog (NOT SystemVerilog), where the maximum N is 64? Each input is 32-bits wide and there are N such inputs. Verilog doesn't allow two-dimensional ...
0
votes
1answer
80 views

How to have an in-system check in an FPGA based system that it has been reset?

I have a system based on Altera's MAX10 device that is doing the following tasks: receives the data and stores it on an on-chip flash memory only once. reads all the data from on-chip flash, stores ...
0
votes
1answer
812 views

Vivado simulation stuck at 0 fs

I am trying to simulate a D flip flop using Vivado 2018.2.2. But upon running the simulation a window pops up stating Current time: 0 fs. The program doesn't freeze, it just doesn't progress. Here is ...
0
votes
1answer
312 views

Net type, variable type, data type and data objects

I am really confused by the conception of net type, variable type, data type and data objects in SystemVerilog. I am using the simulator inside Xilinx Vivado 2018.02 for all the following codes. <...
1
vote
1answer
59 views

Can demultiplexers be synthesized?

In my digital design module involving HDL (Verilog) and a ton of RTL diagrams, our lecturer always said never to use demultiplexers because they do not exist. Why is that?
0
votes
1answer
101 views

How exactly does $cast work

When a $cast is executed between a base and a derived class objects, does it allocate more memory for the derived class handle? ...
0
votes
3answers
171 views

What exactly lies between an HDL and a circuit?

I'm trying to learn basics of hardware design process to get a better understanding of how CPUs, microcontrollers etc work and how are they made. My googleing gave me many articles with info like "...
0
votes
2answers
80 views

how to trigger another clk in mainclk (verilog)

I wrote somekind of prescaler in verilog to make sclk_adc signal from clk_i. by now my code looks like: always @(posedge clk_i) begin //generation of sclk_adc end ...
2
votes
2answers
248 views

Xilinx ZYNQ/ARTIX7 Invert Clock without inducing skew

For HDL design I'm currently developing for a zynq SoC, I need to invert a clock signal because of a swapped differential pair on board level. Using "NOT" to invert adds a LUT in the path and as ...
-1
votes
1answer
274 views

Using compiler directives and macros in verilog, how to use multiple macros conditionally in verilog?

I have 2 macros in verilog used them as below. ...
0
votes
2answers
116 views

How to model electric power consumption in verilog-a?

I am modeling an analog device using verilog-a (to which I am quite new). I would like the model to match the power consumption of the physical device, for which the energy cost associated with state ...
0
votes
0answers
75 views

FSM was struck between two states only!

I'm writing an fsm which is struck between s1 and s2 and not going to next state. Even if I increase the delay after s3 ( for it to complete operation). I even observed the simulation that the data ...
0
votes
1answer
193 views

Problem relating to FSM machine

I am trying to write a verilog code for a Fibonacci sequence generator. It's output will be nth Fibonacci number where n is the output of the count. The code works for count = 2. But when the count ...
1
vote
3answers
105 views

Generate if-for statement

Can we declare Generate if-for statement? ...
3
votes
1answer
344 views

Initial Block is Sythesizable!

I came across a lot of posts saying that initial block is not synthesizable in Verilog HDL.Even I followed the standard reference (https://link.springer.com/content/pdf/bbm%3A978-81-322-2791-5%2F1.pdf)...
0
votes
1answer
331 views

Will temp variable in always_comb create latch

I have following code snippet where a temp variable is used to count number of 1s in an array: ...
2
votes
4answers
246 views

Generation of non overlapping clocks on FPGA using VHDL

I am trying to implement switched capacitor circuits and I hence need to generate a two-phase non-overlapping clock. I have been trying to use an FPGA for the same. Unfortunately, my synthesis tool- ...
1
vote
1answer
157 views

Best practice for synchronizing VHDL stimuli with circuit

What is the best practice or method for synchronizing stimuli input and output with a sequential logic block in VHDL? I am currently running only behavioral simulations, but I want to make sure my ...
1
vote
1answer
100 views

VHDL does not have built in capability to read binary files, do Verilog and SystemVerilog have it?

Reading and writing binary files in VHDL is not straightforward, I am not sure why this is so. I think that Verilog and SystemVerilog are more closer to C. Do they have built in capability to read/...
0
votes
0answers
32 views

Verilog-A Current/Voltage/Power Inconsistency

I'm simulating a phase change material in Verilog-A and need to calculate the power across the material. The material is a resistor, so it satisfies Ohm's Law. Therefore, P = IV = (I^2)R = (V^2)/R ...