Questions tagged [hdl]

HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

Filter by
Sorted by
Tagged with
0 votes
1 answer
64 views

Are there other examples of applications of a priority arbiter apart from sharing system bus or memory?

I was wondering where else a priority arbiter is used in the real world, apart from sharing a system bus or memory. I tried googling, but couldn't find any other examples. For context: I'm working on ...
  • 21
0 votes
2 answers
99 views

Are SR latches bad in ASIC design?

I am implementing an ASIC design, and my current solution for a problem requires an SR latch. I've always been told that latches are bad in FPGA and ASIC designs, but never got a proper answer as to ...
  • 103
0 votes
1 answer
58 views

Verilog counter is not working using @always statement

I am trying to implement counter using Verilog HDL ...
  • 3
1 vote
1 answer
91 views

Dense Neuron Neural Network in Verilog

I am trying to build NN in system verilog, but I am facing a problem with neuron implementaion, as it only displays 'x'. ...
2 votes
1 answer
34 views

Why I am having x as output from ReLU?

I am trying to test ReLU, but it always gives 'x' for the output. ...
2 votes
1 answer
50 views

VHDL: Variables depending on other variables

If I'm in a process and I have a variable (A) changing and a different variable (B) changing based on the original variable (A), does other variable (B) change based on the new value or the initial ...
  • 185
0 votes
1 answer
59 views

Performance metrics for a VHDL/Verilog RTL design

Correctness and performance is everything in programming. Verifying it for software is relatively easy because you can "just" run the program and see if it crashes and/or is very slow. ...
0 votes
1 answer
99 views

Unpacked and Packed Arrays

I have been reading on the unpacked and packed arrays in SV. I have mostly understood the concepts and style with which arrays are declared. However, there are some particular cases: ...
  • 41
0 votes
2 answers
146 views

FPGA applications in power electronics [closed]

I'm a power electronics hardware design engineer and I'm trying to build some additional skills like a sub-branch. I've always been interested in FPGAs and I decided to combine my major skill with my ...
  • 149
0 votes
0 answers
79 views

Sequence of execution of "always" and "generate" blocks

I'm fairly new to Verilog. I have been writing some code by myself and need some help. The following is the code for a serial to parallel interface. ...
  • 41
0 votes
1 answer
60 views

Alternative to using FSM for implementing round robin

It is easy to implement round robin (A->B->C->A->B->C..) using FSM in VHDL. Is there an alternative to FSM? For some reason, I have a feeling there is a nice and neat implementation ...
3 votes
4 answers
183 views

Difference in synthesis between bitwise AND (&) and logical AND (&&)

Would these two code snippets synthesize the same way? I know this will be tool dependent because all synthesizers are slightly different. That being said, I think they probably tend to agree on this ...
  • 31
-1 votes
1 answer
260 views

Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

I write some library module on SystemVerilog. I want to check input parameters on synthesis and then if their values are wrong I want to stop synthesis with a custom error that will tell which ...
  • 2,120
1 vote
1 answer
77 views

Why does adding "& 1" to an assign statement produce a completely different synthesis?

I am trying to implement a one-bit full adder in Verilog. Here's my original code: ...
1 vote
2 answers
114 views

Why is order of bits not getting reversed?

In this code, while declaring in and out, the seventh bit of input is MSB, while the zeroth bit of output is MSB. So, why is the ...
0 votes
1 answer
90 views

Modelsim Altera not working [closed]

Hi i'm new to verilog designing and i'm trying to simulate but modelsim doesn't even load the design, i'm glad if someone could help, thanks. ( counter and contatore are two modules that i included in ...
  • 1
0 votes
1 answer
326 views

Syntax error Begin statement HDL 9-806

I have an error in the form of HDL 9-806 on the begin statement. The code below is a button based sequence detector an addition LED flash when sequence is correct with a debouncer to stop multiple ...
  • 1
0 votes
1 answer
256 views

What is the logic behind the behaviour of reg in Verilog?

I know SystemVerilog and now I'm trying to learn pure Verilog. I find the way reg works to be rather odd. I thought wire is used ...
  • 15
0 votes
1 answer
163 views

Build on-chip ROM in HDL

I wrote the next code in quartus 15.0, where I show what I want to do for a specific project. I can write it both in VHDL and Verilog HDL, but verilog is notoriously shorter. ...
  • 58
3 votes
1 answer
179 views

Ternary operator doesn't work in Icarus Verilog

I have the following Verilog modules, which I'm simulating with Icarus Verilog. It seems that the ternary operator doesn't work, or has a bug: main module (i2c_app_tb.v) ...
  • 1,151
-2 votes
5 answers
352 views

Why Hardware Description Language?

Before moving to understand the purpose of Hardware Description Language(HDL), we need to know what is HDL? From wiki, A hardware description language enables a precise, formal description of an ...
  • 129
1 vote
4 answers
203 views

What is the difference between throughput and operating frequency of a digital system?

I am designing a digital system with 2 pipeline stages. While synthesizing the design in Xilinx ISE, I find that the latency of the critical path is 19ns. The clock period estimate for my design is ...
1 vote
2 answers
1k views

Positive edge reset and negative edge reset

I am new to Verilog and I am trying to implement an asynchronous reset. I have difficulties understanding the difference between using ...
  • 13
2 votes
2 answers
444 views

Is it bad practice to use the positive/rising edge of a "non-clock" signal?

Situation: Before a data ready signal can go high it must wait for a data valid signal to go high. Once ...
  • 367
1 vote
1 answer
154 views

Multiple Driver Error When Trying to Instantiate Wires

I am trying to run Vivado's implementation on my design but I am getting this error: ...
1 vote
1 answer
229 views

Creating internal write and read enable pulses for a FIFO

I am trying to learn how to use Vivado's IP core generator. I came up with a simple project where I want to use a counter that measures the width of an incoming pulse, writes the measurement into a ...
0 votes
1 answer
268 views

For QuestaSim, what's the difference between vsim.exe and vsimk.exe? [closed]

For QuestaSim, what's the difference between vsim.exe and vsimk.exe under C:\questasim64_2020.4\win64\vsimk.exe? for some reason, in order to invoke QuestaSim in batch mode from the Powershell prompt, ...
  • 173
0 votes
2 answers
278 views

Is there an implementation of mixed analog (SPICE) and digital (HDL) simulations?

I wonder how it could be possible to do mixed circuits simulations. In my imagination, there is a circuit netlist which contains analog and digital components. Since XSPICE (and I think ngspice) has ...
  • 45
2 votes
2 answers
2k views

Vivado Simulation Running Very Slow

I am trying to blink an LED on a new board I bought that uses an Artix-7 FPGA. This is my first time using Vivado and for some reason when I run a simulation for 1 second the simulation draws the ...
-1 votes
1 answer
405 views

Quadrature Decoding using FPGA

I am currently working through FPGA4FUN's tutorial on quadrature decoding using an FPGA. I am currently just trying to simulate the decoders behavior by using a testbench that essentially drives the A ...
0 votes
2 answers
296 views

Concatenation with non-blocking assignment

I'm teaching myself Verilog with HDLbits and tackling this problem. According to this post, assignment with the LHS of the expression as a concatenation should work. In practice I've used this many ...
2 votes
3 answers
6k views

How to rotate bits in Verilog

I am trying to create a way to rotate bits in Verilog according to a calculated register. Here is what I have tried: ...
0 votes
1 answer
634 views

Addition of two hex numbers in Verilog gives wrong result

I am trying to add hexadecimal numbers in Verilog but I am getting the wrong outputs. Here are the numbers I am adding. Variables temp_1 and ...
0 votes
2 answers
793 views

Verilog for loop not iterating

The current for loop that I have coded below is getting stuck at its last iteration value. In other words, the value of i initially starts at 0 but once it reaches ...
0 votes
1 answer
422 views

How to Use Modular Arithmetic in Verilog

I am trying to code the RC6 (Rivest cipher 6) algorithm using Verilog. The algorithm requires addition, subtraction and multiplication in modulo 232. I've been told that I can use conventional +, -, * ...
0 votes
1 answer
679 views

Assigning Specific Input Bits to Separate Registers in Verilog

I have a 128-bit input that I am trying to assign to four different 32-bit registers. I believe the issue is the way I have the 128-bit input coded in my test bench because my output is just a 128-bit ...
4 votes
3 answers
611 views

Why does “non blocking” assignment in Verilog seem like a misnomer?

As their names imply, Non blocking assignments allow concurrent execution while blocking assignments execute sequentially. Take Nandland’s explanation for example: In C, “The second line is only ...
  • 367
1 vote
1 answer
153 views

Triggering another always block from an always block

In the below image,there's the code for parity generation. State represented by even_odd and output as z. What will happen if the circled red part as in the image has blocking assignments instead of ...
0 votes
1 answer
155 views

TeraTerm can't detect the correct port, FPGA Project

I'm a beginner at FPGA design and have been actively trying to complete new projects to get more hands on experience. The project I'm currently working on is a tutorial from nandland. This video ...
2 votes
2 answers
178 views

Asking if this module is physically possible?

I am an electronics student and learning Verilog. I had an assignment to build an clock divider for arbitrary frequency. I have made a module that works, ...
1 vote
2 answers
225 views

Implementing an SHA256 algorithm in an FPGA - Error during timing analysis

I ve updated this question because of manange to improve a bit. Right now i have no timing issues anymore but when i try to hash something on the board, my output on TeraTerm will be some random ...
4 votes
2 answers
207 views

Verilog conditional assignments without using procedural blocks like VHDL with/select

I am trying to find a way to conditionally assign values to a signal in verilog similar to the with/select in VHDL. So far I found two ways https://www.chipverify.com/verilog/verilog-4to1-mux. This is ...
  • 59
1 vote
3 answers
119 views

How to implement a continuously scanning multi-channel system in Verilog

I currently have a multi-channel system where each channel is receiving a pulse at different times. I want whichever channel receives its pulse first to act as the reference to then measure the time ...
1 vote
0 answers
163 views

Why is my FPGA clock so slow

To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this: <...
  • 25
2 votes
2 answers
352 views

VHDL: port declaration design for a feedback signal

I am a Computer Engineering student currently learning computer architecture, and working on modeling a booth's algorithm in VHDL. My design hierarchy contains a datapath and a control unit. The ...
0 votes
2 answers
218 views

VHDL: on variable declarations to act as register

I am currently a CPE student taking up computer architecture, learning how to model major computer components using VHDL. Currently, I am working on a shift register as a sub component for a top-level ...
2 votes
1 answer
160 views

Model running slower than RTL in SystemVerilog

I'm testing an RTL implementation of a certain block from a 3rd party company in SystemVerilog using Questa. The block is fairly large and my block which acts as a wrapper around it is also large. The ...
-2 votes
1 answer
171 views

Doubt in non-blocking regarding order of execution

If I have theses statements: output reg [7:0] cnt; initial cnt=8'b00000001; always @(posedge clk) begin cnt<=cnt<<1; cnt[0]<=cnt[7]; end Now in this ...
0 votes
1 answer
39 views

Doubt in non-blocking statement verilog

Suppose i have 2 non-blocking statements as follows: reg x,y; initial begin x=10; y=20; end and if I execute this: a) ...
1 vote
1 answer
360 views

Copying Queues to Dynamic Arrays

...

1
2 3 4 5 6