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Questions tagged [hdl]

HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

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Using a parameter as a macro in system verilog code

Assume that I have below module definition with a parameter N: ...
Saransh Choudhary's user avatar
-3 votes
1 answer
106 views

Whats the error?

I'm trying to make a counter but Vivado display an error, and I cannot see what's the problem. As far as I know the design is correct. Someone can tell if I'm missing something, please.
A. V.'s user avatar
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2 answers
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FPGA arithmetic implementation

How does an FPGA synthesis tool decide how to implement arithmetic operations on the target hardware? For example, if I implement some integer multiplication and division operations directly in HDL ...
b7031719's user avatar
2 votes
1 answer
69 views

D latch module in VHDL using NAND structure [closed]

What is the difference between a positive-level D latch and a negative-level D latch? How to create positive and negative D latch in VHDL using NAND structure? Can you share some example codes for ...
Serkan Kaya's user avatar
1 vote
1 answer
63 views

A NAND gate with propagation delay in VHDL

I want to design a NAND gate (\$t_{PLH}\$ = \$t_{PHL}\$ = 10ns) with VHDL. \$t_{PLH}\$ = Propagation delay low to high \$t_{PHL}\$ = Propagation delay high to low This is first code. ...
Serkan Kaya's user avatar
2 votes
2 answers
96 views

Fixed point multiplication circuit in HDL doesn't work as expected

I am implementing a fixed point multiplication circuit in SystemVerilog to multiply 2 64-bit numbers, each has 20 bits of decimal part (which remains 44 bits of integer part). The problem is the ...
Becker's user avatar
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1 vote
1 answer
59 views

Where to register value in Verilog?

I'm looking for some help understanding a synthesis error I run into frequently with Verilog code on an FPGA platform (Lattice ECP5U). Here's a simplified setup that produces the error. ...
jemalloc's user avatar
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1 vote
2 answers
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Verilog Double Counter Testbench Issues

I've been practicing writing some more advanced testbenches for my Verilog circuits. I thought I'd work with something simple: a double counter setup, where c0 is 3-bits long and c1 is 16-bits long. ...
aofarmakis's user avatar
2 votes
2 answers
114 views

What is the technical reason an array of interfaces can't be indexed into unless the index is constant?

I'm curious as to why an array of interfaces can't be indexed into unless the index is constant. Specifically I'm curious as to the case where a for loop is used, because a for loop elaborates into an ...
avor's user avatar
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What is the relation between number of LUT values and output frequency?

VLSI/FPGA beginner here. I interfaced my Digilent Arty A7-35 with a DAC, using basic DDS (implementing timing diagram of the DAC on FPGA) and interfacing LUT(s) to form sine waves of multiple ...
DaveFenner's user avatar
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How do I call a module repeatedly in Verilog, in sync with a clock?

What I intend to do is basically cycle through a LUT created in a second module, by instantiating it in the first. Additionally, I need to call the instantiation in sync with the clock. The basic idea ...
DaveFenner's user avatar
1 vote
2 answers
72 views

When should you use default operators vs. implementing your own hardware?

When using Verilog, when should you use default operators like a + b, and when should you implement your own version of the hardware, like writing a full adder? Is ...
Tzanker's user avatar
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2 answers
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Do HDL synthesizers "optimize code", more or less as compilers do?

I'm implementing a pipelined CPU in SystemVerilog. I need to propagate datapath signals from one pipeline stage to the next but, of course, not all stages produce the same number of signals. To keep ...
Dan's user avatar
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1 answer
410 views

SystemVerilog array of parameters/constants

If I have code like this: ...
lousycoder's user avatar
2 votes
2 answers
151 views

Does this Verilog HDL code of a decoder look strange in any way?

I am wondering if it is ok to use output instead of wire for another output in Verilog coding (using Quartus for this). Just ...
towel Lijiang's user avatar
2 votes
1 answer
188 views

My 1-bit ALU is not able to do subtraction [closed]

I am trying to make a 4-bit ALU in Verilog which can perform the following functions: Add Subtract Compare (>,<,=) AND The approach I have taken is to make 4, 1-bit ALUs and connect them in ...
Koustubh Jain's user avatar
1 vote
1 answer
258 views

How to legally/properly run a Verilog file that needs other files?

I have written a simple ripple carry adder in Verilog (in a structural fashion), and I have defined the required half adder in a module in another file. When I run them (using ...
Koustubh Jain's user avatar
3 votes
2 answers
487 views

Why does this Verilog code work without "wire" statements?

My textbook (Brown and Vranesic) gives the following code for a simple 4-bit RCA implementation in Verilog: ...
EE18's user avatar
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1 answer
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How do I create custom signal in waveform config file for a big Boolean expression made of many signals/expressions in an "if else" block in Vivado?

This question is related to (System/)Verilog HDL simulation for FPGA inside tools like Vivado, Modelsim etc. In a sample code where I have 2 net type variables, I want to plot a waveform for a ...
lousycoder's user avatar
-1 votes
1 answer
648 views

Logical AND vs Bitwise AND for single bit and multibits [duplicate]

What is the functional and physical difference in using Logical AND ( && ) and Bitwise AND (&&) over singlebit and multibit signals. Below shared cases. case 1: A[3:0] & B[3:0] = ?...
DonMano's user avatar
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1 answer
104 views

How to do clock signal rising edge detection in Chisel (scala)?

I have encountered in a problem of rising edge detection in writing chisel code. Here is the code I wrote. ...
Chenhe yuan's user avatar
2 votes
2 answers
199 views

Parsing variable-sized data in 32-bit datastream

I have a 32-bit datastream coming from a sensor. The data is encoded as a Type-Length-Value encoding. This means the first byte indicates what kind of data there is and the second byte contains the ...
John Smith's user avatar
1 vote
1 answer
250 views

What's the correct way of port declaration while instantiating modules in Verilog HDL?

From what I know, if we need to instantiate module1 in module2, then I need to declare all the ...
Killjoy's user avatar
  • 131
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1 answer
67 views

Why does this Verilog testbench not undergo a race condition?

This is the testbench in question: ...
Killjoy's user avatar
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1 vote
1 answer
52 views

How do I figure out if my Verilog code output was generated out of race condition?

Apart from physical observation, is there a way to know if my code will undergo a race condition? For example, the following code has a race condition because both ...
Killjoy's user avatar
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2 votes
1 answer
2k views

How do I create a 2D array in Verilog?

I want to use a 2D array in a Verilog testbench. I tried it this way: ...
Killjoy's user avatar
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1 vote
1 answer
153 views

What's the purpose of "functions" if they can be replaced by "tasks" in Verilog HDL?

In Verilog, a task can do everything that a function can along with having other features. Then what's the purpose of having ...
Killjoy's user avatar
  • 131
1 vote
1 answer
137 views

What am I doing wrong with this 2x2 Karatsuba Multiplier in Verilog HDL?

I am trying to implement a 2x2 karatsuba Multiplier which I will be using as a base case for a higher bit multiplier. Here's the code: ...
Killjoy's user avatar
  • 131
3 votes
1 answer
535 views

Why is my Karatsuba multiplier not giving right answers for large numbers?

I tried to implement 16-Bit Karasutba Multiplier in Verilog HDL. It gives me right answers for small numbers, but it's incorrect for large numbers. Can someone point out what's wrong? Here's the ...
Killjoy's user avatar
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1 vote
1 answer
60 views

How can I compare the speed of two algorithms implemented in verilog HDL without using FPGA?

I have implemented two 32 bit multiplier algorithms (Booth and Karatsuba) in verilog HDL. I wanted to make a comparison of the time taken by both algorithms to multiply same numbers. How can I do that ...
Killjoy's user avatar
  • 131
0 votes
2 answers
360 views

How do I instantiate modules within case statements in Verilog HDL?

I am trying to make a sequence detector with 4 modes - Moore machine overlapping & non-overlapping and Mealy machine overlapping & non-overlapping. But writing my code like this gives me an ...
Killjoy's user avatar
  • 131
3 votes
2 answers
2k views

How do you invert a section of a four bit wide signal in Verilog?

I'm working on this lab from the ETH Zurich course on Digital Design. I'm creating a truth table for signals to lines in a 7-segment number display. The display is controlled by a 4-bit input. One of ...
Connor's user avatar
  • 399
2 votes
1 answer
821 views

How to write program counter in SystemVerilog?

I was trying to build an 8-bit program counter, and it should support branching. This is what I wrote: ...
Chenhe yuan's user avatar
-1 votes
1 answer
516 views

Delaying falling edge, and faster rising edge for output signal [closed]

I'm trying to take an incoming signal to use as an output, but that output (active low) needs to be enabled about 20ns after the incoming signal goes low, and then go high again about 20ns before the ...
mikerakesh's user avatar
0 votes
2 answers
373 views

When using Cocotb, should I be using FallingEdge to set and assert values?

I'm attempting to use Cooctb to verify a simple Verilog counter with a reset: ...
Dave Dribin's user avatar
3 votes
1 answer
255 views

Basic addition not working as expected

I'm trying to add two numbers together, and it's giving an odd result. Here's the code, ...
Lethe563's user avatar
  • 115
1 vote
1 answer
121 views

What value will be assigned to x, is it a or ~x?

I have some Verilog code for which I am unsure of the outcome of the non-blocking assignment of x as shown below : ...
davos's user avatar
  • 13
0 votes
0 answers
44 views

How flexible are modern HDL Synthesis tools in terms of output primitives?

As a firmware guy I'm fascinated with porting tools like GCC to support arbitrary weird processors, which nowadays can be manifested on FPGAs with relative ease. I'm curious whether something ...
Aaron Linnell's user avatar
7 votes
2 answers
1k views

Identifying an edge INSIDE an 'always' block

I am an experienced C programmer trying to learn enough Verilog to create a brushless motor controller. I am nearly done except for one detail. I want to do something like this: ...
Tinkerer's user avatar
0 votes
1 answer
100 views

Are there other examples of applications of a priority arbiter apart from sharing system bus or memory?

I was wondering where else a priority arbiter is used in the real world, apart from sharing a system bus or memory. I tried googling, but couldn't find any other examples. For context: I'm working on ...
Ash's user avatar
  • 23
0 votes
2 answers
312 views

Are SR latches bad in ASIC design?

I am implementing an ASIC design, and my current solution for a problem requires an SR latch. I've always been told that latches are bad in FPGA and ASIC designs, but never got a proper answer as to ...
Elzaidir's user avatar
  • 103
0 votes
1 answer
109 views

Verilog counter is not working using @always statement

I am trying to implement counter using Verilog HDL ...
nai1ka's user avatar
  • 3
1 vote
1 answer
311 views

Dense Neuron Neural Network in Verilog

I am trying to build NN in system verilog, but I am facing a problem with neuron implementaion, as it only displays 'x'. ...
Ghadeer Ali Jaradat's user avatar
2 votes
1 answer
45 views

Why I am having x as output from ReLU?

I am trying to test ReLU, but it always gives 'x' for the output. ...
Ghadeer Ali Jaradat's user avatar
2 votes
1 answer
145 views

VHDL: Variables depending on other variables

If I'm in a process and I have a variable (A) changing and a different variable (B) changing based on the original variable (A), does other variable (B) change based on the new value or the initial ...
Q-Tip's user avatar
  • 197
0 votes
1 answer
143 views

Performance metrics for a VHDL/Verilog RTL design

Correctness and performance is everything in programming. Verifying it for software is relatively easy because you can "just" run the program and see if it crashes and/or is very slow. ...
Gaslight Deceive Subvert's user avatar
0 votes
1 answer
707 views

Unpacked and Packed Arrays

I have been reading on the unpacked and packed arrays in SV. I have mostly understood the concepts and style with which arrays are declared. However, there are some particular cases: ...
Sac's user avatar
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0 votes
2 answers
644 views

FPGA applications in power electronics [closed]

I'm a power electronics hardware design engineer and I'm trying to build some additional skills like a sub-branch. I've always been interested in FPGAs and I decided to combine my major skill with my ...
Das D.'s user avatar
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0 answers
209 views

Sequence of execution of "always" and "generate" blocks

I'm fairly new to Verilog. I have been writing some code by myself and need some help. The following is the code for a serial to parallel interface. ...
Sac's user avatar
  • 41
0 votes
1 answer
122 views

Alternative to using FSM for implementing round robin

It is easy to implement round robin (A->B->C->A->B->C..) using FSM in VHDL. Is there an alternative to FSM? For some reason, I have a feeling there is a nice and neat implementation ...
user7586189's user avatar

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