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Questions tagged [hdl]

HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

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How to compare a re-writable 4 bit value to a given 4 bit input in Verilog?

The goal of this project to design a computational lock alarm in Verilog to be run on an Altera board (note on the board 0 is actually ON and 1 is OFF). Based on the design criteria I created a state ...
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2answers
45 views

How to get the MSB into a logic gate which will check if a number is negative or not?

I need to create a logic gate which will find out whether a number is negative or not. The input is 8 bits and the output is 1 bit, and if the input is 1 (i.e. negative number) then the output ...
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29 views

Variable input MUX in Verilog

What's the best way to make an N:1 multiplexer in Verilog (NOT SystemVerilog), where the maximum N is 64? Each input is 32-bits wide and there are N such inputs. Verilog doesn't allow two-dimensional ...
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67 views

How to have an in-system check in an FPGA based system that it has been reset?

I have a system based on Altera's MAX10 device that is doing the following tasks: receives the data and stores it on an on-chip flash memory only once. reads all the data from on-chip flash, stores ...
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104 views

Vivado simulation stuck at 0 fs

I am trying to simulate a D flip flop using Vivado 2018.2.2. But upon running the simulation a window pops up stating Current time: 0 fs. The program doesn't freeze, it just doesn't progress. Here is ...
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86 views

Net type, variable type, data type and data objects

I am really confused by the conception of net type, variable type, data type and data objects in SystemVerilog. I am using the simulator inside Xilinx Vivado 2018.02 for all the following codes. <...
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1answer
56 views

Can demultiplexers be synthesized?

In my digital design module involving HDL (Verilog) and a ton of RTL diagrams, our lecturer always said never to use demultiplexers because they do not exist. Why is that?
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62 views

How exactly does $cast work

When a $cast is executed between a base and a derived class objects, does it allocate more memory for the derived class handle? ...
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97 views

What exactly lies between an HDL and a circuit?

I'm trying to learn basics of hardware design process to get a better understanding of how CPUs, microcontrollers etc work and how are they made. My googleing gave me many articles with info like "...
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2answers
64 views

how to trigger another clk in mainclk (verilog)

I wrote somekind of prescaler in verilog to make sclk_adc signal from clk_i. by now my code looks like: always @(posedge clk_i) begin //generation of sclk_adc end ...
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2answers
110 views

Xilinx ZYNQ/ARTIX7 Invert Clock without inducing skew

For HDL design I'm currently developing for a zynq SoC, I need to invert a clock signal because of a swapped differential pair on board level. Using "NOT" to invert adds a LUT in the path and as ...
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How to model electric power consumption in verilog-a?

I am modeling an analog device using verilog-a (to which I am quite new). I would like the model to match the power consumption of the physical device, for which the energy cost associated with state ...
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63 views

FSM was struck between two states only!

I'm writing an fsm which is struck between s1 and s2 and not going to next state. Even if I increase the delay after s3 ( for it to complete operation). I even observed the simulation that the data ...
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1answer
106 views

Problem relating to FSM machine

I am trying to write a verilog code for a Fibonacci sequence generator. It's output will be nth Fibonacci number where n is the output of the count. The code works for count = 2. But when the count ...
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3answers
77 views

Generate if-for statement

Can we declare Generate if-for statement? ...
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1answer
133 views

Initial Block is Sythesizable!

I came across a lot of posts saying that initial block is not synthesizable in Verilog HDL.Even I followed the standard reference (https://link.springer.com/content/pdf/bbm%3A978-81-322-2791-5%2F1.pdf)...
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56 views

Will temp variable in always_comb create latch

I have following code snippet where a temp variable is used to count number of 1s in an array: ...
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4answers
120 views

Generation of non overlapping clocks on FPGA using VHDL

I am trying to implement switched capacitor circuits and I hence need to generate a two-phase non-overlapping clock. I have been trying to use an FPGA for the same. Unfortunately, my synthesis tool- ...
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1answer
71 views

Best practice for synchronizing VHDL stimuli with circuit

What is the best practice or method for synchronizing stimuli input and output with a sequential logic block in VHDL? I am currently running only behavioral simulations, but I want to make sure my ...
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1answer
53 views

VHDL does not have built in capability to read binary files, do Verilog and SystemVerilog have it?

Reading and writing binary files in VHDL is not straightforward, I am not sure why this is so. I think that Verilog and SystemVerilog are more closer to C. Do they have built in capability to read/...
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26 views

Verilog-A Current/Voltage/Power Inconsistency

I'm simulating a phase change material in Verilog-A and need to calculate the power across the material. The material is a resistor, so it satisfies Ohm's Law. Therefore, P = IV = (I^2)R = (V^2)/R ...
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3answers
222 views

iverilog unable to bind parameter

When using iverilog to compile a script I get the following error: ...
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2answers
46 views

Change memory content of FPGA SoC (DE1-SoC) using software while .sof (EPCQ) is running on FPGA

I am new to FPGA and FPGA-SoC world. I have a DE1-SoC board. I am doing a project. Hardware design of the project contains a memory block which is initialized using .mif file. I know that we can use ...
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5answers
118 views

Will the High-Level Synthesis (HLS) design approach for FPGAs reduce the demand for RTL designers? [closed]

I'm a senior electrical engineering student who's very interested in FPGAs and RTL design. But recently after learning what HLS compilers are capable of I had to consider the possibility that ...
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1answer
61 views

VHDL - Can you produce an output corresponding to the input if the input changed in the same clock cycle?

In VHDL, if we have a system where the output changes depending on a variable that changes with the input. Say the output has 2 modes and an input switches between them. In the same clock cycle, can ...
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1answer
57 views

Cannot extract expected values in VHDL at first clock cycle

The VHDL design below is supposed to extract the Nth bits from the four values x_0, x_1, x_2 and x_3 and create a new value at every clock but this is not happening. Find below the design and the ...
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147 views

Can I connect all my components in my top level entity

I have finished writing a project with separate VHDL files. Most of the components have connections directly to the FPGA ( which I have instantiated and connected in the top level file) but a few do ...
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2answers
216 views

in what order does a VHDL program run in an FPGA

I am trying to wrap my head around exactly what goes on in an FPGA when I program it, specifically using VHDL. I know all code outside processes run concurrently but what about processes in different ...
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1answer
113 views

How to modify input wires before sending them as input in another modules?

I want to design a 8 bit adder-subtracter in verilog. when cin is 1, it should add 2 numbers, when 0, it should subtracts. For performing subtraction, I said to add number1 and ~number2 and 1. here ...
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49 views

Structure Identification in HDL codes

I wanted to automatically Identify some structures in HDL code (Verilog/VHDL), let say an adder. I need to automatically detect how many adders in the design. I am not sure from where to start, should ...
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1answer
88 views

Altera HDL design techniques

Some many years ago my teacher taught us to program Xilinx Spartan II development board. He taught us to think of the hardware element we wanted to invoke (logic gate, adder, shift register, etc) and ...
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1answer
226 views

using generate statement in verilog

I am using nested for loops using generate module for creating multiple instances of sub-modules in verilog this is for finding 4x4 determinant. I generated the sub-modules with inputs given ...
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60 views

Can MATLAB HDL coder support LUTs for native floating point mode?

I'm trying to implement HDL coder in Simulink to convert a subsystem to HDL which takes 2 inputs for a 2D lookup-table (LUT) and outputs one signal. This works fine if the data type is fixed point, ...
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2answers
86 views

Illegal sequential statement right shift multiplier

I am trying to implement a Right shift multiplier and that is supposed to be the data path. Why does this code generate this error ?: Illegal sequential statement. ...
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35 views

VHDL Modelling Style

I know there are 3 types of modelling styles (Structural, Dataflow, Behavioral) but I don't understand what is the point of all three as standalone styles and as a whole. What is the point of every ...
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1answer
278 views

Verilog modulus operator for wrapping around a range

My background is in software and I'm new to (System)Verilog so when tasked with implementing a caesar shifter (shift each letter in a string by N letters, wrapping around if necessary e.g. ABCXYZ ...
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2answers
38 views

System-level, mixed signal hardware description language (HDL) and software (editor, simulator)?

I am looking for devices (conceptual / software) to simplify and unify our current method of industrial control system planning and documentation, especially to help with debugging. This is currently ...
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52 views

Verilog code indetermination [duplicate]

i have a problem with this code, because in the RTL simulation, the output Cookie appears as StX. I don't know why this is happening since i don't know verilog well. Can someone help me? ...
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2answers
751 views

Counter in verilog

i want to make a counter that increases by the value of its inputs, but i did the testbench and the output is undetermined, xxxx. Can someone tell me if there is something wrong in this code? ...
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72 views

Verilog Code Optimisation

I have recently become involved in FPGA design and I am just testing out some new Zync SoC hardware. I have followed a tutorial online to blink some LED's however I have modified it to blink all the ...
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2answers
278 views

Verilog Vivado UART design : implementation / bitstream issues

I am currently working on my first-ever Verilog project for my company. I am a newly minted engineer so my experience is just academical. Forgive me if my English is not perfect, I'll try to do my ...
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2answers
946 views

Eliminate VHDL inferred latch in case statement

I'm a mostly analog EE who's trying to set up an fpga dev kit (terasic de0-nano) to twiddle the control bits on some pulse control parts I'm doing an evaluation board for. I'm using an external dip ...
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3answers
914 views

Sensitivity list rule in HDL

I have a little confusion about sensitivity list rule: all signals that are read in the always block must be included in the list. When including the posedge CLK and EN in my sensitivity list, I get ...
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1answer
178 views

VHDL Style Checker / Check Style

Is there a style checker for VHDL? I found style guidelines, but I didn't find anything like check style. Thanks in advance!
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2answers
83 views

Mixing reset and non reset registers

If you must mix synchronous reset and non reset flops in a single always block, would this be the correct way... ...
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0answers
504 views

Verilog SRAM controller

I am trying to implement a SRAM controller module. It's structured as follows External connections: extA[18:0] -- address extIO[7:0] -- bidirectional input/output OE,WE,CE -- control signals ...
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0answers
185 views

Matlab and HDL code generation

I have a project involving audio on a Xilinx Spartan6 FPGA. The goal of the project is to make an audio processor using HDL (mostly educative and for fun). It's basically a pipeline of audio effects ...
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1answer
169 views

Truncate and other operations on the constant in Verilog

Very simple example I am stuck with. I want design written in Verilog to return a year defined in source as 16-bit format to the outer world using two bytes. ...
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60 views

What do i need to connect to clock_enable pin from VHDL box in Signadyne FPGA?

I have this digital filter box (it's VHDL vodule that i get from matlab hdlgenerator) I want to know, what do i should connect to clock_enable pin? If it possible i really want a comprehensive ...