Questions tagged [hdl]

HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

Filter by
Sorted by
Tagged with
0 votes
0 answers
27 views

Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

I write some library module on SystemVerilog. I want to check input parameters on synthesis and then if their values are wrong I want to stop synthesis with a custom error that will tell which ...
user avatar
  • 1,834
0 votes
1 answer
54 views

Why does adding "& 1" to an assign statement produce a completely different synthesis?

I am trying to implement a one-bit full adder in Verilog. Here's my original code: ...
user avatar
-1 votes
1 answer
45 views

Is there a need to add reset to flip flop? [closed]

Flip flop is composed from a latch, is it necessary to add a reset signal?
user avatar
1 vote
2 answers
91 views

Why is order of bits not getting reversed?

In this code, while declaring in and out, the seventh bit of input is MSB, while the zeroth bit of output is MSB. So, why is the ...
user avatar
-1 votes
0 answers
45 views

ModelSim cannot find SystemVerilog standard library file

I am trying to compile a very simple SystemVerilog module; however, I am getting the following error messages. ...
user avatar
0 votes
1 answer
32 views

Modelsim Altera not working [closed]

Hi i'm new to verilog designing and i'm trying to simulate but modelsim doesn't even load the design, i'm glad if someone could help, thanks. ( counter and contatore are two modules that i included in ...
user avatar
  • 1
0 votes
1 answer
138 views

Syntax error Begin statement HDL 9-806

I have an error in the form of HDL 9-806 on the begin statement. The code below is a button based sequence detector an addition LED flash when sequence is correct with a debouncer to stop multiple ...
user avatar
  • 1
0 votes
1 answer
162 views

What is the logic behind the behaviour of reg in Verilog?

I know SystemVerilog and now I'm trying to learn pure Verilog. I find the way reg works to be rather odd. I thought wire is used ...
user avatar
  • 25
0 votes
1 answer
99 views

Build on-chip ROM in HDL

I wrote the next code in quartus 15.0, where I show what I want to do for a specific project. I can write it both in VHDL and Verilog HDL, but verilog is notoriously shorter. ...
user avatar
  • 48
3 votes
1 answer
123 views

Ternary operator doesn't work in Icarus Verilog

I have the following Verilog modules, which I'm simulating with Icarus Verilog. It seems that the ternary operator doesn't work, or has a bug: main module (i2c_app_tb.v) ...
user avatar
  • 965
-2 votes
5 answers
237 views

Why Hardware Description Language?

Before moving to understand the purpose of Hardware Description Language(HDL), we need to know what is HDL? From wiki, A hardware description language enables a precise, formal description of an ...
user avatar
  • 129
1 vote
4 answers
146 views

What is the difference between throughput and operating frequency of a digital system?

I am designing a digital system with 2 pipeline stages. While synthesizing the design in Xilinx ISE, I find that the latency of the critical path is 19ns. The clock period estimate for my design is ...
user avatar
1 vote
2 answers
460 views

Positive edge reset and negative edge reset

I am new to Verilog and I am trying to implement an asynchronous reset. I have difficulties understanding the difference between using ...
user avatar
  • 13
2 votes
2 answers
267 views

Is it bad practice to use the positive/rising edge of a "non-clock" signal?

Situation: Before a data ready signal can go high it must wait for a data valid signal to go high. Once ...
user avatar
  • 355
1 vote
1 answer
82 views

Multiple Driver Error When Trying to Instantiate Wires

I am trying to run Vivado's implementation on my design but I am getting this error: ...
user avatar
1 vote
1 answer
116 views

Creating internal write and read enable pulses for a FIFO

I am trying to learn how to use Vivado's IP core generator. I came up with a simple project where I want to use a counter that measures the width of an incoming pulse, writes the measurement into a ...
user avatar
0 votes
1 answer
155 views

For QuestaSim, what's the difference between vsim.exe and vsimk.exe? [closed]

For QuestaSim, what's the difference between vsim.exe and vsimk.exe under C:\questasim64_2020.4\win64\vsimk.exe? for some reason, in order to invoke QuestaSim in batch mode from the Powershell prompt, ...
user avatar
  • 173
0 votes
2 answers
183 views

Is there an implementation of mixed analog (SPICE) and digital (HDL) simulations?

I wonder how it could be possible to do mixed circuits simulations. In my imagination, there is a circuit netlist which contains analog and digital components. Since XSPICE (and I think ngspice) has ...
user avatar
  • 23
2 votes
2 answers
1k views

Vivado Simulation Running Very Slow

I am trying to blink an LED on a new board I bought that uses an Artix-7 FPGA. This is my first time using Vivado and for some reason when I run a simulation for 1 second the simulation draws the ...
user avatar
-1 votes
1 answer
264 views

Quadrature Decoding using FPGA

I am currently working through FPGA4FUN's tutorial on quadrature decoding using an FPGA. I am currently just trying to simulate the decoders behavior by using a testbench that essentially drives the A ...
user avatar
0 votes
2 answers
150 views

Concatenation with non-blocking assignment

I'm teaching myself Verilog with HDLbits and tackling this problem. According to this post, assignment with the LHS of the expression as a concatenation should work. In practice I've used this many ...
user avatar
1 vote
2 answers
3k views

How to rotate bits in Verilog

I am trying to create a way to rotate bits in Verilog according to a calculated register. Here is what I have tried: ...
user avatar
0 votes
1 answer
278 views

Addition of two hex numbers in Verilog gives wrong result

I am trying to add hexadecimal numbers in Verilog but I am getting the wrong outputs. Here are the numbers I am adding. Variables temp_1 and ...
user avatar
0 votes
2 answers
309 views

Verilog for loop not iterating

The current for loop that I have coded below is getting stuck at its last iteration value. In other words, the value of i initially starts at 0 but once it reaches ...
user avatar
0 votes
1 answer
250 views

How to Use Modular Arithmetic in Verilog

I am trying to code the RC6 (Rivest cipher 6) algorithm using Verilog. The algorithm requires addition, subtraction and multiplication in modulo 232. I've been told that I can use conventional +, -, * ...
user avatar
0 votes
1 answer
213 views

Assigning Specific Input Bits to Separate Registers in Verilog

I have a 128-bit input that I am trying to assign to four different 32-bit registers. I believe the issue is the way I have the 128-bit input coded in my test bench because my output is just a 128-bit ...
user avatar
4 votes
3 answers
369 views

Why does “non blocking” assignment in Verilog seem like a misnomer?

As their names imply, Non blocking assignments allow concurrent execution while blocking assignments execute sequentially. Take Nandland’s explanation for example: In C, “The second line is only ...
user avatar
  • 355
1 vote
1 answer
88 views

Triggering another always block from an always block

In the below image,there's the code for parity generation. State represented by even_odd and output as z. What will happen if the circled red part as in the image has blocking assignments instead of ...
user avatar
0 votes
1 answer
79 views

TeraTerm can't detect the correct port, FPGA Project

I'm a beginner at FPGA design and have been actively trying to complete new projects to get more hands on experience. The project I'm currently working on is a tutorial from nandland. This video ...
user avatar
2 votes
2 answers
176 views

Asking if this module is physically possible?

I am an electronics student and learning Verilog. I had an assignment to build an clock divider for arbitrary frequency. I have made a module that works, ...
user avatar
1 vote
2 answers
210 views

Implementing an SHA256 algorithm in an FPGA - Error during timing analysis

I ve updated this question because of manange to improve a bit. Right now i have no timing issues anymore but when i try to hash something on the board, my output on TeraTerm will be some random ...
user avatar
4 votes
2 answers
90 views

Verilog conditional assignments without using procedural blocks like VHDL with/select

I am trying to find a way to conditionally assign values to a signal in verilog similar to the with/select in VHDL. So far I found two ways https://www.chipverify.com/verilog/verilog-4to1-mux. This is ...
user avatar
  • 59
1 vote
3 answers
88 views

How to implement a continuously scanning multi-channel system in Verilog

I currently have a multi-channel system where each channel is receiving a pulse at different times. I want whichever channel receives its pulse first to act as the reference to then measure the time ...
user avatar
1 vote
0 answers
122 views

Why is my FPGA clock so slow

To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this: <...
user avatar
  • 25
2 votes
2 answers
221 views

VHDL: port declaration design for a feedback signal

I am a Computer Engineering student currently learning computer architecture, and working on modeling a booth's algorithm in VHDL. My design hierarchy contains a datapath and a control unit. The ...
user avatar
0 votes
2 answers
115 views

VHDL: on variable declarations to act as register

I am currently a CPE student taking up computer architecture, learning how to model major computer components using VHDL. Currently, I am working on a shift register as a sub component for a top-level ...
user avatar
2 votes
1 answer
100 views

Model running slower than RTL in SystemVerilog

I'm testing an RTL implementation of a certain block from a 3rd party company in SystemVerilog using Questa. The block is fairly large and my block which acts as a wrapper around it is also large. The ...
user avatar
-2 votes
1 answer
71 views

Doubt in non-blocking regarding order of execution

If I have theses statements: output reg [7:0] cnt; initial cnt=8'b00000001; always @(posedge clk) begin cnt<=cnt<<1; cnt[0]<=cnt[7]; end Now in this ...
user avatar
0 votes
1 answer
36 views

Doubt in non-blocking statement verilog

Suppose i have 2 non-blocking statements as follows: reg x,y; initial begin x=10; y=20; end and if I execute this: a) ...
user avatar
1 vote
1 answer
198 views

Copying Queues to Dynamic Arrays

...
user avatar
1 vote
1 answer
251 views

How do I fill a SystemVerilog Queue variable?

...
user avatar
1 vote
2 answers
82 views

Testbench using Task operation [closed]

I have to write a testbench using "tasks" to verify the functionality of an 8-bit ALU. My tasks are not getting simulated properly in EDA playground. Can anyone please tell me where my ...
user avatar
0 votes
2 answers
109 views

What will happen if the reset button is not pressed while running a synchronous counter on FPGA (using verilog)?

I was using the following code for a multiplexing circuit to activate 7 seg display on the Basys 3 FPGA. As for multiplexing circuit you don't often need to press a reset, so I was just wondering What ...
user avatar
0 votes
1 answer
224 views

SystemVerilog Assertions syntax error unexpected |-> [closed]

I'm starting to use SVAs for formal verification. I run QuestaSim2019 and I can successfully import uvm_pkg (is it needed to use assertions anyways?): as I do ...
user avatar
  • 325
1 vote
0 answers
148 views

SystemVerilog: copy a slice from a vector to another vector of different size

as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location. Example: ...
user avatar
0 votes
2 answers
134 views

Clock usage in the always block and in the event

In general, if we are working on a sequential circuit, say a Flip Flop (e.g. D Flip Flop) The code we write for the always block part is: ...
user avatar
1 vote
1 answer
93 views

Is this the correct truth table to determine whether or not to execute an interrupt in a RISC V system?

I'm working on implementing the privileged RISC V ISA, which can be found here. I'm looking at the bottom of page 20, and the interrupt conditions are stated very confusingly: Global interrupt-...
user avatar
  • 583
0 votes
1 answer
92 views

How does assignment work in Verilog?

I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...
user avatar
1 vote
2 answers
323 views

Is it possible to have a register with multiple drivers?

This is just a theoretical question I have. Imagine we have a register (a reg signal in Verilog for example) and two possible inputs that have to write to that register. I am assuming all signals are ...
user avatar
1 vote
3 answers
136 views

Using too many Modules in Verilog affect timing?

I have a straightforward quest about HDL and FPGA design. If I seperate my code to a lot of modules, by modules I mean verilog files which do specifig things instead of writing close to the top ...
user avatar

1
2 3 4 5 6