Questions tagged [hdl]

HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

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1answer
54 views

what is the difference between a design before synthesis and a design after synthesis [closed]

I just know synthesis is about Translation + Optimization + Mapping I want to know what the difference between them.thanks.
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1answer
66 views

Build on-chip ROM in HDL

I wrote the next code in quartus 15.0, where I show what I want to do for a specific project. I can write it both in VHDL and Verilog HDL, but verilog is notoriously shorter. ...
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1answer
64 views

Ternary operator doesn't work in Icarus Verilog

I have the following Verilog modules, which I'm simulating with Icarus Verilog. It seems that the ternary operator doesn't work, or has a bug: main module (i2c_app_tb.v) ...
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5answers
167 views

Why Hardware Description Language?

Before moving to understand the purpose of Hardware Description Language(HDL), we need to know what is HDL? From wiki, A hardware description language enables a precise, formal description of an ...
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4answers
123 views

What is the difference between throughput and operating frequency of a digital system?

I am designing a digital system with 2 pipeline stages. While synthesizing the design in Xilinx ISE, I find that the latency of the critical path is 19ns. The clock period estimate for my design is ...
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2answers
77 views

Positive edge reset and negative edge reset

I am new to Verilog and I am trying to implement an asynchronous reset. I have difficulties understanding the difference between using ...
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2answers
181 views

Is it bad practice to use the positive/rising edge of a "non-clock" signal?

Situation: Before a data ready signal can go high it must wait for a data valid signal to go high. Once ...
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1answer
67 views

Multiple Driver Error When Trying to Instantiate Wires

I am trying to run Vivado's implementation on my design but I am getting this error: ...
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1answer
86 views

Creating internal write and read enable pulses for a FIFO

I am trying to learn how to use Vivado's IP core generator. I came up with a simple project where I want to use a counter that measures the width of an incoming pulse, writes the measurement into a ...
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1answer
69 views

For QuestaSim, what's the difference between vsim.exe and vsimk.exe? [closed]

For QuestaSim, what's the difference between vsim.exe and vsimk.exe under C:\questasim64_2020.4\win64\vsimk.exe? for some reason, in order to invoke QuestaSim in batch mode from the Powershell prompt, ...
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2answers
97 views

Is there an implementation of mixed analog (SPICE) and digital (HDL) simulations?

I wonder how it could be possible to do mixed circuits simulations. In my imagination, there is a circuit netlist which contains analog and digital components. Since XSPICE (and I think ngspice) has ...
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2answers
805 views

Vivado Simulation Running Very Slow

I am trying to blink an LED on a new board I bought that uses an Artix-7 FPGA. This is my first time using Vivado and for some reason when I run a simulation for 1 second the simulation draws the ...
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1answer
146 views

Quadrature Decoding using FPGA

I am currently working through FPGA4FUN's tutorial on quadrature decoding using an FPGA. I am currently just trying to simulate the decoders behavior by using a testbench that essentially drives the A ...
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2answers
83 views

Concatenation with non-blocking assignment

I'm teaching myself Verilog with HDLbits and tackling this problem. According to this post, assignment with the LHS of the expression as a concatenation should work. In practice I've used this many ...
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2answers
906 views

How to rotate bits in Verilog

I am trying to create a way to rotate bits in Verilog according to a calculated register. Here is what I have tried: ...
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1answer
116 views

Addition of two hex numbers in Verilog gives wrong result

I am trying to add hexadecimal numbers in Verilog but I am getting the wrong outputs. Here are the numbers I am adding. Variables temp_1 and ...
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2answers
92 views

Verilog for loop not iterating

The current for loop that I have coded below is getting stuck at its last iteration value. In other words, the value of i initially starts at 0 but once it reaches ...
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1answer
128 views

How to Use Modular Arithmetic in Verilog

I am trying to code the RC6 (Rivest cipher 6) algorithm using Verilog. The algorithm requires addition, subtraction and multiplication in modulo 232. I've been told that I can use conventional +, -, * ...
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1answer
96 views

Assigning Specific Input Bits to Separate Registers in Verilog

I have a 128-bit input that I am trying to assign to four different 32-bit registers. I believe the issue is the way I have the 128-bit input coded in my test bench because my output is just a 128-bit ...
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3answers
230 views

Why does “non blocking” assignment in Verilog seem like a misnomer?

As their names imply, Non blocking assignments allow concurrent execution while blocking assignments execute sequentially. Take Nandland’s explanation for example: In C, “The second line is only ...
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1answer
61 views

Triggering another always block from an always block

In the below image,there's the code for parity generation. State represented by even_odd and output as z. What will happen if the circled red part as in the image has blocking assignments instead of ...
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1answer
60 views

TeraTerm can't detect the correct port, FPGA Project

I'm a beginner at FPGA design and have been actively trying to complete new projects to get more hands on experience. The project I'm currently working on is a tutorial from nandland. This video ...
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2answers
172 views

Asking if this module is physically possible?

I am an electronics student and learning Verilog. I had an assignment to build an clock divider for arbitrary frequency. I have made a module that works, ...
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2answers
163 views

Implementing an SHA256 algorithm in an FPGA - Error during timing analysis

I ve updated this question because of manange to improve a bit. Right now i have no timing issues anymore but when i try to hash something on the board, my output on TeraTerm will be some random ...
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2answers
65 views

Verilog conditional assignments without using procedural blocks like VHDL with/select

I am trying to find a way to conditionally assign values to a signal in verilog similar to the with/select in VHDL. So far I found two ways https://www.chipverify.com/verilog/verilog-4to1-mux. This is ...
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3answers
73 views

How to implement a continuously scanning multi-channel system in Verilog

I currently have a multi-channel system where each channel is receiving a pulse at different times. I want whichever channel receives its pulse first to act as the reference to then measure the time ...
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0answers
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Why is my FPGA clock so slow

To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this: <...
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2answers
150 views

VHDL: port declaration design for a feedback signal

I am a Computer Engineering student currently learning computer architecture, and working on modeling a booth's algorithm in VHDL. My design hierarchy contains a datapath and a control unit. The ...
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2answers
83 views

VHDL: on variable declarations to act as register

I am currently a CPE student taking up computer architecture, learning how to model major computer components using VHDL. Currently, I am working on a shift register as a sub component for a top-level ...
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1answer
85 views

Model running slower than RTL in SystemVerilog

I'm testing an RTL implementation of a certain block from a 3rd party company in SystemVerilog using Questa. The block is fairly large and my block which acts as a wrapper around it is also large. The ...
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1answer
42 views

Doubt in non-blocking regarding order of execution

If I have theses statements: output reg [7:0] cnt; initial cnt=8'b00000001; always @(posedge clk) begin cnt<=cnt<<1; cnt[0]<=cnt[7]; end Now in this ...
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1answer
35 views

Doubt in non-blocking statement verilog

Suppose i have 2 non-blocking statements as follows: reg x,y; initial begin x=10; y=20; end and if I execute this: a) ...
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1answer
113 views

Copying Queues to Dynamic Arrays

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1answer
145 views

How do I fill a SystemVerilog Queue variable?

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2answers
69 views

Testbench using Task operation [closed]

I have to write a testbench using "tasks" to verify the functionality of an 8-bit ALU. My tasks are not getting simulated properly in EDA playground. Can anyone please tell me where my ...
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2answers
90 views

What will happen if the reset button is not pressed while running a synchronous counter on FPGA (using verilog)?

I was using the following code for a multiplexing circuit to activate 7 seg display on the Basys 3 FPGA. As for multiplexing circuit you don't often need to press a reset, so I was just wondering What ...
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1answer
129 views

SystemVerilog Assertions syntax error unexpected |-> [closed]

I'm starting to use SVAs for formal verification. I run QuestaSim2019 and I can successfully import uvm_pkg (is it needed to use assertions anyways?): as I do ...
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0answers
92 views

SystemVerilog: copy a slice from a vector to another vector of different size

as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location. Example: ...
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2answers
93 views

Clock usage in the always block and in the event

In general, if we are working on a sequential circuit, say a Flip Flop (e.g. D Flip Flop) The code we write for the always block part is: ...
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1answer
83 views

Is this the correct truth table to determine whether or not to execute an interrupt in a RISC V system?

I'm working on implementing the privileged RISC V ISA, which can be found here. I'm looking at the bottom of page 20, and the interrupt conditions are stated very confusingly: Global interrupt-...
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1answer
79 views

How does assignment work in Verilog?

I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...
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2answers
153 views

Is it possible to have a register with multiple drivers?

This is just a theoretical question I have. Imagine we have a register (a reg signal in Verilog for example) and two possible inputs that have to write to that register. I am assuming all signals are ...
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3answers
111 views

Using too many Modules in Verilog affect timing?

I have a straightforward quest about HDL and FPGA design. If I seperate my code to a lot of modules, by modules I mean verilog files which do specifig things instead of writing close to the top ...
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3answers
52 views

Why to use signal in this VHDL code?

Here is my code for 4 to 1 mux: ...
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1answer
194 views

Help on writing test bench for up counter in verilog

preamble: I think I have enough understanding of logic circuits and enough experience in programming from other languages(C, python, etc.) However, I am very new at Verilog and also have never used ...
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1answer
102 views

Open source CPU HDL decriprion? [closed]

I'd like to get familar with an implemebtaion of modern CPUs. Are there Amy processors with an open-source Hardware Decriprion Language? Perfectlt, I'd like to take a look at Intel/AMD implemebtaion, ...
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2answers
415 views

Verilog: Can't resolve multiple constant drivers for net

I am writing a code sung Quartus IDE: The following is my code: ...
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3answers
767 views

Verilog code "always @" block not working as expected

My Verilog code samples the input (Vin) at fixed intervals using a counter. The counter is a 2-bit register whose value increments at every positive edge of a clock ...
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1answer
380 views

3-Stage Shift Register using Blocking assignment in Verilog - Differences among simulators

Simulation of a 3-stage shift register using blocking assignment statement in Verilog gives different simulation results across simulators: The RTL code is as follows: ...
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1answer
149 views

How is AI being used these days in designing ASIC? [closed]

Is AI used in HDL synthesis or design? For example, I would imagine that the process of place-and-route could benefit tremendously from the past decade developments in AI and Deep Learning. How do ...

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