Questions tagged [hdl]
HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.
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Can anyone please take a look of this Verilog HDL code? Does it look strange by any means?
I am wondering if it is ok to use output instead of wire for another output in Verilog coding (using Quartus for this). Just ...
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My 1-bit ALU is not able to do subtraction [closed]
I am trying to make a 4-bit ALU in Verilog which can perform the following functions:
Add
Subtract
Compare (>,<,=)
AND
The approach I have taken is to make 4, 1-bit ALUs and connect them in ...
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How to legally/properly run a Verilog file that needs other files?
I have written a simple ripple carry adder in Verilog (in a structural fashion), and I have defined the required half adder in a module in another file. When I run them (using ...
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Why does this Verilog code work without "wire" statements?
My textbook (Brown and Vranesic) gives the following code for a simple 4-bit RCA implementation in Verilog:
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How do I easily create waveform for an expression having more than one signal inside an "if else" block in Vivado?
In a sample code where I have 2 net type variables, I want to plot a waveform for a conditional statement like this:
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Logical AND vs Bitwise AND for single bit and multibits [duplicate]
What is the functional and physical difference in using Logical AND ( && ) and Bitwise AND (&&) over singlebit and multibit signals.
Below shared cases.
case 1: A[3:0] & B[3:0] = ?...
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How to do clock signal rising edge detection in Chisel (scala)?
I have encountered in a problem of rising edge detection in writing chisel code. Here is the code I wrote.
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Parsing variable-sized data in 32-bit datastream
I have a 32-bit datastream coming from a sensor. The data is encoded as a Type-Length-Value encoding. This means the first byte indicates what kind of data there is and the second byte contains the ...
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What's the correct way of port declaration while instantiating modules in Verilog HDL?
From what I know, if we need to instantiate module1 in module2, then I need to declare all the ...
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Why does this Verilog testbench not undergo a race condition?
This is the testbench in question:
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How do I figure out if my Verilog code output was generated out of race condition?
Apart from physical observation, is there a way to know if my code will undergo a race condition?
For example, the following code has a race condition because both ...
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How do I use conditional compilation in Xilinx Vivado?
I want to conditionally include one of three files if the respective macro for that file has been defined. Normally I would define the macros in a separate file, say ...
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How do I create a 2D array in Verilog?
I want to use a 2D array in a Verilog testbench. I tried it this way:
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What's the purpose of "functions" if they can be replaced by "tasks" in Verilog HDL?
In Verilog, a task can do everything that a function can along with having other features. Then what's the purpose of having ...
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What am I doing wrong with this 2x2 Karatsuba Multiplier in Verilog HDL?
I am trying to implement a 2x2 karatsuba Multiplier which I will be using as a base case for a higher bit multiplier.
Here's the code:
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Why is my Karatsuba multiplier not giving right answers for large numbers?
I tried to implement 16-Bit Karasutba Multiplier in Verilog HDL. It gives me right answers for small numbers, but it's incorrect for large numbers.
Can someone point out what's wrong?
Here's the ...
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How can I compare the speed of two algorithms implemented in verilog HDL without using FPGA?
I have implemented two 32 bit multiplier algorithms (Booth and Karatsuba) in verilog HDL. I wanted to make a comparison of the time taken by both algorithms to multiply same numbers. How can I do that ...
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How do I instantiate modules within case statements in Verilog HDL?
I am trying to make a sequence detector with 4 modes - Moore machine overlapping & non-overlapping and Mealy machine overlapping & non-overlapping.
But writing my code like this gives me an ...
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How do you invert a section of a four bit wide signal in Verilog?
I'm working on this lab from the ETH Zurich course on Digital Design.
I'm creating a truth table for signals to lines in a 7-segment number display. The display is controlled by a 4-bit input.
One of ...
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How to write program counter in SystemVerilog?
I was trying to build an 8-bit program counter, and it should support branching. This is what I wrote:
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Delaying falling edge, and faster rising edge for output signal [closed]
I'm trying to take an incoming signal to use as an output, but that output (active low) needs to be enabled about 20ns after the incoming signal goes low, and then go high again about 20ns before the ...
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When using Cocotb, should I be using FallingEdge to set and assert values?
I'm attempting to use Cooctb to verify a simple Verilog counter with a reset:
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Basic addition not working as expected
I'm trying to add two numbers together, and it's giving an odd result.
Here's the code,
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What value will be assigned to x, is it a or ~x?
I have some Verilog code for which I am unsure of the outcome of the non-blocking assignment of x as shown below :
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How flexible are modern HDL Synthesis tools in terms of output primitives?
As a firmware guy I'm fascinated with porting tools like GCC to support arbitrary weird processors, which nowadays can be manifested on FPGAs with relative ease. I'm curious whether something ...
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Identifying an edge INSIDE an 'always' block
I am an experienced C programmer trying to learn enough Verilog to create a brushless motor controller. I am nearly done except for one detail. I want to do something like this:
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Are there other examples of applications of a priority arbiter apart from sharing system bus or memory?
I was wondering where else a priority arbiter is used in the real world, apart from sharing a system bus or memory. I tried googling, but couldn't find any other examples.
For context: I'm working on ...
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Are SR latches bad in ASIC design?
I am implementing an ASIC design, and my current solution for a problem requires an SR latch. I've always been told that latches are bad in FPGA and ASIC designs, but never got a proper answer as to ...
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Verilog counter is not working using @always statement
I am trying to implement counter using Verilog HDL
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Dense Neuron Neural Network in Verilog
I am trying to build NN in system verilog, but I am facing a problem with neuron implementaion, as it only displays 'x'.
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Why I am having x as output from ReLU?
I am trying to test ReLU, but it always gives 'x' for the output.
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VHDL: Variables depending on other variables
If I'm in a process and I have a variable (A) changing and a different variable (B) changing based on the original variable (A), does other variable (B) change based on the new value or the initial ...
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Performance metrics for a VHDL/Verilog RTL design
Correctness and performance is everything in programming. Verifying it for software is relatively easy because you can "just" run the program and see if it crashes and/or is very slow. ...
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Unpacked and Packed Arrays
I have been reading on the unpacked and packed arrays in SV. I have mostly understood the concepts and style with which arrays are declared. However, there are some particular cases:
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FPGA applications in power electronics [closed]
I'm a power electronics hardware design engineer and I'm trying to build some additional skills like a sub-branch. I've always been interested in FPGAs and I decided to combine my major skill with my ...
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Sequence of execution of "always" and "generate" blocks
I'm fairly new to Verilog. I have been writing some code by myself and need some help. The following is the code for a serial to parallel interface.
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Alternative to using FSM for implementing round robin
It is easy to implement round robin (A->B->C->A->B->C..) using FSM in VHDL. Is there an alternative to FSM? For some reason, I have a feeling there is a nice and neat implementation ...
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Difference in synthesis between bitwise AND (&) and logical AND (&&)
Would these two code snippets synthesize the same way? I know this will be tool dependent because all synthesizers are slightly different. That being said, I think they probably tend to agree on this ...
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Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?
I write some library module on SystemVerilog. I want to check input parameters on synthesis and then if their values are wrong I want to stop synthesis with a custom error that will tell which ...
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Why does adding "& 1" to an assign statement produce a completely different synthesis?
I am trying to implement a one-bit full adder in Verilog. Here's my original code:
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Why is order of bits not getting reversed?
In this code, while declaring in and out, the seventh bit of input is MSB, while the zeroth bit of output is MSB. So, why is the ...
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Modelsim Altera not working [closed]
Hi i'm new to verilog designing and i'm trying to simulate but modelsim doesn't even load the design, i'm glad if someone could help, thanks.
( counter and contatore are two modules that i included in ...
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Syntax error Begin statement HDL 9-806
I have an error in the form of HDL 9-806 on the begin statement.
The code below is a button based sequence detector an addition LED flash when sequence is correct with a debouncer to stop multiple ...
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454
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What is the logic behind the behaviour of reg in Verilog?
I know SystemVerilog and now I'm trying to learn pure Verilog. I find the way reg works to be rather odd. I thought wire is used ...
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Build on-chip ROM in HDL
I wrote the next code in quartus 15.0, where I show what I want to do for a specific project. I can write it both in VHDL and Verilog HDL, but verilog is notoriously shorter.
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Ternary operator doesn't work in Icarus Verilog
I have the following Verilog modules, which I'm simulating with Icarus Verilog. It seems that the ternary operator doesn't work, or has a bug:
main module (i2c_app_tb.v)
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Why Hardware Description Language?
Before moving to understand the purpose of Hardware Description Language(HDL), we need to know what is HDL?
From wiki,
A hardware description language enables a precise, formal description of an ...
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What is the difference between throughput and operating frequency of a digital system?
I am designing a digital system with 2 pipeline stages. While synthesizing the design in Xilinx ISE, I find that the latency of the critical path is 19ns. The clock period estimate for my design is ...
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Positive edge reset and negative edge reset
I am new to Verilog and I am trying to implement an asynchronous reset.
I have difficulties understanding the difference between using ...
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