Questions tagged [hdl]

HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

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Dynamic Huffman Compression FPGA: How to implement

I wanted to create a dynamic huffman decoder that has data formatted according to RFC 1951 and output decoded data for an LZ77 module. So far, after getting the lengths for the code length alphabet, I ...
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1answer
45 views

Analyzing large verilog/hdl code (Tools and Tricks?) [closed]

In general, do you have any advice for trying to analyze big hdl files with little/insufficient commenting? I am currently looking at a fairly complicated hdl core comprised of several other ...
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1answer
113 views

How is AI being used these days in designing ASIC? [closed]

Is AI used in HDL synthesis and design? Fir example, I would imagine that the process of place-and-route could benefit tremendously from the past decade developments in AI and Deep Learning. How ...
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78 views

How to generate signal who have value less then one clk in vhdl? [closed]

How to generate signal who have value less then one clk in vhdl? Signal req is generate base on input signal dat1 and dat2. If they are equals, signal req have value of 1 less then one clk. On ...
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154 views

Why would this cause a latch?

I'm reading ZipCPU's tutorial and got confused. Specifically, I'm referring to this page. To transcribe the Verilog code: ...
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1answer
84 views

What kind of FSM is it, if outputs depend on internally generated signals?

The classical definitions are that in a Moore machine the outputs depend only on the state, while in a Mealy machine they are also allowed to depend on inputs. But what if outputs and/or state ...
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15 views

Finding duplicate reference designators in Design Entry HDL Schematic

This is related to Allegro Design entry HDL schematic. we have imported few pages from other design to current design and Integrated to current design. Because of that we saw few reference ...
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1answer
100 views

How to implement 32-bit adder logic using two 16-bit adders?

I've been trying to implement a 32-bit adder by instantiating two 16-bit adders. The code is compiling but failing some test cases. I don't know what is going wrong in this. verilog code ...
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2answers
141 views

Verilog latch occurring with instantiating modules with in a generate statement

I am trying to create a register file in Verilog. To do this, I am instantiating multiple instances of a register module I designed in a generate statement. Each module uses a different input and ...
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3answers
88 views

Verilog: negative value in brackets of vector signal definition

I am looking at the code in the following website. https://www.csee.umbc.edu/~tinoosh/cmpe641/slides/05-Memories.pdf In their code, they claims something like input signed [7:-12] c_in; I am ...
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1answer
46 views

Two questions about testing with HDL designer

I hope it's okay to ask about specific programs here. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through ...
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2answers
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“Increase” of a register in VHDL and hardware synthesis

Suppose you have already defined a register (for instance called "reg") in VHDL, for instance as a vectors of 4 bit. Now consider the operation: reg <= reg + 0001; it is like reg ++ in C. My ...
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3answers
153 views

VHDL process' sensitivity list

I do not understand the precise role of the sensitivity list in a process in VHDL. For instance, consider an architecture with 3 input signals: a, b, c. I read that if we write: PROCESS (a, b) we ...
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1answer
129 views

SystemVerilog FIFO problem with 6 bits in and 4 bits out

I was trying to induce the following functionality into SystemVerilog but i cant think of any efficient ways: So above is a picture of two 6-bit input packets that come one after the other (triggered ...
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4answers
131 views

How to avoid big mux in RTL design?

When doing rtl design, mux is always used to select the input of a block/module, for example: ...
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1answer
119 views

How to automate Instantiation of modules in Verilog? (permutation)

Consider this file tb_sr_latch.v: ...
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1answer
36 views

create sr_latch from gates in verilog

consider this file : tb_sr_latch.v ...
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1answer
100 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in ...
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3answers
781 views

VHDL: is there a way to create an entity into which constants can be passed?

Lets say we want to create a generic t flip flop counter, the structure of this kind of counter is perfectly repetitive, and you can synthesize one with arbitrary length just using a ...
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2answers
344 views

Are Verilog if blocks executed sequentially or concurrently?

I'm learning Verilog with some background in VHDL and C. I would like to know if Verilog if blocks are executed concurrently or not, and if this is IDE- or vendor-dependent. For example, are the ...
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2answers
150 views

Why we need non-blocking assignments in Verilog?

I understand the basics of blocking and non-blocking assignments in verilog. I understand that blocking assignments execute in a sequential manner,whereas it is possible to assign values concurrently ...
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1answer
105 views

Verilog if else if construct

I have verilog code that looks like this begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end ...
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1answer
76 views

Why is 7:1 video serialization required?

I am trying to migrate portions of a ZYNQ design from one platform to another. Part of the project is based on Avnet's ALI3 touchscreen kit. From the docs: The 7-inch Zed Touch Display Kit includes ...
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1answer
111 views

Too many ports expected in verilog? [duplicate]

I get an error saying i have to many port connections when I try to model sim, but clearly I have the right amount. Whats wrong with my design ?? As you can see the error appears in line line 16 of ...
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2answers
390 views

Are nested modules allowed in Verilog?

module A (input a, input b) ... module B (input a, input b) ... endmodule endmodule Is the above allowed in Verilog?
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Instantiating modules in SystemVerilog

This is a picture of a system that I am building: (original) I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
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1answer
1k views

Unknown Formal Identifier in VHDL

I am facing an error with my VHDL code. I am new in it. After putting so much of my time I am even unable to resolve this error. I am using ModelSim software for it. Here is my code: ...
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2answers
339 views

Can I use 8 bits out of 16 bits as signed bits in verilog?

Generally Verilog takes the first bit of any bit pattern as signed bit. I know that -4 can be represented in signed representation as ...
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1answer
216 views

Can I use custom data types to exchange data between modules in VHDL?

I'm new to VHDL and currently try to get more complex data types working, so that code becomes more readable... However, it seems that I cannot define a type in VHDL before the ...
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1answer
184 views

I write this module to arithmetic shift to left and right in verilog

this is my code: module zero(out,A,B); output signed[5:0] out; input signed[5:0] A,B; assign out = A[5:0]<<<2 + B[5:0]>>>1; endmodule ...
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3answers
118 views

HDL code convention for register resets

When it comes to (synchronously) resetting registers in HDL (I'll use Verilog), is it considered bad practice to code the reset combinatorially? As far as I can tell, the following two snippets are ...
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1answer
199 views

Are there CPLD / FPGA toolchains and workflows that bypass vendor IDEs? [duplicate]

Custom programming for FPGA boards is a similar and helpful question for any with the same as this, but they are different. In that thread they discuss custom options and building their own. This ...
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1answer
105 views

Clock frequency of FPGA circuit and 4-bit counter [closed]

I have implemented a 4 bit counter using HDL. Now I have downloaded the code to an FPGA kit with a 50 Mhz oscillator. This means that the clock period will be equal to 0.02 microseconds and ...
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2answers
112 views

Strange behavior in VHDL design (randomly incrementing values)

I have a fairly simple VHDL design that looks like the following: ...
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1answer
26 views

Can specific pipeline latency arithmatic block be inferred when using * or / operator in VHDL?

When using the * or / in VHDL, the synthesis tool shall infer the appropriate IP block to carry out that operation. If we open the actual GUI for that IP block we can find a lot of options e.g select ...
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1answer
125 views

What is the proper methodology to create portable FPGA designs?

FPGA designs may contain RTL along with IP blocks. These IP blocks most likely shall be from the vendor of the FPGA. Examples of such IP blocks are instantiating dual clock FIFOs, floating point and ...
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2answers
267 views

(System)Verilog: extracting a smaller bus/vector from a larger bus?

What is the best practice for creating a bus, which is just extraction of certain bits of a larger bus. I do not want to store the index numbers to make the lookup in the generate-for if it could be ...
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1answer
413 views

How to compare a re-writable 4 bit value to a given 4 bit input in Verilog?

The goal of this project to design a computational lock alarm in Verilog to be run on an Altera board (note on the board 0 is actually ON and 1 is OFF). Based on the design criteria I created a state ...
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2answers
234 views

How to get the MSB into a logic gate which will check if a number is negative or not?

I need to create a logic gate which will find out whether a number is negative or not. The input is 8 bits and the output is 1 bit, and if the input is 1 (i.e. negative number) then the output ...
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0answers
755 views

Variable input MUX in Verilog

What's the best way to make an N:1 multiplexer in Verilog (NOT SystemVerilog), where the maximum N is 64? Each input is 32-bits wide and there are N such inputs. Verilog doesn't allow two-dimensional ...
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1answer
80 views

How to have an in-system check in an FPGA based system that it has been reset?

I have a system based on Altera's MAX10 device that is doing the following tasks: receives the data and stores it on an on-chip flash memory only once. reads all the data from on-chip flash, stores ...
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1answer
1k views

Vivado simulation stuck at 0 fs

I am trying to simulate a D flip flop using Vivado 2018.2.2. But upon running the simulation a window pops up stating Current time: 0 fs. The program doesn't freeze, it just doesn't progress. Here is ...
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1answer
376 views

Net type, variable type, data type and data objects

I am really confused by the conception of net type, variable type, data type and data objects in SystemVerilog. I am using the simulator inside Xilinx Vivado 2018.02 for all the following codes. <...
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1answer
59 views

Can demultiplexers be synthesized?

In my digital design module involving HDL (Verilog) and a ton of RTL diagrams, our lecturer always said never to use demultiplexers because they do not exist. Why is that?
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1answer
118 views

How exactly does $cast work

When a $cast is executed between a base and a derived class objects, does it allocate more memory for the derived class handle? ...
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3answers
192 views

What exactly lies between an HDL and a circuit?

I'm trying to learn basics of hardware design process to get a better understanding of how CPUs, microcontrollers etc work and how are they made. My googleing gave me many articles with info like "...
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2answers
90 views

how to trigger another clk in mainclk (verilog)

I wrote somekind of prescaler in verilog to make sclk_adc signal from clk_i. by now my code looks like: always @(posedge clk_i) begin //generation of sclk_adc end ...
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2answers
307 views

Xilinx ZYNQ/ARTIX7 Invert Clock without inducing skew

For HDL design I'm currently developing for a zynq SoC, I need to invert a clock signal because of a swapped differential pair on board level. Using "NOT" to invert adds a LUT in the path and as ...
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1answer
334 views

Using compiler directives and macros in verilog, how to use multiple macros conditionally in verilog?

I have 2 macros in verilog used them as below. ...
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2answers
159 views

How to model electric power consumption in verilog-a?

I am modeling an analog device using verilog-a (to which I am quite new). I would like the model to match the power consumption of the physical device, for which the energy cost associated with state ...

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