Questions tagged [hdl]

HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

Filter by
Sorted by
Tagged with
0
votes
0answers
39 views

ADS1115 I2C won't communicate with CPLD

I have an EPM240T100C5, which is a 240 LE CPLD with a 50MHz internal clock. And as part of a project, I need an ADC, which means that I cannot use too much logic elements, thus, I create a simple ...
0
votes
1answer
40 views

TeraTerm can't detect the correct port, FPGA Project

I'm a beginner at FPGA design and have been actively trying to complete new projects to get more hands on experience. The project I'm currently working on is a tutorial from nandland. This video ...
2
votes
2answers
161 views

Asking if this module is physically possible?

I am an electronics student and learning Verilog. I had an assignment to build an clock divider for arbitrary frequency. I have made a module that works, ...
2
votes
2answers
101 views

Implementing an SHA256 algorithm in an FPGA - Error during timing analysis

I ve updated this question because of manange to improve a bit. Right now i have no timing issues anymore but when i try to hash something on the board, my output on TeraTerm will be some random ...
0
votes
0answers
56 views

tag replication circuitry

I found a question to practice so I can increase my experience in RTL design. I am trying to come up with a generalized design which can support all these requirements. Here are the details: Black-box ...
4
votes
2answers
57 views

Verilog conditional assignments without using procedural blocks like VHDL with/select

I am trying to find a way to conditionally assign values to a signal in verilog similar to the with/select in VHDL. So far I found two ways https://www.chipverify.com/verilog/verilog-4to1-mux. This is ...
1
vote
3answers
60 views

How to implement a continuously scanning multi-channel system in Verilog

I currently have a multi-channel system where each channel is receiving a pulse at different times. I want whichever channel receives its pulse first to act as the reference to then measure the time ...
1
vote
0answers
90 views

Why is my FPGA clock so slow

To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this: <...
2
votes
2answers
115 views

VHDL: port declaration design for a feedback signal

I am a Computer Engineering student currently learning computer architecture, and working on modeling a booth's algorithm in VHDL. My design hierarchy contains a datapath and a control unit. The ...
0
votes
2answers
55 views

VHDL: on variable declarations to act as register

I am currently a CPE student taking up computer architecture, learning how to model major computer components using VHDL. Currently, I am working on a shift register as a sub component for a top-level ...
2
votes
1answer
62 views

Model running slower than RTL in SystemVerilog

I'm testing an RTL implementation of a certain block from a 3rd party company in SystemVerilog using Questa. The block is fairly large and my block which acts as a wrapper around it is also large. The ...
-2
votes
1answer
29 views

Doubt in non-blocking regarding order of execution

If I have theses statements: output reg [7:0] cnt; initial cnt=8'b00000001; always @(posedge clk) begin cnt<=cnt<<1; cnt[0]<=cnt[7]; end Now in this ...
0
votes
1answer
31 views

Doubt in non-blocking statement verilog

Suppose i have 2 non-blocking statements as follows: reg x,y; initial begin x=10; y=20; end and if I execute this: a) ...
1
vote
1answer
57 views

Copying Queues to Dynamic Arrays

...
1
vote
1answer
76 views
1
vote
2answers
60 views

Testbench using Task operation [closed]

I have to write a testbench using "tasks" to verify the functionality of an 8-bit ALU. My tasks are not getting simulated properly in EDA playground. Can anyone please tell me where my ...
0
votes
2answers
85 views

What will happen if the reset button is not pressed while running a synchronous counter on FPGA (using verilog)?

I was using the following code for a multiplexing circuit to activate 7 seg display on the Basys 3 FPGA. As for multiplexing circuit you don't often need to press a reset, so I was just wondering What ...
0
votes
1answer
59 views

SystemVerilog Assertions syntax error unexpected |-> [closed]

I'm starting to use SVAs for formal verification. I run QuestaSim2019 and I can successfully import uvm_pkg (is it needed to use assertions anyways?): as I do ...
1
vote
0answers
66 views

SystemVerilog: copy a slice from a vector to another vector of different size

as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location. Example: ...
0
votes
2answers
74 views

Clock usage in the always block and in the event

In general, if we are working on a sequential circuit, say a Flip Flop (e.g. D Flip Flop) The code we write for the always block part is: ...
1
vote
1answer
62 views

Is this the correct truth table to determine whether or not to execute an interrupt in a RISC V system?

I'm working on implementing the privileged RISC V ISA, which can be found here. I'm looking at the bottom of page 20, and the interrupt conditions are stated very confusingly: Global interrupt-...
0
votes
1answer
71 views

How does assignment work in Verilog?

I am trying to encapsulate my fast adder design with a top module containing input and output registers. All combinational logic is present in the instantiated module. The purpose of top design is to ...
1
vote
2answers
76 views

Is it possible to have a register with multiple drivers?

This is just a theoretical question I have. Imagine we have a register (a reg signal in Verilog for example) and two possible inputs that have to write to that register. I am assuming all signals are ...
1
vote
3answers
97 views

Using too many Modules in Verilog affect timing?

I have a straightforward quest about HDL and FPGA design. If I seperate my code to a lot of modules, by modules I mean verilog files which do specifig things instead of writing close to the top ...
0
votes
3answers
48 views

Why to use signal in this VHDL code?

Here is my code for 4 to 1 mux: ...
0
votes
1answer
103 views

Help on writing test bench for up counter in verilog

preamble: I think I have enough understanding of logic circuits and enough experience in programming from other languages(C, python, etc.) However, I am very new at Verilog and also have never used ...
0
votes
1answer
101 views

Open source CPU HDL decriprion? [closed]

I'd like to get familar with an implemebtaion of modern CPUs. Are there Amy processors with an open-source Hardware Decriprion Language? Perfectlt, I'd like to take a look at Intel/AMD implemebtaion, ...
-3
votes
2answers
213 views

Verilog: Can't resolve multiple constant drivers for net

I am writing a code sung Quartus IDE: The following is my code: ...
1
vote
3answers
506 views

Verilog code “always @” block not working as expected

My Verilog code samples the input (Vin) at fixed intervals using a counter. The counter is a 2-bit register whose value increments at every positive edge of a clock ...
1
vote
1answer
202 views

3-Stage Shift Register using Blocking assignment in Verilog - Differences among simulators

Simulation of a 3-stage shift register using blocking assignment statement in Verilog gives different simulation results across simulators: The RTL code is as follows: ...
-1
votes
1answer
147 views

How is AI being used these days in designing ASIC? [closed]

Is AI used in HDL synthesis or design? For example, I would imagine that the process of place-and-route could benefit tremendously from the past decade developments in AI and Deep Learning. How do ...
0
votes
1answer
83 views

How to generate signal who have value less then one clk in vhdl? [closed]

How to generate signal who have value less then one clk in vhdl? Signal req is generate base on input signal dat1 and dat2. If they are equals, signal req have value of 1 less then one clk. On ...
0
votes
2answers
169 views

Why would this cause a latch?

I'm reading ZipCPU's tutorial and got confused. Specifically, I'm referring to this page. To transcribe the Verilog code: ...
0
votes
1answer
131 views

What kind of FSM is it, if outputs depend on internally generated signals?

The classical definitions are that in a Moore machine the outputs depend only on the state, while in a Mealy machine they are also allowed to depend on inputs. But what if outputs and/or state ...
0
votes
1answer
394 views

How to implement 32-bit adder logic using two 16-bit adders?

I've been trying to implement a 32-bit adder by instantiating two 16-bit adders. The code is compiling but failing some test cases. I don't know what is going wrong in this. verilog code ...
0
votes
2answers
182 views

Verilog latch occurring with instantiating modules with in a generate statement

I am trying to create a register file in Verilog. To do this, I am instantiating multiple instances of a register module I designed in a generate statement. Each module uses a different input and ...
2
votes
3answers
1k views

Verilog: negative value in brackets of vector signal definition

I am looking at the code in the following website. https://www.csee.umbc.edu/~tinoosh/cmpe641/slides/05-Memories.pdf In their code, they claims something like input signed [7:-12] c_in; I am ...
0
votes
1answer
63 views

Two questions about testing with HDL designer

I hope it's okay to ask about specific programs here. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through ...
2
votes
2answers
84 views

“Increase” of a register in VHDL and hardware synthesis

Suppose you have already defined a register (for instance called "reg") in VHDL, for instance as a vectors of 4 bit. Now consider the operation: reg <= reg + 0001; it is like reg ++ in C. My ...
3
votes
3answers
859 views

VHDL process' sensitivity list

I do not understand the precise role of the sensitivity list in a process in VHDL. For instance, consider an architecture with 3 input signals: a, b, c. I read that if we write: PROCESS (a, b) we ...
0
votes
1answer
354 views

SystemVerilog FIFO problem with 6 bits in and 4 bits out

I was trying to induce the following functionality into SystemVerilog but i cant think of any efficient ways: So above is a picture of two 6-bit input packets that come one after the other (triggered ...
0
votes
4answers
374 views

How to avoid big mux in RTL design?

When doing rtl design, mux is always used to select the input of a block/module, for example: ...
0
votes
1answer
189 views

How to automate Instantiation of modules in Verilog? (permutation)

Consider this file tb_sr_latch.v: ...
0
votes
1answer
56 views

create sr_latch from gates in verilog

consider this file : tb_sr_latch.v ...
0
votes
1answer
255 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in ...
5
votes
3answers
1k views

VHDL: is there a way to create an entity into which constants can be passed?

Lets say we want to create a generic t flip flop counter, the structure of this kind of counter is perfectly repetitive, and you can synthesize one with arbitrary length just using a ...
1
vote
2answers
2k views

Are Verilog if blocks executed sequentially or concurrently?

I'm learning Verilog with some background in VHDL and C. I would like to know if Verilog if blocks are executed concurrently or not, and if this is IDE- or vendor-dependent. For example, are the ...
2
votes
2answers
679 views

Why we need non-blocking assignments in Verilog?

I understand the basics of blocking and non-blocking assignments in verilog. I understand that blocking assignments execute in a sequential manner,whereas it is possible to assign values concurrently ...
1
vote
1answer
229 views

Verilog if else if construct

I have verilog code that looks like this begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end ...
0
votes
1answer
162 views

Why is 7:1 video serialization required?

I am trying to migrate portions of a ZYNQ design from one platform to another. Part of the project is based on Avnet's ALI3 touchscreen kit. From the docs: The 7-inch Zed Touch Display Kit includes ...

1
2 3 4 5