Questions tagged [instruction-set]

Instruction set refers to the Assembly syntax based on a processor's architecture that interacts with its registers within the processing unit itself. There is a large variety of instruction sets including: MIPS, ARM, 68HC11/12, x86, and so forth.

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imm8 in ARM data-processing instruction

In ARM, Data-processing instructions have an unusual immediate representation involving an 8-bit unsigned immediate, imm8, and a 4-bit rotation, rot. imm8 is rotated right by 2 × rot to create a 32-...
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Difference between clock cycle, machine cycle and instruction cycle of the CPU

There is a lot of ambiguity between the definition of these three terms. So, I wanted to know what is the intuition behind these terms and how all three are connected to each other.
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MU0 register transfer level organization by adding index register

Q. Write the MU0 register transfer level organization by adding index register. Give the control logic for the following instructions and explanations. LDA S,X ; A:=mem((S)+[X]) STA S,X ; mem((S)+[X])...
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Linkage pointer in procedure

https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-computation-structures-spring-2017/c12/c12s3/procedures_answers.pdf I don't understand how the linkage pointer can be the ...
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What is the difference between Computer Organization and Computer Architecture?

I am still not getting a clear picture from any textbooks. Anyone, please elaborate with examples. What does 8086 architecture block diagram refer to?
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what were the ENIAC's equivalent to the modern CPU's elements?

If a modern CPU contains these elements: - 3 or more register units - ALU - control unit and the CPU is connected to a RAM composed of several addresses, what ...
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Most bare-bones way to use a CPU? (How to learn)

I know a bit of programming but am brand new to lower-level stuff so please forgive the naivety of this question. What would be the most direct way of executing a series of commands on a CPU to do a ...
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DAA operation in 8085 microprocessor

Let the content of register A is 98H. Both Auxiliary Carry flag and Carry flag are set i.e. AC=1 & Cy=1. If now I execute DAA once, both nibbles will get added with (0110) and the result is FEH ...
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12-bit homebrew computer?

I'm planning my first homebrew computer. I'd like to perform calculations with 8-bit numbers. My op codes will be 4-bit numbers. I'll be building this on breadboards so I'd like to keep things as ...
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Designing an instruction set for a homebrew computer

I'm going to begin the adventure of building an 8-bit homebrew computer. Right now, I'm considering the instruction set. SAP-1 seems a bit too sparse, so I'm designing my own. Some facts: My primary ...
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What is the difference in design between a von Neumann and the Harvard's machines?

Although there are many webpages talkink about the difference between the Aiken (prototype: Harvard Mark I) and von Neumann (prototype: ENIAC) architecture, the actual divergence remain uncertain to ...
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How to use only BEQ to perform other conditional branch

Given "Branch if equal(BEQ)" as the only conditional branch and other instruction like arithmetic and unconditional branch instructions, is it possible to perform other conditional branching like ...
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8085;Condition CALL Instruction: if condition fails

In call instruction there are 5 machine cycles S,R,R,W,W (S is 6 T-states opcode fetch) and thus 18 T-states In first machine cycle, t1-t4 is utilized for fetching the opcode and decoding it and t5-...
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MOV C, B instruction in 8085 takes 4T cycles so when and how does the data copies from B to C

As specified all over the internet, MOV C, B instruction in 8085 only takes 4T states to execute but the opcode fetch and decode take 4T states, which means the transfer of data from one register to ...
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Can an instruction set do everything?

Given a certain instruction set, and that any high-level code is just converted to machine code anyway, then except simulating human intelligence, is it sufficient enough to do anything you want a ...
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8085 ;JMP instruction

How exactly is JMP XXXXH; executed ? First the PC(Program counter) will contain the address where this instruction is present. In first machine cycle opcode will be fetched and PC will be incremented ...
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How can a 4-bit CPU have 40 instructions?

Currently, I am using Logisim(yes, still Logisim) to build a 4-bit variant of the 8-bit SAP-1 microcomputer. However, I ran into a problem with the instruction register. Let me explain. The SAP-1 has ...
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8085 ; High impedance state of lower order address/multiplexed data bus during memory read and write machine cycles

The two pictures are of memory read and write machine cycles . Could somebody please explain why in memory read cycle the lower order address / multiplexed data bus is in high impedance state at the ...
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8085; why we can't reduce number of T-states in opcode fetch machine cycle [duplicate]

In the above timing diagram for opcode fetch machine cycle , can we not do the entire operation in just 2 T states like this : In T1 state we first latch the lower order address by making ALE high for ...
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Why do computers have only a few thousand instructions when they could have millions? [closed]

Most computers contain only a couple thousand instructions, but the bit width(usually 64-bit) technically allows computers to have access to millions or even billions of instructions. Some could be ...
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How do computers execute instructions spanning multiple clock cycles?

There are some(or most) instructions in a computer that simply cannot be executed in a single clock cycle. But there lies a problem. How does the program counter in the computer know when an ...
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Where in the instruction pipeline is machine code to microcode translation?

In my computer architecture courses on the N-stage pipeline, I never encountered the concept of microcode. I was surprised, then, when in a performance analysis course assignment, I discovered that ...
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Where to study Cortex R architecture? [closed]

I am interested to study Cortex-R architecture but I cannot find its details online. Is it proprietary detail or should I ask for this information from arm.com? Obviously I am not looking for the ...
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ARM Instruction size vs Instruction encoding

I cannot make sense of the difference between 'Instruction size' and 'Instruction encoding' specially about ARM and Thumb ISA's as explained here: Can we say that Instruction size is 32 bits but its ...
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X86_64 Architecture, how does it handle instructions larger than 64 bits?

I have been looking more into how CPU's work, and have a question. If I have a instruction that e.g. takes a 64bit address and a register, and copies the value from that address into the register. And ...
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DMA and Instruction Pipeline

My university resources say that DMA transfers the bunch of data from IO unit to memory or vice verse when processor is not busy with data and address bus. According to the resources, DMA Controller ...
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Have separate instructions for each register or pass register as argument?

I am trying to design a (very) simple processor architecture. I am in the process of creating a basic instruction set for it, however I am not sure of the best ("best" meaning what most people use - ...
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Micro programming and hard wiring

I have a question about the details of microprogramming and hard wiring in CPU architecture. In hardwiring, we write a code, the compiler translates it to the ISA, then the ISA is run in the hardware....
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store word assembly instruction in risc-v

I'm really confused about the store instruction in risc-v. When I store word from register to memory, after the word is copied into the mem, does it sign-extended or zero-extended or perhaps something ...
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CPU register count and access time [closed]

It has been suggested that one of the reasons typical RISC CPUs stop at 32 architectural integer registers, despite a 32-bit instruction having enough spare bits to specify 64, is that a larger ...
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Design an instruction using Thumb-2

I'm studying the Cortex-M3 of ARM. The problem statement reads: We're going to use a Harvard architecture with the following addressing capabilities: 32M words of code and 16-bit data words. The ...
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What is the role of ISA (Instruction Set Architecture) in the comp arch abstraction stack. [closed]

I have programming background, and I recently started taking computer architecture course. Most of the lectures I see use the some sort of the layering as described in the following diagram explaining ...
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How does an ARM processor in thumb state execute 32-bit values?

What I understand is, the ARM mode can execute 32-bit of instructions and Thumb mode can execute 16-bit of instructions. For instance, Here is the ARM instructions set: And Thumb instructions set: ...
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Why don't we have an instruction called LDAX H in 8085 microprocessor?

Whereas we have instructions such as LDAX B , LDAX D !!!
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Why does out command works wrong? (Proteus 8086)

I am trying to create an output unit for 8086 microprocessor which is connected to MP's 00ABh(10101011) address. I used 74LS373 for that. This is how I made connections: When I run the code below, ...
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Would semi-VLIW make sense?

Typical CPU instruction set: the CPU has several functional units, and when each instruction is read, some bits specify which functional unit is to be activated, while others specify the details of ...
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ISA opcodes---Where do they come from?

When engineers are designing an instruction set architecture, by what procedure or protocol, if any, do they follow when designating certain binary codes as instructions. For example, if I have an ISA ...
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What happens when you fall off the end of main() in a PIC? [duplicate]

Another question included this program: void main(void){ TRISD = 0x00; PORTD = 0xFF; } Let us assume that it does exactly what was intended up through ...