Questions tagged [intel]

Intel is a semiconductor manufacturer headquartered in the United States. They are best known for their x86 range of microprocessors and associated chipsets that are the basis of most personal computers.

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Intel FPGA input voltage between Vil and Vih : what's happening?

Considering these settings: Cyclone 10 LP (or Cyclone II / Cyclone III / Cyclone IV) IO configured as Input LVTTL 3.3V (Vilmax=0.8V Vihmin=1.7V) Voltage between 0.8V and 1.7V on this input No CLK ...
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Why does Intel's CCA (USB3 JTAG control scheme) not let a remote attacker own any system with a flash drive plugged in?

JTAG lets us read / write the architecture states on a CPU core. Intel's CCA let's us connect to JTAG with a USB3 port. So why could an attacker not execute code to trick a flash drive plugged into a ...
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33 views

MP2949A IMVP9 Controller: PSYS Pin for no-battery applications

I'm using MPS2940A Digital Multi-phase Controller with PMBus interface for IMVP8/9 for a PC design that uses Tiger Lake UP3 CPU. Unfortunately, I can't share the datasheet for confidentiality reasons ...
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2answers
93 views

What is the most important CPU price factor [closed]

I have two intel CPUS with distinct features. intel i7 8550U intel i5 8300H Which have big performance difference with the cheaper 8300H being higher in memory ...
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107 views

Finding datasheets for 30+ year old ICs?

Anyone who can lead me in the right direction for finding datasheet for some old ICs? I've googled every possible variation of the numbers, which are: MSM93H002-74 (DIP64, marked OKI/Intel), C1185 (...
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127 views

Difference between ARM7 and intel i3, i5 & i7 processors

I am just starting out on a journey to understand microcontroller and microprocessor design. Have read briefly on their differences (ARM7 and Intel i3, i5 & i7). Couldn't find any information on ...
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67 views

I225 Ethernet Controller - SPI Flash

I'm designing a motherboard with Tiger Lake UP3 CPU, and I want to use Intel I225 Ethernet controller for the LAN ports. I225 reference design includes an SPI flash. I couldn't find what is the ...
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4answers
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Why is the 8061 microcontroller described as having 256 bytes of internal memory?

According to doc (http://www.auto-diagnostics.info/pdf/ford_eectch98.pdf), this 8061 microprocessor chip contains 256bytes of internal RAM (also referred to as register file in the doc). However, the ...
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1answer
43 views

Number of read and write ports on L2 and L3 cache

I have an Intel Core i9-9900K processor (some specs here) and I'm trying to figure out how many read and write ports each level of cache has, for a personal project. I cannot find this in any online ...
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270 views

When did system-on-chip (SoC) arrive in mainstream laptops? Are intel chipsets used in laptops such as XPS 13, SoCs?

An SoC has multiple functional units like CPU, GPU, sometimes DSPs(Digital Signal Processors), memory and many other units embedded in a single chip. Most intel chipsets used in laptops do have ...
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1k views

How are other chipmakers keeping up with TSMC if their processes are just the best?

In the news recently was Intel's stock falling 20% because its 7nm processes are being delayed by 6+ months. The argument seems to be that Intel is already behind (since they're using 10nm processes ...
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83 views

Development Board

i gained some experience with ARM and especially with STM32 MCU models.Now i wanted to start learning x86_64 architecture and my initial goal was going towards it. Is there any good development boards ...
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144 views

What is Symbol Clock Frequency?

I came across the term Symbol Clock Frequency in this Intel programmer reference manual (P131). I could not find what the symbol clock frequency actually is in the manual or online and thought it ...
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1answer
87 views

Why must the VCCA be powered in Cyclone 10 LP even if PLLs are not being used?

The device documentation related to the Cyclone 10 LP FPGA states that "you must power up VCCA even if the PLL is not used". We were comparing the power dissipation of a Microsemi IGLOO2 FPGA with ...
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Connecting a signal to a pin in Quartus

I want to connect a signal in a .v file to a top level pin assigned in the pin planner but I've no idea where to start. I've looked at several guides but as a C programmer this is all quite alien to ...
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1answer
47 views

Can a micro operation pass multiple pipeline stages with a single clock cycle?

I'm learning a CPU architecture and currently found some high-level description of Intel x86_64 CPUs architecture. By the high level description I mean something like the following micro-op flow (...
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174 views

How x86-64 Intel CPU understands how many bytes load into a register

I have the following byte code one the left and and its byte representation on the right: ...
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1answer
1k views
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1answer
231 views

Why can't dual port RAM be read out using the Quartus In-System Memory Content Editor?

Here are the screen shots from Quartus; When I want to instantiate the single port RAM, I get option to assign an instance ID and thus read it using the ISMCE (In-System Memory Content Editor). ...
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51 views

How do CPU, IOMMU and DMA controller interact with each other?

While drawing an interaction diagram involving CPU, IOMMU and DMA controller, I failed to find any authentic document showing how they interact with each other. Is the DMA controller physically a ...
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How does an Intel processor "talk" to an I2C device?

I don't come from an Electronics background, so please bear with me. Assume an Intel processor wants to talk to a temperature sensor over the I2C bus. How does the underlying communication look like? ...
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463 views

Difference between USB host & device when connected to the Intel PCH chipset

I know USB 3.0 Host & Device connector port has the same pin count (VBUS, D+/-, TX+/-, RX+/-, GND), but what is the difference between USB host & device when they are connected to the Intel ...
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IA 32 architecture segmentation

I was reading the 10th edition of "Operating System Concepts" written by Abraham Silberschatz and many others. It says about IA-32 architecture's segmentation: The IA-32 architecture allows a ...
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"recommended that CLK begin toggling within 150 ms ... to ensure long-term reliability of the device" -- why?

In Intel's Pentium Processor Family Developer Manual, regarding the CPU clock, it says that "it is recommended that CLK begin toggling within 150 ms after VCC reaches its proper operating level. This ...
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288 views

Buses and the ALU in the 8086

Intel's 8086 manual shows the following diagram for the CPU's architecture (in page 2-5): If I understand correctly, the ALU's two operands and result are retrieved from / sent to the same 16-bit bus....
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151 views

Where in the instruction pipeline is machine code to microcode translation?

In my computer architecture courses on the N-stage pipeline, I never encountered the concept of microcode. I was surprised, then, when in a performance analysis course assignment, I discovered that ...
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Intel FPGA OpenCL work-group scheduling

I have a question about work-group scheduling on multiple CUs in Intel FPGA. As work-groups are assigned to available CUs, when is a CU considered available? Is it when the last work-item of the ...
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6answers
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Why does Intel's Haswell chip allow floating point multiplication to be twice as fast as addition?

I was reading this very interesting question on Stack Overflow: Is integer multiplication really done at the same speed as addition on a modern CPU? One of the comments said: "It's worth nothing ...
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1answer
126 views

Intel FPGA: applying timing constraints

I have a data signal, select and clock signal which I am sending from the FPGA to another chip and I need to constrain them so I don't violate setup/hold time etc. I have tried to write and SDC file, ...
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318 views

why ARM architecture necessarily dominates the IOT market? [closed]

I would like to understand why do we use ARM for routers, cell phones, cameras, refrigerators, smart tv, and everything. instead of using any other architecture like x86. What are the advantages of ...
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1answer
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Design PC mainboard from scratch [closed]

As a hobbist I always wish to design own PC mainboard. I want to try build such PC based on I3-390m CPU (pga988) and bd82hm55 chipset. Any clue where I can find some datasheet or circuits that can ...
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3answers
119 views

Why system energy is equal to 1/f?

I am studying Intel speed shift. I see a slide: Reference I don't understand, why the green line 1/f means system energy, I think more performance should need more energy as the red line (compute ...
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Intel Compute Stick & USB 4G Device

Id like to create a powerful IoT Edge device that has cellular capability (Wifi is undesirable). Right now the intel compute stick/neural stick almost fits the bill except that it does not have 4G ...
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1answer
46 views

Where the appropriate word size is selected for the operand?

This question is about a 32 bit Intel Chip using x86 assembly. My question specifically is what happens when you do the mov reg, mem instruction where the memory operand is a word (16 bits) from DRAM. ...
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321 views

Why cant we increase chip area?

According to Moore's law, transistors are getting double every 24 months. But now, we have reached the transistor size limit which results in leakage current. Then why can't we increase chip area size,...
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1answer
126 views

Building a simple manual Intel 8085 study kit

I am toying with the idea of building an Intel 8085 demonstration/study kit which would consist of an Intel 8085 microprocessor on a PCB, where all input nodes (including the clock X1, X2) would be ...
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599 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...
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2answers
962 views

Altera has created EPCS and EPCQ devices, can only these be used to store FPGA configuration data?

FPGA configuration data must be stored in external non-volatile memory. Can we use just any flash memory or only specific types? What about EEPROMs or any other nonvolatile memory device? Edit: I am ...
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Two-Terminal Passive Analog Component Tester Using the DE1-SoC Development Board

I am having hard time understanding this problem. I have to draw a Level 1 block diagram for this system. I really appreciated it if somebody can help me. I am new to DE1-Soc. use the Intel DE1-SoC ...
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1answer
347 views

How to determine bandwidth available at USB ports

I am considering a mini-itx single board computer for a project that makes heavy use of USB. I want to ensure that certain USB devices have enough bandwidth. For example I have a data acquisition ...
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257 views

Intel Altera MAX 10 DEV KIT Interface - Can a RS232 6 pin PMOD module by Digilent be used seamlessly with MAX 10 for PC-FPGA UART communication?

I am planning to either purchase a MAX 10 or a DE2-115 dev kit to implement communication via both ethernet and RS-232. DE2-115 has both ports soldered onto the board, but MAX-10 has 2 ethernet ports ...
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2answers
684 views

Why is ACALL instruction a 2 Byte instruction in 8051 microcontroller?

The target address of the subroutine must be within 2K bytes address because only 11 bits of the 2 bytes are used for the address. (Source: http://iamtechnical.com/call-instructions-in-8051-...
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Fan-out of the Intel 8086

I'm studying Intel 8086 processor. I can't understand why the "Fan-out" column is like that in the table below I understand that only one "74 family" chips or five "74LS family" gates can be ...
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What is the purpose of built-in FPGA with Intels new chip [closed]

I know that Intel acquired Altera in 2015 and the new Intel chips include a built-in FPGA. But what is it for?
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Where is the Intel Common Redundant Power Supply (CRPS) Standard Specified?

Intel server reference designs use the Intel Common Redundant Power Supply Standard (CRPS). These documents include a brief over view of CRPS with information like the pin names and refer the reader ...
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1answer
514 views

Intel iGPU die area and power consumption

What is the Intel's iGPU area occupied on the die (or transistor count) and what is the power consumpition of the iGPU alone? Didnt find any information from Intel, quite odd they dont advertise this ...
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590 views

Why DMI instead of a PCIe link

In some Intel chipsets the CPU is connected to the Platform Controller Hub (PCH) by a link called Direct Media Interface (DMI). Based on what I found when researching about it, It's a link very ...
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201 views

Simulate Intel FPGA for software development

i'm currently working for a project for my university. It's about the Intel SoC Embedded Development Suite, and for this i need an actual FPGA board. Unfortunately i'm unable to buy a board, because ...
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1answer
206 views

Can the Intel Curie modules be programmed in assembly using the Quark toolchain?

I've been looking over an Intel Curie module for a project. From the datasheet it looks like the Curie module contains an Intel Quark D1000 embedded processor along with a lot of other components. I'...
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What does the "side-band" and "in-band" mean in the context of digital circuit?

I read below content from the Intel On-chip System Fabric (IOSF) spec. AS I understand, the IOSF is a technology for chip reuse and interconnect. The sideband message interface covers most ...