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Questions tagged [intel]

Intel is a semiconductor manufacturer headquartered in the United States. They are best known for their x86 range of microprocessors and associated chipsets that are the basis of most personal computers.

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Memory Interfacing of 8086

I'm finding trouble doing this exercise from a course I'm taking: Interface 4 RAM's of 64 kB and 4 ROM's of 64 kB, both of which have 2 active low Chip Enable inputs. Also, the circuit has to be done ...
Agus's user avatar
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Most efficiently adapting IPEX-MHF1 (Wifi-Card) to IPEX-MHF4 (Antenna)?

We have a lot trouble with the windows driver our Intel Wi-Fi 6E AX211 Wifi-cards. It randomly looses connection and it's a general problem, that a lot of users ...
Tomblarom's user avatar
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3 answers
118 views

How can I find out what the value of the capacitor on an Intel Core i5-4690 processor?

How can I find out what the value of the capacitor shown in the photo is on an Intel Core i5-4690 processor?
Абдулло's user avatar
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1 answer
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How to properly constrain this hold time?

I am puzzled, can't get to any seemingly simple and, what's more important, solution looking correctly. There's a main fast clock, fclk, and I divide it by 4, ...
Anonymous's user avatar
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Fiber weave effect calculation for a PCB

How can I calculate the angle offset and maximum length? Here is my stack-up: You can consider my signal to be routed in layer 3. Please help in understanding the calculation and concept of it.
Ram_R's user avatar
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1 vote
1 answer
176 views

Unable to write to MT25QU256 from Arria 10 SOM

I am using module Arria 10 SOM by iWave with IC Flash MT25QU256. I am trying to read and write from NIOS II processor to different sectors of this flash. Currently, I'm using the IP Core Generic Quad ...
LowK's user avatar
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0 answers
170 views

Why Intel 4004 published schematics uses NMOS, if the 4004 was produced only with PMOS?

According to Wikipedia[0]: The 4004 employs an 10 μm process silicon-gate enhancement-load pMOS technology on a 12 mm2 die[36] In 2006 Intel released original schematics of 4004 CPU [1]. Seemingly ...
dejw's user avatar
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1 answer
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i8253 manual programming by direct signal input

I have a 8253 programmable interval timer and I want it to work in the Rate Generator (MODE 2). How can I achieve this using direct signal inputs to the chip? I have attempted to write the control ...
EpicMandM's user avatar
1 vote
1 answer
256 views

x86 MUL operation at hardware level

I understand the x86 operation to perform integer multiplication of two numbers (e.g. on 64 bits) is MUL. My question is, how is this operation generally ...
Weier's user avatar
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2 votes
1 answer
156 views

AMD R6000 CPU - DisplayPort dual-mode feature

In the past I have designed a platform that used an Intel Tiger Lake (Gen 11) CPU and now I have a new project that uses the AMD R6000 series. Different from Intel, the design of the DP++ feature ...
Firas Abd El Gani's user avatar
1 vote
2 answers
478 views

Bare metal coding for newest Intel or AMD processors with I/O access

I am working in the field of real-time simulation for power electronics. The simulator is based on the most recent Intel and AMD processors. The simulation consists in a loop of code executed the ...
Christian's user avatar
2 votes
1 answer
80 views

Bias circuit on memory data lines

simulate this circuit – Schematic created using CircuitLab I have the above in a vintage computer project's schematic, without specification of the transistor or the diode. The Intel 4289 serves ...
andi8086's user avatar
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1 answer
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What type of control unit do Sandy Bridge processors use?

I'm doing a class project about the Intel Pentium G620 processor and I need to know the type of control unit used in Sandy Bridge processors (at least in the Pentium G620). Is it microprogrammed or ...
Caco's user avatar
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9 votes
4 answers
2k views

Upload ASM code on Intel 8086 chip

I have been struggling to find a method to actually run any assembly code on my 8086 chip. I have an 8086 chip and I am trying to implement it on hardware to power up a LED or anything simple. On ...
Mora's user avatar
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1 vote
3 answers
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What is the name of this part in Intel 8086?

Picture is from here. I am pointing to the block inside the BIU that I marked with a red box. There memory address calculation is performed, or conversion from 16-bits into 20-bits. The shape is like ...
AirCraft Lover's user avatar
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1 answer
99 views

Intel 8086 register bus default to high logic with pull-up resistor?

This schematic from righto.com's article on the register of 8086 shows a bi-stable latch with inverters. When the read line is set to high, and the inverter output is also set to high, the bit line ...
BipedalJoe's user avatar
7 votes
0 answers
403 views

x86 Motherboard Bring Up - Intel Tiger Lake UP3 CPU

For those who has experience with Intel x86 motherboard design and bring up. I'm in the middle of motherboard bring-up that has Intel Tiger Lake UP3 CPU. Seems like I had a good run so far at power-up ...
Firas Abd El Gani's user avatar
0 votes
2 answers
615 views

Does Intel/AMD publish the role (purpose) of every SMD (Surface Mounted Cap) that is traced to the die?

Would someone be able to tell me if Intel/AMD publishes a data-sheet (or other documentation) that explains the role (or purpose) of every SMC (Surface Mounted Cap) which connects to the die ? I've ...
David J's user avatar
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1 answer
729 views

Designing baseboard for Intel processor

We are studying the feasibility of designing a minimal board for a high end CPU such as Intel's 8th Gen Core i7/9 alongside some FPGA. We have experience with DDR3/PCIe designs and know about high ...
2i3r's user avatar
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1 answer
256 views

Intel HDA connector - jack detection

Good morning/afternoon/evening I'm trying to resolve an issue related to Jack autodetection on an Intel motherboard In a nutshell, I'm using a home made simple adapter for the HDA connector on the ...
Ashram56's user avatar
-3 votes
2 answers
431 views

Why Intel does not make 5nm chips buying UV machines from ASML? [closed]

I've recently found out (correct me if I'm wrong here), that 5nm lithograthy machines are made by ASML, which is independent and Intel invested in it. I've tried web searches but I still do not ...
Martian2020's user avatar
-1 votes
1 answer
140 views

Intel FPGA input voltage between Vil and Vih : what's happening?

Considering these settings: Cyclone 10 LP (or Cyclone II / Cyclone III / Cyclone IV) IO configured as Input LVTTL 3.3V (Vilmax=0.8V Vihmin=1.7V) Voltage between 0.8V and 1.7V on this input No CLK ...
zian's user avatar
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0 answers
80 views

Why does Intel's CCA (USB3 JTAG control scheme) not let a remote attacker own any system with a flash drive plugged in?

JTAG lets us read / write the architecture states on a CPU core. Intel's CCA let's us connect to JTAG with a USB3 port. So why could an attacker not execute code to trick a flash drive plugged into a ...
J.Todd's user avatar
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-1 votes
2 answers
174 views

What is the most important CPU price factor [closed]

I have two intel CPUS with distinct features. intel i7 8550U intel i5 8300H Which have big performance difference with the cheaper 8300H being higher in memory ...
Abraham's user avatar
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0 answers
147 views

Finding datasheets for 30+ year old ICs?

Anyone who can lead me in the right direction for finding datasheet for some old ICs? I've googled every possible variation of the numbers, which are: MSM93H002-74 (DIP64, marked OKI/Intel), C1185 (...
GarageNSX's user avatar
0 votes
2 answers
367 views

Difference between ARM7 and intel i3, i5 & i7 processors

I am just starting out on a journey to understand microcontroller and microprocessor design. Have read briefly on their differences (ARM7 and Intel i3, i5 & i7). Couldn't find any information on ...
user435715's user avatar
2 votes
0 answers
245 views

I225 Ethernet Controller - SPI Flash

I'm designing a motherboard with Tiger Lake UP3 CPU, and I want to use Intel I225 Ethernet controller for the LAN ports. I225 reference design includes an SPI flash. I couldn't find what is the ...
Firas Abd El Gani's user avatar
6 votes
4 answers
3k views

Why is the 8061 microcontroller described as having 256 bytes of internal memory?

According to doc (http://www.auto-diagnostics.info/pdf/ford_eectch98.pdf), this 8061 microprocessor chip contains 256bytes of internal RAM (also referred to as register file in the doc). However, the ...
Jt90's user avatar
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0 votes
1 answer
281 views

Number of read and write ports on L2 and L3 cache

I have an Intel Core i9-9900K processor (some specs here) and I'm trying to figure out how many read and write ports each level of cache has, for a personal project. I cannot find this in any online ...
Anthony Krivonos's user avatar
-1 votes
2 answers
709 views

When did system-on-chip (SoC) arrive in mainstream laptops? Are intel chipsets used in laptops such as XPS 13, SoCs?

An SoC has multiple functional units like CPU, GPU, sometimes DSPs(Digital Signal Processors), memory and many other units embedded in a single chip. Most intel chipsets used in laptops do have ...
Rishab-Binoy's user avatar
3 votes
2 answers
1k views

How are other chipmakers keeping up with TSMC if their processes are just the best?

In the news recently was Intel's stock falling 20% because its 7nm processes are being delayed by 6+ months. The argument seems to be that Intel is already behind (since they're using 10nm processes ...
Allure's user avatar
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0 votes
2 answers
116 views

Development Board

i gained some experience with ARM and especially with STM32 MCU models.Now i wanted to start learning x86_64 architecture and my initial goal was going towards it. Is there any good development boards ...
Anton Stafeyev's user avatar
-1 votes
1 answer
420 views

What is Symbol Clock Frequency?

I came across the term Symbol Clock Frequency in this Intel programmer reference manual (P131). I could not find what the symbol clock frequency actually is in the manual or online and thought it ...
Zed's user avatar
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0 votes
1 answer
168 views

Why must the VCCA be powered in Cyclone 10 LP even if PLLs are not being used?

The device documentation related to the Cyclone 10 LP FPGA states that "you must power up VCCA even if the PLL is not used". We were comparing the power dissipation of a Microsemi IGLOO2 FPGA with ...
gyuunyuu's user avatar
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0 votes
1 answer
274 views

Connecting a signal to a pin in Quartus

I want to connect a signal in a .v file to a top level pin assigned in the pin planner but I've no idea where to start. I've looked at several guides but as a C programmer this is all quite alien to ...
Joel Whybrow's user avatar
1 vote
1 answer
114 views

Can a micro operation pass multiple pipeline stages with a single clock cycle?

I'm learning a CPU architecture and currently found some high-level description of Intel x86_64 CPUs architecture. By the high level description I mean something like the following micro-op flow (...
Some Name's user avatar
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1 vote
1 answer
490 views

How x86-64 Intel CPU understands how many bytes load into a register

I have the following byte code one the left and and its byte representation on the right: ...
No Name QA's user avatar
1 vote
1 answer
3k views

8051 microcontroller assembly language elevator coding

...
MCS_51's user avatar
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3 votes
1 answer
780 views

Why can't dual port RAM be read out using the Quartus In-System Memory Content Editor?

Here are the screen shots from Quartus; When I want to instantiate the single port RAM, I get option to assign an instance ID and thus read it using the ISMCE (In-System Memory Content Editor). ...
gyuunyuu's user avatar
  • 2,101
2 votes
0 answers
82 views

How do CPU, IOMMU and DMA controller interact with each other?

While drawing an interaction diagram involving CPU, IOMMU and DMA controller, I failed to find any authentic document showing how they interact with each other. Is the DMA controller physically a ...
sherlock's user avatar
  • 219
10 votes
5 answers
4k views

How does an Intel processor "talk" to an I2C device?

I don't come from an Electronics background, so please bear with me. Assume an Intel processor wants to talk to a temperature sensor over the I2C bus. How does the underlying communication look like? ...
sherlock's user avatar
  • 219
0 votes
1 answer
2k views

Difference between USB host & device when connected to the Intel PCH chipset

I know USB 3.0 Host & Device connector port has the same pin count (VBUS, D+/-, TX+/-, RX+/-, GND), but what is the difference between USB host & device when they are connected to the Intel ...
Gintama Duck's user avatar
0 votes
1 answer
188 views

IA 32 architecture segmentation

I was reading the 10th edition of "Operating System Concepts" written by Abraham Silberschatz and many others. It says about IA-32 architecture's segmentation: The IA-32 architecture allows a ...
user avatar
9 votes
3 answers
1k views

"recommended that CLK begin toggling within 150 ms ... to ensure long-term reliability of the device" -- why?

In Intel's Pentium Processor Family Developer Manual, regarding the CPU clock, it says that "it is recommended that CLK begin toggling within 150 ms after VCC reaches its proper operating level. This ...
Zane Kaminski's user avatar
1 vote
2 answers
636 views

Buses and the ALU in the 8086

Intel's 8086 manual shows the following diagram for the CPU's architecture (in page 2-5): If I understand correctly, the ALU's two operands and result are retrieved from / sent to the same 16-bit bus....
obe's user avatar
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0 votes
1 answer
237 views

Where in the instruction pipeline is machine code to microcode translation?

In my computer architecture courses on the N-stage pipeline, I never encountered the concept of microcode. I was surprised, then, when in a performance analysis course assignment, I discovered that ...
Dragonsheep's user avatar
1 vote
0 answers
46 views

Intel FPGA OpenCL work-group scheduling

I have a question about work-group scheduling on multiple CUs in Intel FPGA. As work-groups are assigned to available CUs, when is a CU considered available? Is it when the last work-item of the ...
HastatusXXI's user avatar
39 votes
6 answers
8k views

Why does Intel's Haswell chip allow floating point multiplication to be twice as fast as addition?

I was reading this very interesting question on Stack Overflow: Is integer multiplication really done at the same speed as addition on a modern CPU? One of the comments said: "It's worth nothing ...
Nike Dattani's user avatar
0 votes
1 answer
238 views

Intel FPGA: applying timing constraints

I have a data signal, select and clock signal which I am sending from the FPGA to another chip and I need to constrain them so I don't violate setup/hold time etc. I have tried to write and SDC file, ...
Tom Berge's user avatar
-3 votes
1 answer
412 views

why ARM architecture necessarily dominates the IOT market? [closed]

I would like to understand why do we use ARM for routers, cell phones, cameras, refrigerators, smart tv, and everything. instead of using any other architecture like x86. What are the advantages of ...
BunnyGuy's user avatar