Newest 'intel-fpga' Questions

1

vote

1answer

87 views

How to constrain a source-synchronous FPGA input?

I have a source-synchronous input to my FPGA (an Intel Cyclone 10 GX 10CX085), coming from an external chip whose datasheet gives the following information: fmax = 300 MHz (single data rate) tsetup = ...

asked Dec 27 '21 at 8:18

Harry

1557 bronze badges

0

votes

0answers

21 views

Nios2 - GDB Server Timeout

I am programming an Intel Nios2 softcore processor using VS Code and the available command line tools (Ubuntu Linux 18.04.6, Quartus 18.1). The FPGA is an Intel MAX10 device. Everything works fine ...

intel-fpga gdb nios-ii

asked Dec 23 '21 at 18:10

Sportsfreund80

1

0

votes

1answer

62 views

How effective is the Intel video Frame Buffer core when storing in memory?

The Intel Video and Image Processing (VIP) Suite IP has a Video Frame Buffer (VFB) core, named Frame Buffer II IP Core, that can take streaming images on the Avalon-ST IF and save them into memory ...

intel-fpga video

asked Nov 27 '21 at 8:27

EquipDev

4274 silver badges13 bronze badges

0

votes

1answer

44 views

JTAG Communication Failure in ARRIA 10 FPGA

Has anyone bricked an ARRIA 10 FGPA (or any FPGA) and successfully unbricked it? I have an ARRIA 10 that uses an EPCQ-L256 external memory to configure the FPGA. When I uploaded some code, I think I ...

communication intel-fpga jtag quartus

asked Nov 16 '21 at 0:47

Aaron

12611 bronze badges

2

votes

1answer

73 views

Constraining combinatorial path delays in Intel Cyclone-V FPGA

I am working on a design with a Cyclone-V FPGA. I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother. 4 DFFs running on each of these respective ...

digital-logic fpga intel-fpga timing-analysis sdc

asked Nov 9 '21 at 17:24

cplusruss

552 bronze badges

0

votes

3answers

80 views

Software to program a Cyclone 10 via JTAG with microcontroller?

I've designed a small circuit board with a Cyclone 10 LP FPGA and an EZ-USB FX2LP microcontroller. My current revision has a 10-pin header for connecting a USB Blaster, and it works just fine that ...

microcontroller fpga intel-fpga jtag

asked Oct 21 '21 at 15:02

Andrew

1135 bronze badges

1

vote

0answers

34 views

How to convert from Avalon-MM 128-bit to 48-bit IF?

Some Intel FPGA DDR memory controller only offers 48-bit Avalon-MM IF, when implementing the hard External Memory IF (EMIF) controller. For connection from a 128-bit Avalon-MM IF, it is therefore ...

intel-fpga soc ddr3

asked Oct 3 '21 at 15:05

EquipDev

4274 silver badges13 bronze badges

-4

votes

1answer

93 views

Verilog truth tables [closed]

I am starting in verilog, I am very confused with truth tables, how do I do it in verilog using "if-else", my instructor introduced us to the topic with the following example: after seeing ...

fpga verilog intel-fpga system-verilog max10

asked Sep 29 '21 at 20:55

Rafael Lozano

1

0

votes

1answer

185 views

Quartus cannot place PLL

I am using Intel/Altera Cyclone V 5CSEMA4U23C6 on DE0-nano-SoC board. My design is using one PLL that I added a while ago in Platform Designer. Though it isn't explicitly calling Fractional PLL based ...

intel-fpga quartus

asked Sep 20 '21 at 5:12

Martin Vana

63910 bronze badges

0

votes

1answer

74 views

Is it possible to write an "interconnect" in VHDL by hand?

An interconnect connects one or more masters to one or more slaves in a sort of system on chip design. In such a scenario there would be a master containing a standard bus like Avalon-MM, AMBA AXI, ...

fpga xilinx intel-fpga interconnect microsemi-fpga

asked Aug 5 '21 at 23:39

quantum231

9,27221 gold badges86 silver badges169 bronze badges

-2

votes

1answer

72 views

Implement glDrawArrays function in FPGA [duplicate]

I need to implement glDrawArrays function in FPGA. I understand it's part of the OpenGL library. I'm trying to get to its source code to figure out what it contains. Does anyone know of a tool that ...

fpga intel-fpga vivado vivado-hls

asked Jul 29 '21 at 10:40

ohad

1

-1

votes

1answer

65 views

How to use command-line to cause Qsys to generate only synthesis or only simulation files?

In my project there are several Qsys files. Some of them are for synthesis but most are for testbench. When changes are made to source code, I usually just run generate Qsys system from the GUI and ...

intel-fpga quartus

asked Jul 23 '21 at 0:17

quantum231

9,27221 gold badges86 silver badges169 bronze badges

2

votes

3answers

72 views

How to make Quartus generated programming files for two different but pin compatible FPGAs?

On most porotype boards there is a smaller FPGA which does fit the design but cannot fit a lot of signal tap tap to aid in debugging. Thus, I got a few boards modified with the largest pin compatible ...

intel-fpga quartus

asked Jul 23 '21 at 0:09

quantum231

9,27221 gold badges86 silver badges169 bronze badges

0

votes

0answers

28 views

Manually override Quartus Fitter/Pin Assignment constraints

I have a design that I want to synthesize for / upload to a Max 10 FPGA. One of the inputs goes to a PLL. Quartus now claims, that the neighbouring IO pin is too close to the PLL input pin and won't ...

fpga intel-fpga quartus

asked Jul 15 '21 at 8:53

stebu92

1214 bronze badges

0

votes

2answers

81 views

Unexpected change when reading input signals in a VHDL Finite State Machine

I implemented a FSM in vhdl using two processes; A sync process for state transition ...

vhdl intel-fpga quartus modelsim

asked Jul 4 '21 at 20:11

Ahmed

91 bronze badge

0

votes

1answer

112 views

Is there a reason to have different files or entities with same name in FPGA project?

In FPGA projects, the files are usually named after the entity they contain. I am trying to figure out these things: Is it a good practice to have multiple entities in same file? What if entity and ...

fpga vhdl intel-fpga microsemi-fpga

asked Jun 9 '21 at 11:00

quantum231

9,27221 gold badges86 silver badges169 bronze badges

1

vote

1answer

66 views

Unable to constrain HPS peripheral pins on intel agilex fpga dev kit

I'm having trouble getting the Hard Processor System (HPS, the embedded hard processor of the agilex fpga series) to work properly on the Intel Agilex Dev kit version 3. The issue says that that there ...

intel-fpga constraints

asked Jun 3 '21 at 11:34

Doralitze

112 bronze badges

2

votes

1answer

124 views

What value to use for Byte Count field in PCI Express (PCIe) IO read completion?

In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read. A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this ...

fpga digital-communications intel-fpga pcie pci

asked May 25 '21 at 17:46

EquipDev

4274 silver badges13 bronze badges

0

votes

0answers

33 views

What "portable" NOC architectures exist for use in FPGA designs to be implemented across multiple vendors?

I have used Qsys in Intel Quartus and am aware that it generates an "interconnect fabric" that connects the different peripherals together. The generation of this interconnect is done ...

intel-fpga microsemi-fpga noc

asked May 25 '21 at 13:59

quantum231

9,27221 gold badges86 silver badges169 bronze badges

0

votes

1answer

100 views

Can transceiver replace SPI, I2C and other "normal" methods for high speed data transfer between FPGAs? If so, how? [closed]

SPI, I2C and UART are some well known serial methods for data transfer between devices on the same PCB. However, they all have a data rate bottleneck which is significantly lower than Multi Gigabit ...

fpga intel-fpga transceiver

asked May 18 '21 at 14:28

quantum231

9,27221 gold badges86 silver badges169 bronze badges

0

votes

0answers

52 views

how use text file as input for sinewave and produce sample each clock in tesbench(VHDL)?

so there error is Fatal error in process sinewave_proc at C/..../sin_from_text_tb.vhd at if if not endfile(file_sinewave) I have made a very simple code in vhdl so I can understand how reading a file ...

vhdl intel-fpga modelsim

asked Apr 23 '21 at 7:31

Yaakov

3012 silver badges18 bronze badges

2

votes

2answers

89 views

Maximum rate between ADC-FPGA link for Igloo 2 vs Max 10

An ADC has a source synchronous output interface and is to be interfaced with an FPGA. The ADC can communicate using single ended CMOS, DDR CMOS and DDR LVDS. How do I know what is the fastest rate ...

intel-fpga microsemi-fpga data-rate

asked Apr 20 '21 at 13:42

Quantum0xE7

1,2723 silver badges19 bronze badges

0

votes

1answer

60 views

clkp and clkn inputs in Intel MAX10 FPGAs

The clkp and clkn can be used to insert a differential clock signal into the Intel MAX10 FPGA. Intel MAX10 FPGA Datasheet My question is, can we have 2 separate independent single ended clock signals ...

clock intel-fpga

asked Apr 19 '21 at 10:07

Quantum0xE7

1,2723 silver badges19 bronze badges

0

votes

1answer

143 views

How does Quartus pin planner know about voltage in each I/O bank?

It is possible to specify a range of I/O standard options in Quartus pin planner. I am trying to understand a few things: How does Quartus know what voltage is supplied to each bank? Why does Quartus ...

intel-fpga quartus

asked Apr 13 '21 at 1:39

Quantum0xE7

1,2723 silver badges19 bronze badges

0

votes

1answer

163 views

LCD 16x2 (I2C) with FPGA (Altera Cyclone II)

this is the question, a few days ago I bought the FPGA Cyclone II development board from altera (I am a big fan of arduino and I have a variety of modules and others) at first I started studying ...

fpga i2c lcd intel-fpga

asked Apr 10 '21 at 4:33

last-redman

31 bronze badge

0

votes

1answer

76 views

What is the FPGA with the highest LEs / $?

Well, what is the FPGA with more Logic Elements per Dollar? I already tried to search some sites but the filters for the products do not include that option.

fpga xilinx intel-fpga

asked Apr 8 '21 at 13:24

last-redman

31 bronze badge

-3

votes

1answer

95 views

How to implement neural network using FPGA? [closed]

I want to design neural networks using FPGAs and make neuromorphic chip. Is there a tutorial or course to learn how to do that and to implement neural network using FPGA especially for evaluating the ...

fpga vhdl verilog hardware intel-fpga

asked Mar 31 '21 at 0:47

Coder 13

1

vote

0answers

99 views

Why is my FPGA clock so slow

To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this: <...

fpga verilog intel-fpga hdl

asked Mar 29 '21 at 22:31

Hal

234 bronze badges

0

votes

0answers

740 views

Quartus Prime Lite: Error (209053): Unexpected error in JTAG server -- error code 35 and Error 202940 Can't access JTAG chain with SSH

Today I received a Terasic USB Blaster and I want to program an Altera 10M04SCE144C8G FPGA. I am using the Intel Quartus Prime 20.1.1 Lite Edition installed in Ubuntu 20.04. This FPGA has already been ...

intel-fpga error quartus

asked Mar 25 '21 at 17:22

user171780

4305 silver badges15 bronze badges

0

votes

0answers

38 views

SPI Altera master IP not behaving as expected

Using Platform designer on Quartus, This is a system with Nios and SPI IP. The code on the nios is attached. This code is supposed to drive the MOSI output to 1 forever, the MOSI on the waveform is ...

spi intel-fpga modelsim hal nios-ii

asked Mar 24 '21 at 20:50

Salma El-Sokkary

1

0

votes

1answer

47 views

Pipelined designs with outputs in differentes delay clocks

I have a pipelined design that ends in 13 clock cycles when the input value is not close to zero, but when the input is close to zero, the design only needs about 4 clock cycles, because of all the ...

verilog intel-fpga pipeline

asked Mar 11 '21 at 10:19

Diego Ruiz

155 bronze badges

1

vote

0answers

54 views

Is there a "universal" JTAG controller peripheral?

JTAG can be used to read/write data from/to FPGAs. I want to know if there is any device with an interpreter that can be used with user written STAPL files. Basically the peripheral shall wiggle the ...

debugging intel-fpga jtag microsemi-fpga

asked Mar 3 '21 at 22:03

Quantum0xE7

1,2723 silver badges19 bronze badges

1

vote

2answers

127 views

Altera Quartus detects 2 CPLD devices instead of 1

I try to program a design I made using 5M40ZE64C5N CPLD. The software side was successful and I got a .pof file without any critical warnings or errors. The problem occurs when I try to upload the ...

intel-fpga jtag programmable-logic

asked Feb 26 '21 at 14:02

user3161354

335 bronze badges

0

votes

1answer

74 views

How to transfer blocks of data into FPGA to aid in testing?

How can one transfer data from PC to FPGA and read back result for test purpose where the data must not get corrupted i.e resend if data integrity was lost or use some other error recovery mechanism. ...

debugging intel-fpga testing microsemi-fpga

asked Feb 22 '21 at 20:34

Quantum0xE7

1,2723 silver badges19 bronze badges

0

votes

1answer

70 views

What timing constrains would I need to set for a handshake based clock transfer

I want to transfer a couple of bits between two clocks, so I build a small handshake logic, but my timing analyzer shows me some violations. Setup/hold violations and in addition some rule check ...

fpga intel-fpga timing-analysis

asked Feb 16 '21 at 17:35

Darki

613 bronze badges

-1

votes

1answer

158 views

Help me debug these VHDL errors please

There are just 6 errors now Can't trace errors in this VHDL ...

vhdl debugging intel-fpga quartus

asked Jan 19 '21 at 4:44

STUDENT

13 bronze badges

0

votes

1answer

235 views

Output waveform of TCS3200

I am trying to use TCS3200 color sensor for my project with De0 nano FPGA board. The output of TCS3200 is a square waveform and i am confused how to use that waveform for a particular task. I searched ...

fpga verilog intel-fpga quartus

asked Dec 31 '20 at 10:27

Ayush Sharma

133 bronze badges

1

vote

0answers

137 views

MAX10 Flash and separating NIOS Firmware from FPGA config for remote updates

I'm trying to get to grips with how MAX10 memories work, especially if you want to split firmware and FPGA config into completely separate sections. I have read and reread the MAX memory guide, but I'...

flash intel-fpga max10

asked Dec 22 '20 at 10:32

DiBosco

1,3106 silver badges19 bronze badges

4

votes

2answers

169 views

FPGA - synchronise “very close” clock from signal

This is more of a learning question, I can solve the problem but it would be good to know how to do it - can a clock be reconstructed from a signal, and is it easier when the frequency of the clock is ...

fpga clock intel-fpga video pll

asked Dec 2 '20 at 23:33

Adam Eberbach

2493 silver badges9 bronze badges

0

votes

1answer

453 views

Intel De1-SoC VGA controller in VHDL

I have implemented a VGA controller in VHDL using the timing specifications for a 600x480 monitor as described in the attached photos. The module takes in a 50MHz clock and is supposed to draw a ...

digital-logic vhdl intel-fpga vga

asked Nov 13 '20 at 17:15

Sweet Nemesis

235 bronze badges

0

votes

1answer

176 views

problem in adding IP to platform designer

I'm new to platform designer and I want to add an ALT PLL intel FPGA IP to a platfrom designer project but after opening Mega wizard plugin manager and setting up the requirements, IP does not add to ...

fpga intel-fpga quartus

asked Nov 13 '20 at 13:23

m-sh-shokouhi

1011 bronze badge

1

vote

0answers

180 views

Verilog design to display character using "16x2 Character Display" IP from Quartus IP Library

I was trying to display a single character on 16x2 display. I created simple Verilog design for "Altera Cyclone V Development Kit". In the project I used "16x2 Character Display" ...

verilog lcd intel-fpga

asked Nov 4 '20 at 18:26

dirk

191 bronze badge

2

votes

1answer

240 views

Possible to use Segger J-Link with Intel Quartus to flash FPGA?

Does anybody know if it's possible to use a Segger J-Link with Intel Quartus to flash an FPGA?

flash intel-fpga quartus j-link

asked Oct 27 '20 at 20:46

SofaKng

3592 gold badges4 silver badges11 bronze badges

0

votes

0answers

66 views

How can Quartus Prime System Console be used to read/write a whole file?

I want to find a way to read/write whole file from/to my Intel FPGA design. The file being written provides data to be processed and the file being read shall contain the results of the processing ...

debugging intel-fpga quartus

asked Oct 17 '20 at 12:17

Quantum0xE7

1,2723 silver badges19 bronze badges

0

votes

2answers

80 views

Audio Demos on DE10 Standard not Working

I bought the Terasic DE10 Standard and am having issues trying to run the demos related to audio. I am trying to run the two demos, DE10_Standard_Audio, and DE10_Standard_i2sound, while connecting ...

audio fpga intel-fpga audio-codec

asked Sep 15 '20 at 18:03

Lokwill

856 bronze badges

0

votes

1answer

135 views

How Does One Do Block RAM Inference on Altera Cyclone 10 LP FPGA Boards in Verilog [closed]

I have tried to google for this a lot but I can't seem to find anything.

fpga intel-fpga ram fifo

asked Aug 17 '20 at 19:00

Coder Motor

392 bronze badges

0

votes

3answers

314 views

How to create on-board USB blaster for Intel FPGAs?

Intel/Altera FPGA development boards only require a USB cable to configure the FPGAs. There is no need to buy a byte blaster. How is the USB blaster implemented on these boards, is this method/design ...

intel-fpga

asked Aug 6 '20 at 20:54

Quantum0xE7

1,2723 silver badges19 bronze badges

2

votes

3answers

194 views

Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...

fpga xilinx intel-fpga asic actel

asked Aug 6 '20 at 14:09

Electronic_Nerd

3123 silver badges9 bronze badges

0

votes

1answer

79 views

Generating error condition randomly inside a digital design inside FPGA

In order to aid in testing of the design, it is required that we put it into a "debug mode" whereby specific type of error conditions will occur at random intervals. We must then monitor the ...

fpga vhdl intel-fpga random-number

asked Jun 16 '20 at 21:27

Quantum0xE7

1,2723 silver badges19 bronze badges

2

votes

1answer

197 views

How do you select pin functions on an EPM7128 CPLD?

I have some old Altera MAX EPM7128SLC84-15N CPLDs kicking around that I want to use to interface with 5v TTL logic. If you look at the pinout, some of the pins have more than one function (eg. Pin 2 ...

intel-fpga programmable-logic quartus

asked May 24 '20 at 16:03

santonel

232 bronze badges

Questions tagged [intel-fpga]

Related Tags