Newest 'intel-fpga' Questions

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RTL Simulation Error, Can't Launch ModelSim

I am new on FPGAs so I am using the Altera Cyclone II EP2C5T144 The Quartus Prime version that supports Cyclone II is 13.0 ; I am trying to run a very simple code to turn on a LED ...

asked Oct 10 at 7:41

Delfin

13413 bronze badges

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9 views

Can the altera_virtual_jtag be used to store critical design information for read out?

Can critical design information like design version number, compilation date e.t.c be stored inside the FPGA and be read out via JTAG while using the altera_virtual_jtag? I assume that the ...

intel-fpga debugging jtag

asked Oct 8 at 21:33

quantum231

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16 views

How to initialize/load Intel HBM memory in simulation

I am trying to simulate the Intel HBM example design using ModelSim. Is there a way to initialize/load the HBM memory with some data before the simulation? If so, how can we do it?

intel-fpga quartus

asked Oct 8 at 14:52

Shreyas Kolala Venkataramanaia

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2answers

39 views

dual purpose pins on max 10 fpga

I am breaking into the world of FPGA development at my internship for an aerospace company. I keep coming across the term "Dual-Purpose Pin" in the documentation for the Max 10 family of FPGA devices. ...

fpga intel-fpga max10

asked Sep 25 at 20:48

Hannah Did

62 bronze badges

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8 views

EP53F8QI Short to GND fault

We have a design with an EP53F8QI that multiple ICs have been burned both at room temperature and +80 °.C. We are using it to create a +3.3V and on fault we have found that the +3.3V supply is shorted ...

power-supply pcb-design voltage-regulator intel-fpga switching-regulator

asked Sep 12 at 11:58

shmueld

62 bronze badges

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3answers

50 views

Measuring the external memory power consumption in FPGAs?

I am trying to get a power/energy breakdown of DDR3 and core logic. I used Quartus power analyzer tool to get the power estimates, but I am not sure whether it includes the power consumption of ...

power fpga intel-fpga quartus

asked Sep 2 at 18:27

Shreyas Kv

31 bronze badge

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1answer

33 views

Is it possible to add an existing IP variant to a Platform Designer/Qsys system through TCL?

I have a .ip file that contains a parameterized component which I'd like to use in my Qsys system. I can add the component via the GUI but I would like to be able to add it via TCL or another ...

intel-fpga quartus

asked Aug 21 at 15:49

PlasticGlass

83 bronze badges

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42 views

Altera Cyclone IV Setting Impedance

I'm trying to learn how to implement a 3V LVTTL interface using a Cyclone IV E (EP4CE10) FPGA. However, I would like to ensure that the input/output impedances of the IO is at 50R. I see that it is ...

fpga impedance intel-fpga io

asked Aug 13 at 13:13

Arnold Hucks

132 bronze badges

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62 views

VHDL: case when using constants constructs

I'm having some trouble with the following statement ...

fpga vhdl intel-fpga programmable-logic quartus

asked Aug 4 at 21:13

diegogmx

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51 views

Register value is not updated inside always @ loop

I am relatively new to verilog, please help with this issue I am having. Attached is a snippet of the code I am working on. The issue I am facing is, the regs - del1 and del2 are not correctly ...

verilog intel-fpga

asked Jul 31 at 18:22

Am1T

32 bronze badges

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1answer

41 views

What is purpose of exporting system using tcl scripts generated by Qsys?

To "Export" a Qsys system we merely need the .qsys file. Inside Qsys (now called Platform Designer) we have the option where we can export the system as a .tcl script. The options are the in the file ...

intel-fpga

asked Jul 30 at 6:47

Quantum0xE7

546 bronze badges

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34 views

Is it possible to create a Qsys system with VHDL generics at its top level?

Some components in my Qsys system have test modes. These are controlled via generics on their top level. These components are currently in a Qsys system. In Qsys, I can click on them and change the ...

vhdl intel-fpga

asked Jul 29 at 13:08

Quantum0xE7

546 bronze badges

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1answer

26 views

What is the difference between words and symbols in Qsys, how to know which one to use?

Qsys offers options to select address unit or address type. All I know is that my custom components shall write 32 or 64 bit data to a specific address and it is not byte addressable. How do I decide ...

intel-fpga

asked Jul 25 at 8:42

Quantum0xE7

546 bronze badges

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1answer

36 views

Verifying custom Qsys component?

A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also. These copies ...

vhdl intel-fpga verification

asked Jul 23 at 15:13

Quantum0xE7

546 bronze badges

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1answer

71 views

Verilog 'if' statement error

Why are LEDs on after executing this? LEDs on pattern is 1010: ...

fpga verilog intel-fpga if

asked Jul 17 at 20:31

misha

31 bronze badge

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1answer

72 views

Intel FPGA equivalents of Xilinx IBUFDS Primitives?

Im trying to migrate an Design from using Xilinx primitives to Intel Altera FPGA. The original design uses the IBUFDS for the clock signals. ...

fpga xilinx intel-fpga buffer

asked Jun 19 at 9:50

Bá Anh Đào

31 bronze badge

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2answers

37 views

How can Qsys component configuration be accessed in software?

I'm designing a Qsys component which I want to be user-configurable. It has config parameters which are defined in the TCL file. For example, for a GPIO bank component I would write: ...

c intel-fpga quartus soc

asked Jun 16 at 10:31

Dmitry Grigoryev

19.8k2 gold badges31 silver badges79 bronze badges

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2answers

96 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...

fpga intel-fpga pll quartus

asked Jun 11 at 8:03

Olupo

337 bronze badges

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1answer

52 views

LMS7002M: I & Q DATA formats from LIMESDR

Can any one tell me what is the data format of LMS7002m I & Q sample? Are they unsigned int or floating or double? how are they ? Also kindly anyone show me any hint of proof for their answer.... ...

intel-fpga sdr

asked Jun 4 at 18:48

ARKARUP7304

11 bronze badge

0

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1answer

76 views

altera FPGA acting like OR gate when programed as AND gate

I'm new to altera fpga , I've bought development board based on EP4CE6E22 cyclon IV and tryed to program it with basic program in quartus environment ...

fpga intel-fpga quartus

asked Jun 1 at 10:00

Ron Vaisman

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1answer

857 views

what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and ...

fpga vhdl intel-fpga virtex-series-fpga microsemi-fpga

asked May 31 at 6:10

srihari

312 bronze badges

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0answers

41 views

Custom PCIe DMA on Cyclone 10GX FPGA burst read stucks

I'm writing a custom DMA machine to read and write data to the host system from FPGA memory. I use the Altera PCIe IP core as end point device in Avalon-MM mode. BAR0 is set as 64bit bar, Avalon-MM ...

intel-fpga linux pcie dma

asked Mar 28 at 16:18

mishaskt

12 bronze badges

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0answers

25 views

In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...

intel-fpga timing-analysis quartus

asked Mar 27 at 19:43

shparekh

1378 bronze badges

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1answer

37 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...

fpga verilog intel-fpga register synthesis

asked Feb 17 at 20:34

axk

4254 silver badges16 bronze badges

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2answers

63 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...

fpga xilinx intel-fpga timing-analysis

asked Feb 17 at 18:04

Sourabh Tapas

13410 bronze badges

1

vote

1answer

212 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...

fpga vhdl spi intel-fpga quartus

asked Feb 6 at 13:26

SDwarfs

4782 silver badges9 bronze badges

1

vote

1answer

97 views

How can I check if an IO pin is dead?

I've been playing around with I2C for a couple days now with a DE10-Nano dev board: I'm implementing an I2C master in CLaSH so that I can talk to the HDMI encoder chip, but for now I'm talking to an ...

fpga gpio pins intel-fpga

asked Feb 6 at 8:59

Cactus

1952 silver badges9 bronze badges

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29 views

Why does functional simulation generate Zs?

I have a very simple project, I share the files in this github repo If I run a functional simulation (Waveform.vwf in the repository) I get some 'Z' in the value of an internal register, see the ...

simulation intel-fpga quartus

asked Feb 5 at 10:57

Fabio Dalla Libera

1339 bronze badges

0

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1answer

95 views

What's wrong with this schematic for powering up Cyclone IV FPGA?

I have followed all the guide lines for powering up the Cyclone IV. However, the 3.3v Regulator is heating too much and also the Cyclone IV FPGA. What's wrong with my schematic? Is there a problem in ...

fpga intel-fpga cyclone

asked Jan 16 at 14:00

Alpha0

82 bronze badges

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votes

1answer

33 views

Altera FlipFlop stuck at GND

I'm trying to make a counter that counts: 0,1,2,3,4,5 I need this for a frequency divider of 6 So I made this table: From this I get: J0= 1 K0= 1 J1 = NOT Q0 AND Q1 K1 = Q1 J2 = Q1 AND Q2 K2 =...

simulation flipflop counter intel-fpga

asked Dec 31 '18 at 20:13

Fox Alex

51 bronze badge

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0answers

45 views

Identify valid FPGA configuration image in serial flash device?

How can I know if there's valid FPGA configuration image in the specific location of the serial configuration device before I perform reconfiguration and experience successful or faulty attempt? ...

intel-fpga cyclone

asked Dec 25 '18 at 10:27

Anonymous

5,4371 gold badge8 silver badges32 bronze badges

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0answers

83 views

can't send characters using fpga cyclone iv

I'm trying to connect my FPGA Cylone IV (CoreEP4CE6) with Raspberry Pi 3 for communication through UART. The process (uart_rx) for receiving data is working fine, however, when I place another process ...

fpga uart intel-fpga

asked Dec 20 '18 at 18:54

Alpha0

82 bronze badges

1

vote

1answer

280 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...

fpga intel-fpga quartus intel max10

asked Dec 18 '18 at 19:42

quantum231

4,11115 gold badges66 silver badges131 bronze badges

1

vote

2answers

379 views

Altera has created EPCS and EPCQ devices, can only these be used to store FPGA configuration data?

FPGA configuration data must be stored in external non-volatile memory. Can we use just any flash memory or only specific types? What about EEPROMs or any other nonvolatile memory device? Edit: I am ...

fpga intel-fpga configuration intel

asked Dec 16 '18 at 17:18

quantum231

4,11115 gold badges66 silver badges131 bronze badges

1

vote

2answers

290 views

Program FPGA using STM32

I am interested in using an STM32 to flash an sof or pof file onto a Cyclone IV FPGA. The sof/pof will be stored in SPI flash memory, and the plan is to use the STM32 as a programmer. I haven't been ...

fpga stm32 intel-fpga

asked Dec 5 '18 at 23:20

jgaro

971 silver badge7 bronze badges

0

votes

1answer

67 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...

fpga vhdl verilog xilinx intel-fpga

asked Dec 1 '18 at 15:54

Sourabh Tapas

13410 bronze badges

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1answer

83 views

Get more AS-attached flash chip information from ALTASMI

I am playing with the attaching various configuration flash devices to the Altera Cyclone 3. In particular, I want to replace EPCS16 (2MB) with W25Q128 (16MB) - for both size and cost reasons. Is ...

flash intel-fpga quartus configuration

asked Nov 28 '18 at 7:05

Anonymous

5,4371 gold badge8 silver badges32 bronze badges

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1answer

394 views

Word alignment / bitslip in LVDS Receiver

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...

intel-fpga lvds

asked Nov 15 '18 at 9:25

SMS

83 bronze badges

0

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1answer

239 views

How to compare a re-writable 4 bit value to a given 4 bit input in Verilog?

The goal of this project to design a computational lock alarm in Verilog to be run on an Altera board (note on the board 0 is actually ON and 1 is OFF). Based on the design criteria I created a state ...

verilog intel-fpga hdl

asked Nov 11 '18 at 23:31

Akila Kavisinghe

1

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1answer

46 views

Is it possible to power down all the PLLs and VCO of a MAX 10 Device?

We are developing a board in which we would like not to use the analog features, like PLL, VCO and ADCs of a MAX10. UG-M10CLKPLL par. 2.3.6 states : "The only time that the VCO is completely disabled ...

intel-fpga pll vco max10

asked Oct 31 '18 at 13:57

MRigh

1

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0answers

48 views

Two-Terminal Passive Analog Component Tester Using the DE1-SoC Development Board

I am having hard time understanding this problem. I have to draw a Level 1 block diagram for this system. I really appreciated it if somebody can help me. I am new to DE1-Soc. use the Intel DE1-SoC ...

microcontroller embedded intel-fpga intel

asked Oct 28 '18 at 19:19

dhruv

133 bronze badges

0

votes

1answer

80 views

How to have an in-system check in an FPGA based system that it has been reset?

I have a system based on Altera's MAX10 device that is doing the following tasks: receives the data and stores it on an on-chip flash memory only once. reads all the data from on-chip flash, stores ...

vhdl verilog intel-fpga hdl programmable-logic

asked Oct 19 '18 at 10:56

SMS

83 bronze badges

1

vote

1answer

364 views

I2S output in VHDL

I am making an I2S output in VHDL for a project. This is my first project using VHDL and the problem may be my basic VHDL understanding. This is my code: ...

vhdl intel-fpga i2s

asked Oct 8 '18 at 17:49

keffe

1291 silver badge10 bronze badges

3

votes

1answer

361 views

Altera Cyclone II Quartus II JTAG Programming Error

I'm trying to program a Cyclone II I bought here using Quartus II 13.0sp1 on Arch Linux. I'm trying to program it with a very simple Verilog program with three inputs and two outputs and a few simple ...

fpga intel-fpga jtag quartus cyclone

asked Oct 5 '18 at 4:07

Chris Loonam

1469 bronze badges

2

votes

1answer

677 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...

fpga intel-fpga timing-analysis quartus sdc

asked Oct 1 '18 at 14:29

fhw72

1112 bronze badges

0

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1answer

150 views

Altera Cyclone IV clock-to-output delay

Trying to find what is the clock-to-output delay for registers inside EP4CE6E22C6. Have looked through the 3 Cyclone IV handbooks searching by delay but have not found any values specified. All the ...

flipflop delay intel-fpga

asked Sep 23 '18 at 15:11

axk

4254 silver badges16 bronze badges

1

vote

1answer

322 views

Altera Cyclone IV PLL: What limits the available multiplication/division factor values

Altera Cyclone IV EP4CE6E22 with a 50 MHz input clock. I want to get 24 MHz out of the ALTPLL megafunction. The requested multiplication/division settings are 12/25 but actual settings turn out to be ...

intel-fpga pll

asked Sep 13 '18 at 21:05

axk

4254 silver badges16 bronze badges

0

votes

1answer

130 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...

fpga verilog intel-fpga pll cyclone

asked Aug 29 '18 at 2:21

thebionicandroid

83 bronze badges

0

votes

1answer

119 views

Intel max 10 dimensions - datasheet & BSDL mismatch

TL;DR: The BSD file from Intel doesn't match the datasheet. What are the right dimensions? BSD: https://www.intel.com/content/dam/altera-www/global/en_US/others/support/devices/bsdl/10M02SCM153.bsd ...

eagle intel-fpga packages dimensions max10

asked Aug 28 '18 at 6:41

Eggi

8510 bronze badges

1

vote

1answer

212 views

Quartus II selected a signal as a clock in combinational circuit

...

vhdl clock intel-fpga quartus

asked Aug 26 '18 at 13:34

Hassan Ibrahim

204 bronze badges

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