Newest 'intel-fpga' Questions

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Variable Bit shift within 1 Clock Cycle (Verilog)

I have a 64-bit register that I would like to right shift n times, with 0<=n<=64, implemented as such always_ff data[63:0] <= (data >> n); I ...

asked yesterday

Rudy Montoya

112 bronze badges

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43 views

How can i export synthesized netlist from Quartus 2?

I need to get a netlist that creates by synthesis and optimization from different hdl languages in Quartus 2. I need a netlist in basic logic. Rtl viewer shows me something similar, but i need it in ...

vhdl intel-fpga quartus

asked Jan 6 at 14:29

Timofey Bolgarin

112 bronze badges

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Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...

fpga verilog intel-fpga quartus

asked Dec 14 '19 at 23:26

user3818491

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1answer

112 views

UART not fast enough for debug purpose, what alternatives exist?

This problem is related with debugging an FPGA design implemented in Intel/Altera FPGA. A custom debug mechanism has been introduced into the design. This new part of the design writes into a FIFO ...

uart intel-fpga debugging jtag

asked Dec 5 '19 at 19:44

quantum231

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50 views

PIN Placement Errors In Quartus

So I am writing a simple blinking LED Verilog code that will be run on a Cyclone10 LP (Device is called 10CL025YU256I7G) and will be tested on a Cyclone 10 Evaluation Kit (6XX-44504R-0D) All code is ...

fpga verilog intel-fpga pinout quartus

asked Nov 27 '19 at 18:31

Coder Motor

111 bronze badge

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1answer

40 views

Setting Pin Assignments For Quartus

So I have written a simple Verilog module which works well in the ModelSim emulator. I would like to now program my Cyclone 10 Dev board to perform this simple task, but I need to set up the pin ...

fpga pins intel-fpga quartus

asked Nov 26 '19 at 21:47

Coder Motor

111 bronze badge

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1answer

100 views

Raw programming of an Altera FPGA

I have an Altera Cyclone IV FPGA (for ie) and my question is: is it possible a raw programming of the FPGA? Is it possible to set "manually" the gates for making experiments? Thank you

digital-logic fpga programming intel-fpga

asked Oct 21 '19 at 10:19

rikicecchi

111 bronze badge

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12 views

Can the altera_virtual_jtag be used to store critical design information for read out?

Can critical design information like design version number, compilation date e.t.c be stored inside the FPGA and be read out via JTAG while using the altera_virtual_jtag? I assume that the ...

intel-fpga debugging jtag

asked Oct 8 '19 at 21:33

quantum231

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25 views

How to initialize/load Intel HBM memory in simulation

I am trying to simulate the Intel HBM example design using ModelSim. Is there a way to initialize/load the HBM memory with some data before the simulation? If so, how can we do it?

intel-fpga quartus

asked Oct 8 '19 at 14:52

Shreyas Kolala Venkataramanaia

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2answers

56 views

dual purpose pins on max 10 fpga

I am breaking into the world of FPGA development at my internship for an aerospace company. I keep coming across the term "Dual-Purpose Pin" in the documentation for the Max 10 family of FPGA devices. ...

fpga intel-fpga max10

asked Sep 25 '19 at 20:48

Hannah Did

112 bronze badges

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16 views

EP53F8QI Short to GND fault

We have a design with an EP53F8QI that multiple ICs have been burned both at room temperature and +80 °.C. We are using it to create a +3.3V and on fault we have found that the +3.3V supply is shorted ...

power-supply pcb-design voltage-regulator intel-fpga switching-regulator

asked Sep 12 '19 at 11:58

shmueld

363 bronze badges

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3answers

50 views

Measuring the external memory power consumption in FPGAs?

I am trying to get a power/energy breakdown of DDR3 and core logic. I used Quartus power analyzer tool to get the power estimates, but I am not sure whether it includes the power consumption of ...

power fpga intel-fpga quartus

asked Sep 2 '19 at 18:27

Shreyas Kv

31 bronze badge

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1answer

77 views

Is it possible to add an existing IP variant to a Platform Designer/Qsys system through TCL?

I have a .ip file that contains a parameterized component which I'd like to use in my Qsys system. I can add the component via the GUI but I would like to be able to add it via TCL or another ...

intel-fpga quartus

asked Aug 21 '19 at 15:49

PlasticGlass

133 bronze badges

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43 views

Altera Cyclone IV Setting Impedance

I'm trying to learn how to implement a 3V LVTTL interface using a Cyclone IV E (EP4CE10) FPGA. However, I would like to ensure that the input/output impedances of the IO is at 50R. I see that it is ...

fpga impedance intel-fpga io

asked Aug 13 '19 at 13:13

Arnold Hucks

232 bronze badges

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1answer

64 views

VHDL: case when using constants constructs

I'm having some trouble with the following statement ...

fpga vhdl intel-fpga programmable-logic quartus

asked Aug 4 '19 at 21:13

diegogmx

3351 silver badge8 bronze badges

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1answer

55 views

Register value is not updated inside always @ loop

I am relatively new to verilog, please help with this issue I am having. Attached is a snippet of the code I am working on. The issue I am facing is, the regs - del1 and del2 are not correctly ...

verilog intel-fpga

asked Jul 31 '19 at 18:22

Am1T

32 bronze badges

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1answer

62 views

What is purpose of exporting system using tcl scripts generated by Qsys?

To "Export" a Qsys system we merely need the .qsys file. Inside Qsys (now called Platform Designer) we have the option where we can export the system as a .tcl script. The options are the in the file ...

intel-fpga

asked Jul 30 '19 at 6:47

Quantum0xE7

1217 bronze badges

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42 views

Is it possible to create a Qsys system with VHDL generics at its top level?

Some components in my Qsys system have test modes. These are controlled via generics on their top level. These components are currently in a Qsys system. In Qsys, I can click on them and change the ...

vhdl intel-fpga

asked Jul 29 '19 at 13:08

Quantum0xE7

1217 bronze badges

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1answer

81 views

What is the difference between words and symbols in Qsys, how to know which one to use?

Qsys offers options to select address unit or address type. All I know is that my custom components shall write 32 or 64 bit data to a specific address and it is not byte addressable. How do I decide ...

intel-fpga

asked Jul 25 '19 at 8:42

Quantum0xE7

1217 bronze badges

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1answer

46 views

Verifying custom Qsys component?

A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also. These copies ...

vhdl intel-fpga verification

asked Jul 23 '19 at 15:13

Quantum0xE7

1217 bronze badges

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1answer

72 views

Verilog 'if' statement error

Why are LEDs on after executing this? LEDs on pattern is 1010: ...

fpga verilog intel-fpga if

asked Jul 17 '19 at 20:31

misha

31 bronze badge

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1answer

110 views

Intel FPGA equivalents of Xilinx IBUFDS Primitives?

Im trying to migrate an Design from using Xilinx primitives to Intel Altera FPGA. The original design uses the IBUFDS for the clock signals. ...

fpga xilinx intel-fpga buffer

asked Jun 19 '19 at 9:50

Bá Anh Đào

31 bronze badge

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2answers

44 views

How can Qsys component configuration be accessed in software?

I'm designing a Qsys component which I want to be user-configurable. It has config parameters which are defined in the TCL file. For example, for a GPIO bank component I would write: ...

c intel-fpga quartus soc

asked Jun 16 '19 at 10:31

Dmitry Grigoryev

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2answers

101 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...

fpga intel-fpga pll quartus

asked Jun 11 '19 at 8:03

Olupo

387 bronze badges

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1answer

100 views

LMS7002M: I & Q DATA formats from LIMESDR

Can any one tell me what is the data format of LMS7002m I & Q sample? Are they unsigned int or floating or double? how are they ? Also kindly anyone show me any hint of proof for their answer.... ...

intel-fpga sdr

asked Jun 4 '19 at 18:48

ARKARUP7304

11 bronze badge

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1answer

84 views

altera FPGA acting like OR gate when programed as AND gate

I'm new to altera fpga , I've bought development board based on EP4CE6E22 cyclon IV and tryed to program it with basic program in quartus environment ...

fpga intel-fpga quartus

asked Jun 1 '19 at 10:00

Ron Vaisman

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1answer

870 views

what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and ...

fpga vhdl intel-fpga virtex-series-fpga microsemi-fpga

asked May 31 '19 at 6:10

srihari

612 bronze badges

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49 views

Custom PCIe DMA on Cyclone 10GX FPGA burst read stucks

I'm writing a custom DMA machine to read and write data to the host system from FPGA memory. I use the Altera PCIe IP core as end point device in Avalon-MM mode. BAR0 is set as 64bit bar, Avalon-MM ...

intel-fpga linux pcie dma

asked Mar 28 '19 at 16:18

mishaskt

12 bronze badges

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0answers

31 views

In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...

intel-fpga timing-analysis quartus

asked Mar 27 '19 at 19:43

shparekh

1478 bronze badges

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1answer

40 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...

fpga verilog intel-fpga register synthesis

asked Feb 17 '19 at 20:34

axk

7055 silver badges16 bronze badges

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2answers

86 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...

fpga xilinx intel-fpga timing-analysis

asked Feb 17 '19 at 18:04

Sourabh Tapas

16410 bronze badges

1

vote

1answer

278 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...

fpga vhdl spi intel-fpga quartus

asked Feb 6 '19 at 13:26

SDwarfs

5582 silver badges9 bronze badges

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1answer

106 views

How can I check if an IO pin is dead?

I've been playing around with I2C for a couple days now with a DE10-Nano dev board: I'm implementing an I2C master in CLaSH so that I can talk to the HDMI encoder chip, but for now I'm talking to an ...

fpga gpio pins intel-fpga

asked Feb 6 '19 at 8:59

Cactus

2853 silver badges9 bronze badges

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123 views

What's wrong with this schematic for powering up Cyclone IV FPGA?

I have followed all the guide lines for powering up the Cyclone IV. However, the 3.3v Regulator is heating too much and also the Cyclone IV FPGA. What's wrong with my schematic? Is there a problem in ...

fpga intel-fpga cyclone

asked Jan 16 '19 at 14:00

Alpha0

132 bronze badges

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1answer

36 views

Altera FlipFlop stuck at GND

I'm trying to make a counter that counts: 0,1,2,3,4,5 I need this for a frequency divider of 6 So I made this table: From this I get: J0= 1 K0= 1 J1 = NOT Q0 AND Q1 K1 = Q1 J2 = Q1 AND Q2 K2 =...

simulation flipflop counter intel-fpga

asked Dec 31 '18 at 20:13

Fox Alex

51 bronze badge

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47 views

Identify valid FPGA configuration image in serial flash device?

How can I know if there's valid FPGA configuration image in the specific location of the serial configuration device before I perform reconfiguration and experience successful or faulty attempt? ...

intel-fpga cyclone

asked Dec 25 '18 at 10:27

Anonymous

5,9521 gold badge9 silver badges33 bronze badges

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95 views

can't send characters using fpga cyclone iv

I'm trying to connect my FPGA Cylone IV (CoreEP4CE6) with Raspberry Pi 3 for communication through UART. The process (uart_rx) for receiving data is working fine, however, when I place another process ...

fpga uart intel-fpga

asked Dec 20 '18 at 18:54

Alpha0

132 bronze badges

1

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1answer

341 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...

fpga intel-fpga quartus intel max10

asked Dec 18 '18 at 19:42

quantum231

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2answers

513 views

Altera has created EPCS and EPCQ devices, can only these be used to store FPGA configuration data?

FPGA configuration data must be stored in external non-volatile memory. Can we use just any flash memory or only specific types? What about EEPROMs or any other nonvolatile memory device? Edit: I am ...

fpga intel-fpga configuration intel

asked Dec 16 '18 at 17:18

quantum231

8,00917 gold badges67 silver badges141 bronze badges

1

vote

2answers

379 views

Program FPGA using STM32

I am interested in using an STM32 to flash an sof or pof file onto a Cyclone IV FPGA. The sof/pof will be stored in SPI flash memory, and the plan is to use the STM32 as a programmer. I haven't been ...

fpga stm32 intel-fpga

asked Dec 5 '18 at 23:20

jgaro

1971 silver badge7 bronze badges

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1answer

70 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...

fpga vhdl verilog xilinx intel-fpga

asked Dec 1 '18 at 15:54

Sourabh Tapas

16410 bronze badges

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1answer

96 views

Get more AS-attached flash chip information from ALTASMI

I am playing with the attaching various configuration flash devices to the Altera Cyclone 3. In particular, I want to replace EPCS16 (2MB) with W25Q128 (16MB) - for both size and cost reasons. Is ...

flash intel-fpga quartus configuration

asked Nov 28 '18 at 7:05

Anonymous

5,9521 gold badge9 silver badges33 bronze badges

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1answer

571 views

Word alignment / bitslip in LVDS Receiver

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...

intel-fpga lvds

asked Nov 15 '18 at 9:25

SMS

133 bronze badges

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1answer

427 views

How to compare a re-writable 4 bit value to a given 4 bit input in Verilog?

The goal of this project to design a computational lock alarm in Verilog to be run on an Altera board (note on the board 0 is actually ON and 1 is OFF). Based on the design criteria I created a state ...

verilog intel-fpga hdl

asked Nov 11 '18 at 23:31

Akila Kavisinghe

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1answer

56 views

Is it possible to power down all the PLLs and VCO of a MAX 10 Device?

We are developing a board in which we would like not to use the analog features, like PLL, VCO and ADCs of a MAX10. UG-M10CLKPLL par. 2.3.6 states : "The only time that the VCO is completely disabled ...

intel-fpga pll vco max10

asked Oct 31 '18 at 13:57

MRigh

1

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0answers

50 views

Two-Terminal Passive Analog Component Tester Using the DE1-SoC Development Board

I am having hard time understanding this problem. I have to draw a Level 1 block diagram for this system. I really appreciated it if somebody can help me. I am new to DE1-Soc. use the Intel DE1-SoC ...

microcontroller embedded intel-fpga intel

asked Oct 28 '18 at 19:19

dhruv

233 bronze badges

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1answer

81 views

How to have an in-system check in an FPGA based system that it has been reset?

I have a system based on Altera's MAX10 device that is doing the following tasks: receives the data and stores it on an on-chip flash memory only once. reads all the data from on-chip flash, stores ...

vhdl verilog intel-fpga hdl programmable-logic

asked Oct 19 '18 at 10:56

SMS

133 bronze badges

1

vote

1answer

402 views

I2S output in VHDL

I am making an I2S output in VHDL for a project. This is my first project using VHDL and the problem may be my basic VHDL understanding. This is my code: ...

vhdl intel-fpga i2s

asked Oct 8 '18 at 17:49

keffe

1891 silver badge10 bronze badges

3

votes

1answer

426 views

Altera Cyclone II Quartus II JTAG Programming Error

I'm trying to program a Cyclone II I bought here using Quartus II 13.0sp1 on Arch Linux. I'm trying to program it with a very simple Verilog program with three inputs and two outputs and a few simple ...

fpga intel-fpga jtag quartus cyclone

asked Oct 5 '18 at 4:07

Chris Loonam

1619 bronze badges

2

votes

1answer

1k views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...

fpga intel-fpga timing-analysis quartus sdc

asked Oct 1 '18 at 14:29

fhw72

1213 bronze badges

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