Questions tagged [intel-fpga]
A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).
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Unable to write to MT25QU256 from Arria 10 SOM
I am using module Arria 10 SOM by iWave with IC Flash MT25QU256. I am trying to read and write from NIOS II processor to different sectors of this flash.
Currently, I'm using the IP Core Generic Quad ...
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How to obtain the counting of TTL pulses from an FPGA?
I'm currently working on a project in which I need to program an FPGA in order to connect it to a photon detector, that generates a TTL pulse when detecting a photon; I need to count this pulses, ...
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Storing Data and Instructions in Memory
I have implemented a RiscV32 single cycle processor using Verilog. Now I am trying to upload it to a FPGA (DE2 - 115 board) and check the functioning. But how do I store instructions and data in the ...
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Intel DCFIFO IP crashing when using a clock with decimal place
I need to build a FIFO with a 96 MHz write clock and a 25.175 MHz read clock.
The data are read from an SDRAM and are fed into the VGA output.
To do that I use the intel DCFIFO IP and PLL IP. The PLL ...
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Error while trying to bind SystemVerilog module with properties module
I have a SystemVerilog module that I want to test using assertions. For simplicity let's say the DUT is this:
...
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SDRAM Voltage and pin planner consequences
I have this SDRAM module:
According to the docs: am I right that it's the 3,3V version?
If yes: what are the consequences of that fact using the Pin Planner?
Is it correct that I have to set the I/O ...
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Cyclone III FPGA 16x2 LCD repeat one character instead of displaying complete word
So I am trying to use the LCD on the cyclone III FPGA.
I have written this verilog code that should display numbers 0 to 9 then letters A to G
Compiling the code has no errors at all
However, when ...
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How to write to EPCS memory without disrupting code execution for DE0-Nano board?
Currently I'm writing my program on DE0-Nano board, which contains an EPCS64 flash memory. My purpose is to save some information of the previous execution of the program, and I have an idea to write ...
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Debuging verilog SDRAM controller
I've been working on a project that involves the creation of a SDRAM Controller in verilog for an Altera DE2 prototyping board. Despite reading the documentation for the memory chip on the board, ...
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Difficulty in understanding the USB interfacing for Altera DE 2
So I am planning to establish connection between my mouse and the USB Host port of the Altera DE-2 board. As per the documentation the Altera DE-2 board uses the Philips ISP1362 chip which follows the ...
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How to generate 3 pulses of varying lengths with an FPGA and Verilog?
I am trying to generate 3 pulses of 2 different lengths at specific times using an Arduino MKR Vidor 4000 which has an Intel Cyclone 10 on board.
I need to generate one pulse with 5 µs length followed ...
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Problem in programming ALTERA MAX 7000S CPLD with homemade Byte Blaster
I am trying to read back an ALTERA MAX 7000S CPLD (EPM7064SLC84-10) mounted on a board (a part of the board's schematic is shown below) and copy it on another CPLD.
In the schematic, X4 is a male 10 ...
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Getting the warning WARNING:Xst:1710 and WARNING:Xst:1895 while running my top module
My aim is to find the pulse width of an unknown incoming signal. To that I have written the following synthesizable verilog code but I am getting the warning XST 1710 and XST 1895. When I try to ...
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The routing delay is 0 ns in quartus chipplanner
I designed a program about TDC. However, I found the routing delay is 0 ns when I check its timming by Timequest. Shown below, the Tco is 0.073 ns, but the routing delay is 0 ns.
Obviously, there is ...
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FPGA to SDRAM communication
I am working with a DE0-nano board, on which is a Cyclone IV EP4CE22F17C6 FPGA, connected to an ISSI IS42S16160G-7TLI 16Mx16 SDRAM chip. In order to setup the communication between the FPGA, I've ...
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Error (209025): Can't recognize silicon ID for device 1
I migrated project from DE0-Nano to custom board with Altera Cyclone IV EP4CE22E22 (TQFP-144). I don't know if I migrated it correctly since I am not the author of the project and it's first project ...
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Way to transfer large amount of data between NIOS and FPGA
I'm searching a method to transfer large amount of data (350 bytes) from NIOS processor to FPGA via Avalon Interface. The board I'm using is DE0-Nano from Altera, therefore, I'm trying to implement ...
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What is the Intel FPGA configuration file .pof used for, and how is it different from the file .jic?
The Intel FPGAs have a number of different programming files, among these the files:
.pof (Programmer Object File)
.jic (JTAG Indirect Configuration)
I know that the file .jic can be used to program ...
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FPGA Bank Voltage
If an FPGA bank is physically connected to a regulator voltage of 2.5V and in the software the bank is defined as 1.8V and the I/O standard used for the buffers is also 1.8V, the code compiles without ...
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What sequence of events happen inside FPGA as we power on?
I am using Cyclone V FPGA from Intel on my board. It is configured using external flash.
I would like to understand what happens (sequence of events) inside the FPGA when I power on the board.
Any ...
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How do I find out what pins of an Intel FPGA can be used to connect to different pin groups in EMIF?
If I want to connect my Intel FPGA using EMIF to a high speed DDR Memory e.g Cyclone IV E to DDR3 memory or Max 10 to DDR2 memory, how do I find out what pins can be used for the data, strobe, clock, ...
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Altera JTAG: No device found
I got a task to create a custom board from DE0-Nano dev board. So I used EP4CE22E22C6N as similar chip for hand soldering. But when we ordered USB Blaster, Quartus says No device found.
I try the JTAG ...
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Change clock frequency from 50MHz to 40MHz using Altera Cyclone IV and Quartus Lite 20.1
I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating ...
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create_generated_clock quartus for derived clock
I am working in a design that creates a 1Hz clock from 20MHz PLL out.
For that purpose, I have created a counter that switches its out when its value arrives to 10 000 000.
That 1Hz clock is used as ...
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Intel FPGA: Source-synchronous input using PHY Lite
I have been trying for several months to get hold of information about how to use an Intel PHY Lite IP (for Arria 10 or Cyclone 10 GX) to implement a source-synchronous input interface:
Last December,...
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Intel FPGA Avalon I2C (Master) Core IP: Where are SCL_OUT and SDA_OUT?
This is for Intel MAX10 (10M08) FPGA, NIOS 2 soft core, Quartus (free version), windows 10.
I'm trying to understand this ip core because I need to connect external tri-state buffer to it. The thing ...
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What is the easiest way to replace a design inside an Intel Cyclone SoC? [closed]
I would like to integrate my VHDL submodule to the FPGA fabric of an Intel Cyclone SoC and make it communicating with an App on its Linux.
There is lot of documentation on the internet but I am not ...
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How to constrain a source-synchronous FPGA input?
I have a source-synchronous input to my FPGA (an Intel Cyclone 10 GX 10CX085), coming from an external chip whose datasheet gives the following information:
fmax = 300 MHz (single data rate)
tsetup = ...
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How effective is the Intel video Frame Buffer core when storing in memory?
The Intel Video and Image Processing (VIP) Suite IP has a Video Frame Buffer (VFB) core, named Frame Buffer II IP Core, that can take streaming images on the Avalon-ST IF and save them into memory ...
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JTAG Communication Failure in ARRIA 10 FPGA
Has anyone bricked an ARRIA 10 FGPA (or any FPGA) and successfully unbricked it?
I have an ARRIA 10 that uses an EPCQ-L256 external memory to configure the FPGA. When I uploaded some code, I think I ...
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Constraining combinatorial path delays in Intel Cyclone-V FPGA
I am working on a design with a Cyclone-V FPGA.
I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother.
4 DFFs running on each of these respective ...
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Software to program a Cyclone 10 via JTAG with microcontroller?
I've designed a small circuit board with a Cyclone 10 LP FPGA and an EZ-USB FX2LP microcontroller. My current revision has a 10-pin header for connecting a USB Blaster, and it works just fine that ...
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How to convert from Avalon-MM 128-bit to 48-bit IF?
Some Intel FPGA DDR memory controller only offers 48-bit Avalon-MM IF, when implementing the hard External Memory IF (EMIF) controller.
For connection from a 128-bit Avalon-MM IF, it is therefore ...
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Verilog truth tables [closed]
I am starting in verilog, I am very confused with truth tables, how do I do it in verilog using "if-else", my instructor introduced us to the topic with the following example:
after seeing ...
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Quartus cannot place PLL
I am using Intel/Altera Cyclone V 5CSEMA4U23C6 on DE0-nano-SoC board.
My design is using one PLL that I added a while ago in Platform Designer.
Though it isn't explicitly calling Fractional PLL based ...
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Is it possible to write an "interconnect" in VHDL by hand?
An interconnect connects one or more masters to one or more slaves in a sort of system on chip design. In such a scenario there would be a master containing a standard bus like Avalon-MM, AMBA AXI, ...
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Implement glDrawArrays function in FPGA [duplicate]
I need to implement glDrawArrays function in FPGA.
I understand it's part of the OpenGL library.
I'm trying to get to its source code to figure out what it contains.
Does anyone know of a tool that ...
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How to use command-line to cause Qsys to generate only synthesis or only simulation files?
In my project there are several Qsys files. Some of them are for synthesis but most are for testbench. When changes are made to source code, I usually just run generate Qsys system from the GUI and ...
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How to make Quartus generated programming files for two different but pin compatible FPGAs?
On most porotype boards there is a smaller FPGA which does fit the design but cannot fit a lot of signal tap tap to aid in debugging. Thus, I got a few boards modified with the largest pin compatible ...
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Manually override Quartus Fitter/Pin Assignment constraints
I have a design that I want to synthesize for / upload to a Max 10 FPGA.
One of the inputs goes to a PLL. Quartus now claims, that the neighbouring IO pin is too close to the PLL input pin and won't ...
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Unexpected change when reading input signals in a VHDL Finite State Machine
I implemented a FSM in vhdl using two processes;
A sync process for state transition
...
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Is there a reason to have different files or entities with same name in FPGA project?
In FPGA projects, the files are usually named after the entity they contain. I am trying to figure out these things:
Is it a good practice to have multiple entities in same file?
What if entity and ...
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Unable to constrain HPS peripheral pins on intel agilex fpga dev kit
I'm having trouble getting the Hard Processor System (HPS, the embedded hard processor of the agilex fpga series) to work properly on the Intel Agilex Dev kit version 3. The issue says that that there ...
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What value to use for Byte Count field in PCI Express (PCIe) IO read completion?
In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read.
A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this ...
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Can transceiver replace SPI, I2C and other "normal" methods for high speed data transfer between FPGAs? If so, how? [closed]
SPI, I2C and UART are some well known serial methods for data transfer between devices on the same PCB. However, they all have a data rate bottleneck which is significantly lower than Multi Gigabit ...
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Maximum rate between ADC-FPGA link for Igloo 2 vs Max 10
An ADC has a source synchronous output interface and is to be interfaced with an FPGA. The ADC can communicate using single ended CMOS, DDR CMOS and DDR LVDS. How do I know what is the fastest rate ...
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clkp and clkn inputs in Intel MAX10 FPGAs
The clkp and clkn can be used to insert a differential clock signal into the Intel MAX10 FPGA.
Intel MAX10 FPGA Datasheet
My question is, can we have 2 separate independent single ended clock signals ...
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How does Quartus pin planner know about voltage in each I/O bank?
It is possible to specify a range of I/O standard options in Quartus pin planner. I am trying to understand a few things:
How does Quartus know what voltage is supplied to each bank?
Why does Quartus ...
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LCD 16x2 (I2C) with FPGA (Altera Cyclone II)
this is the question, a few days ago I bought the FPGA Cyclone II development board from altera (I am a big fan of arduino and I have a variety of modules and others) at first I started studying ...
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What is the FPGA with the highest LEs / $?
Well, what is the FPGA with more Logic Elements per Dollar? I already tried to search some sites but the filters for the products do not include that option.