Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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Is there a reason to have different files or entities with same name in FPGA project?

In FPGA projects, the files are usually named after the entity they contain. I am trying to figure out these things: Is it a good practice to have multiple entities in same file? What if entity and ...
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Unable to constrain HPS peripheral pins on intel agilex fpga dev kit

I'm having trouble getting the Hard Processor System (HPS, the embedded hard processor of the agilex fpga series) to work properly on the Intel Agilex Dev kit version 3. The issue says that that there ...
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What value to use for Byte Count field in PCI Express (PCIe) IO read completion?

In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read. A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this ...
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What “portable” NOC architectures exist for use in FPGA designs to be implemented across multiple vendors?

I have used Qsys in Intel Quartus and am aware that it generates an "interconnect fabric" that connects the different peripherals together. The generation of this interconnect is done ...
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Can transceiver replace SPI, I2C and other “normal” methods for high speed data transfer between FPGAs? If so, how? [closed]

SPI, I2C and UART are some well known serial methods for data transfer between devices on the same PCB. However, they all have a data rate bottleneck which is significantly lower than Multi Gigabit ...
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how use text file as input for sinewave and produce sample each clock in tesbench(VHDL)?

so there error is Fatal error in process sinewave_proc at C/..../sin_from_text_tb.vhd at if if not endfile(file_sinewave) I have made a very simple code in vhdl so I can understand how reading a file ...
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Maximum rate between ADC-FPGA link for Igloo 2 vs Max 10

An ADC has a source synchronous output interface and is to be interfaced with an FPGA. The ADC can communicate using single ended CMOS, DDR CMOS and DDR LVDS. How do I know what is the fastest rate ...
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clkp and clkn inputs in Intel MAX10 FPGAs

The clkp and clkn can be used to insert a differential clock signal into the Intel MAX10 FPGA. Intel MAX10 FPGA Datasheet My question is, can we have 2 separate independent single ended clock signals ...
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division by odd number in VHDL?

ModelSim Version INTEL FPGA STARTER EDITION 10.5b # Fatal error in Process line__45 at C:/Users/Desktop/FPGA/division /division.vhd line 59 So I am trying to ...
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How does Quartus pin planner know about voltage in each I/O bank?

It is possible to specify a range of I/O standard options in Quartus pin planner. I am trying to understand a few things: How does Quartus know what voltage is supplied to each bank? Why does Quartus ...
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LCD 16x2 (I2C) with FPGA (Altera Cyclone II)

this is the question, a few days ago I bought the FPGA Cyclone II development board from altera (I am a big fan of arduino and I have a variety of modules and others) at first I started studying ...
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What is the FPGA with the highest LEs / $?

Well, what is the FPGA with more Logic Elements per Dollar? I already tried to search some sites but the filters for the products do not include that option.
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How to implement neural network using FPGA? [closed]

I want to design neural networks using FPGAs and make neuromorphic chip. Is there a tutorial or course to learn how to do that and to implement neural network using FPGA especially for evaluating the ...
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Why is my FPGA clock so slow

To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this: <...
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Quartus Prime Lite: Error (209053): Unexpected error in JTAG server — error code 35 and Error 202940 Can't access JTAG chain with SSH

Today I received a Terasic USB Blaster and I want to program an Altera 10M04SCE144C8G FPGA. I am using the Intel Quartus Prime 20.1.1 Lite Edition installed in Ubuntu 20.04. This FPGA has already been ...
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SPI Altera master IP not behaving as expected

Using Platform designer on Quartus, This is a system with Nios and SPI IP. The code on the nios is attached. This code is supposed to drive the MOSI output to 1 forever, the MOSI on the waveform is ...
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Intel De1-SoC VGA controller in verilog

I am trying to write a vga controller for D1-SOC boards with 640*480 resolution at 60hz. I did a modelsim simulation with it and it seems to be working correctly, but when I program it on fpga it is ...
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Pipelined designs with outputs in differentes delay clocks

I have a pipelined design that ends in 13 clock cycles when the input value is not close to zero, but when the input is close to zero, the design only needs about 4 clock cycles, because of all the ...
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Is there a “universal” JTAG controller peripheral?

JTAG can be used to read/write data from/to FPGAs. I want to know if there is any device with an interpreter that can be used with user written STAPL files. Basically the peripheral shall wiggle the ...
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Altera Quartus detects 2 CPLD devices instead of 1

I try to program a design I made using 5M40ZE64C5N CPLD. The software side was successful and I got a .pof file without any critical warnings or errors. The problem occurs when I try to upload the ...
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49 views

How to transfer blocks of data into FPGA to aid in testing?

How can one transfer data from PC to FPGA and read back result for test purpose where the data must not get corrupted i.e resend if data integrity was lost or use some other error recovery mechanism. ...
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61 views

What timing constrains would I need to set for a handshake based clock transfer

I want to transfer a couple of bits between two clocks, so I build a small handshake logic, but my timing analyzer shows me some violations. Setup/hold violations and in addition some rule check ...
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Help me debug these VHDL errors please

There are just 6 errors now Can't trace errors in this VHDL ...
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113 views

Output waveform of TCS3200

I am trying to use TCS3200 color sensor for my project with De0 nano FPGA board. The output of TCS3200 is a square waveform and i am confused how to use that waveform for a particular task. I searched ...
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MAX10 Flash and separating NIOS Firmware from FPGA config for remote updates

I'm trying to get to grips with how MAX10 memories work, especially if you want to split firmware and FPGA config into completely separate sections. I have read and reread the MAX memory guide, but I'...
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FPGA - synchronise “very close” clock from signal

This is more of a learning question, I can solve the problem but it would be good to know how to do it - can a clock be reconstructed from a signal, and is it easier when the frequency of the clock is ...
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287 views

Intel De1-SoC VGA controller in VHDL

I have implemented a VGA controller in VHDL using the timing specifications for a 600x480 monitor as described in the attached photos. The module takes in a 50MHz clock and is supposed to draw a ...
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100 views

problem in adding IP to platform designer

I'm new to platform designer and I want to add an ALT PLL intel FPGA IP to a platfrom designer project but after opening Mega wizard plugin manager and setting up the requirements, IP does not add to ...
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Verilog design to display character using “16x2 Character Display” IP from Quartus IP Library

I was trying to display a single character on 16x2 display. I created simple Verilog design for "Altera Cyclone V Development Kit". In the project I used "16x2 Character Display" ...
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115 views

Possible to use Segger J-Link with Intel Quartus to flash FPGA?

Does anybody know if it's possible to use a Segger J-Link with Intel Quartus to flash an FPGA?
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42 views

How can Quartus Prime System Console be used to read/write a whole file?

I want to find a way to read/write whole file from/to my Intel FPGA design. The file being written provides data to be processed and the file being read shall contain the results of the processing ...
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Audio Demos on DE10 Standard not Working

I bought the Terasic DE10 Standard and am having issues trying to run the demos related to audio. I am trying to run the two demos, DE10_Standard_Audio, and DE10_Standard_i2sound, while connecting ...
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Can Quartus System Console be used via Ethernet instead of USB Byte Blaster?

The System Console communicates with the the design inside the Intel FPGA via a JTAG-Avalon MM master. The JTAG connection connects to the Byte Blaster and this is how the debugging works. Is there a ...
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Time to Digital Converter using FPGA with Coarse Counter in Verilog

I am currently using Verilog to program an FPGA and create a time-to-digital converter. What I am trying to do is measure the time interval when a square wave is high and then convert this to a binary ...
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The set_command_request procedure from altera_avalon_mm_master_bfm_vhdl_pkg does not return thus master BFM does nothing

I am trying to use the Altera Avalon MM Master BFM in my Qsys testbench. When we want the BFM to make a read or write request, we first call the set_command_request() which is described in the "...
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How Does One Do Block RAM Inference on Altera Cyclone 10 LP FPGA Boards in Verilog [closed]

I have tried to google for this a lot but I can't seem to find anything.
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Setting minimum and mximumu delay from register to asynchronous logic in sdc file

Is it possible to write design constrain in sdc file to tell synthesyser to limit absolut delay from register to asynchronous multiplexer. I have 4 phase shifted clocks and signals synchronized with ...
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122 views

How to create on-board USB blaster for Intel FPGAs?

Intel/Altera FPGA development boards only require a USB cable to configure the FPGAs. There is no need to buy a byte blaster. How is the USB blaster implemented on these boards, is this method/design ...
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Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
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Generating error condition randomly inside a digital design inside FPGA

In order to aid in testing of the design, it is required that we put it into a "debug mode" whereby specific type of error conditions will occur at random intervals. We must then monitor the ...
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How do you select pin functions on an EPM7128 CPLD?

I have some old Altera MAX EPM7128SLC84-15N CPLDs kicking around that I want to use to interface with 5v TTL logic. If you look at the pinout, some of the pins have more than one function (eg. Pin 2 ...
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46 views

FPGA Timing Constrain Problem

I am using the Cyclone V DE1-SoC in transferring data between HPS and ...
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What do HDLs compile/synthesize to?

I'm a software engineer. As a programmer, I have an understanding of what my compiler does for me because I've manually written a close textual representation of what it outputs (e.g. assembly). For ...
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2answers
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Access elements randomly in RAM based FIFO VHDL FPGA

The thing is: new data is being generated every "time step" that can be few clock cycles. So I want to store the data generated for few time steps in a "buffer". The data must be stored like in a ...
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51 views

How to use array in Verilog actually?

I found that inVerilog, the array can only be declared in reg. And I found that it seems ...
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Present two images side by side on the VGA screen from FPGA

Im trying to get a clue how to present two images on the screen using VGA. I using Altera Cyclone 2 DE2 and VGA, I have already working vga sync driver for 640*480 res: ...
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321 views

Variable Bit shift within 1 Clock Cycle (Verilog)

I have a 64-bit register that I would like to right shift n times, with 0<=n<=64, implemented as such always_ff data[63:0] <= (data >> n); I ...
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Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...
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256 views

UART not fast enough for debug purpose, what alternatives exist?

This problem is related with debugging an FPGA design implemented in Intel/Altera FPGA. A custom debug mechanism has been introduced into the design. This new part of the design writes into a FIFO ...
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217 views

PIN Placement Errors In Quartus

So I am writing a simple blinking LED Verilog code that will be run on a Cyclone10 LP (Device is called 10CL025YU256I7G) and will be tested on a Cyclone 10 Evaluation Kit (6XX-44504R-0D) All code is ...

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