Questions tagged [intel-fpga]
A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.
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FPGA Bank Voltage
If an FPGA bank is physically connected to a regulator voltage of 2.5V and in the software the bank is defined as 1.8V and the I/O standard used for the buffers is also 1.8V, the code compiles without ...
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What sequence of events happen inside FPGA as we power on?
I am using Cyclone V FPGA from Intel on my board. It is configured using external flash.
I would like to understand what happens (sequence of events) inside the FPGA when I power on the board.
Any ...
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How do I find out what pins of an Intel FPGA can be used to connect to different pin groups in EMIF?
If I want to connect my Intel FPGA using EMIF to a high speed DDR Memory e.g Cyclone IV E to DDR3 memory or Max 10 to DDR2 memory, how do I find out what pins can be used for the data, strobe, clock, ...
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Altera JTAG: No device found
I got a task to create a custom board from DE0-Nano dev board. So I used EP4CE22E22C6N as similar chip for hand soldering. But when we ordered USB Blaster, Quartus says No device found.
I try the JTAG ...
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IS42S16320F-7TL, reset SDRAM from any state without shutting down
I'm trying to make a SDRAM interface for a IS42S16320F-7TL on a FPGA.
I'm confused about the reset process for the device after it has been set once already. I understand there is an initialization ...
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Change clock frequency from 50MHz to 40MHz using Altera Cyclone IV and Quartus Lite 20.1
I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating ...
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create_generated_clock quartus for derived clock
I am working in a design that creates a 1Hz clock from 20MHz PLL out.
For that purpose, I have created a counter that switches its out when its value arrives to 10 000 000.
That 1Hz clock is used as ...
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Intel FPGA: Source-synchronous input using PHY Lite
I have been trying for several months to get hold of information about how to use an Intel PHY Lite IP (for Arria 10 or Cyclone 10 GX) to implement a source-synchronous input interface:
Last December,...
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Intel FPGA Avalon I2C (Master) Core IP: Where are SCL_OUT and SDA_OUT?
This is for Intel MAX10 (10M08) FPGA, NIOS 2 soft core, Quartus (free version), windows 10.
I'm trying to understand this ip core because I need to connect external tri-state buffer to it. The thing ...
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Intel FPGA MAX10: How do you connect the buffers to the I2C IP core?
This is for Quartus Lite 21.1 (free version), MAX10 (10M08) and NIOS II, BeMicro MAX10 development kit. I know very little Verilog and no VHDL.
I'm trying to learn more about FPGAs so I dusted off (...
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Crying with Cyclone 3 PLL configuration "no remappling logic cells"
I am designing PLL reconfiguration without ALTPLL_RECONFIG for Cyclone III. Quartus 13.1. There's only one clock output for PLL which will be used internally to drive the design.
When almost done, I ...
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What is the easiest way to replace a design inside an Intel Cyclone SoC? [closed]
I would like to integrate my VHDL submodule to the FPGA fabric of an Intel Cyclone SoC and make it communicating with an App on its Linux.
There is lot of documentation on the internet but I am not ...
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How to constrain a source-synchronous FPGA input?
I have a source-synchronous input to my FPGA (an Intel Cyclone 10 GX 10CX085), coming from an external chip whose datasheet gives the following information:
fmax = 300 MHz (single data rate)
tsetup = ...
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Nios2 - GDB Server Timeout
I am programming an Intel Nios2 softcore processor using VS Code and the available command line tools (Ubuntu Linux 18.04.6, Quartus 18.1). The FPGA is an Intel MAX10 device. Everything works fine ...
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How effective is the Intel video Frame Buffer core when storing in memory?
The Intel Video and Image Processing (VIP) Suite IP has a Video Frame Buffer (VFB) core, named Frame Buffer II IP Core, that can take streaming images on the Avalon-ST IF and save them into memory ...
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JTAG Communication Failure in ARRIA 10 FPGA
Has anyone bricked an ARRIA 10 FGPA (or any FPGA) and successfully unbricked it?
I have an ARRIA 10 that uses an EPCQ-L256 external memory to configure the FPGA. When I uploaded some code, I think I ...
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Constraining combinatorial path delays in Intel Cyclone-V FPGA
I am working on a design with a Cyclone-V FPGA.
I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother.
4 DFFs running on each of these respective ...
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Software to program a Cyclone 10 via JTAG with microcontroller?
I've designed a small circuit board with a Cyclone 10 LP FPGA and an EZ-USB FX2LP microcontroller. My current revision has a 10-pin header for connecting a USB Blaster, and it works just fine that ...
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How to convert from Avalon-MM 128-bit to 48-bit IF?
Some Intel FPGA DDR memory controller only offers 48-bit Avalon-MM IF, when implementing the hard External Memory IF (EMIF) controller.
For connection from a 128-bit Avalon-MM IF, it is therefore ...
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Verilog truth tables [closed]
I am starting in verilog, I am very confused with truth tables, how do I do it in verilog using "if-else", my instructor introduced us to the topic with the following example:
after seeing ...
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Quartus cannot place PLL
I am using Intel/Altera Cyclone V 5CSEMA4U23C6 on DE0-nano-SoC board.
My design is using one PLL that I added a while ago in Platform Designer.
Though it isn't explicitly calling Fractional PLL based ...
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Is it possible to write an "interconnect" in VHDL by hand?
An interconnect connects one or more masters to one or more slaves in a sort of system on chip design. In such a scenario there would be a master containing a standard bus like Avalon-MM, AMBA AXI, ...
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Implement glDrawArrays function in FPGA [duplicate]
I need to implement glDrawArrays function in FPGA.
I understand it's part of the OpenGL library.
I'm trying to get to its source code to figure out what it contains.
Does anyone know of a tool that ...
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How to use command-line to cause Qsys to generate only synthesis or only simulation files?
In my project there are several Qsys files. Some of them are for synthesis but most are for testbench. When changes are made to source code, I usually just run generate Qsys system from the GUI and ...
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How to make Quartus generated programming files for two different but pin compatible FPGAs?
On most porotype boards there is a smaller FPGA which does fit the design but cannot fit a lot of signal tap tap to aid in debugging. Thus, I got a few boards modified with the largest pin compatible ...
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Manually override Quartus Fitter/Pin Assignment constraints
I have a design that I want to synthesize for / upload to a Max 10 FPGA.
One of the inputs goes to a PLL. Quartus now claims, that the neighbouring IO pin is too close to the PLL input pin and won't ...
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Unexpected change when reading input signals in a VHDL Finite State Machine
I implemented a FSM in vhdl using two processes;
A sync process for state transition
...
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Is there a reason to have different files or entities with same name in FPGA project?
In FPGA projects, the files are usually named after the entity they contain. I am trying to figure out these things:
Is it a good practice to have multiple entities in same file?
What if entity and ...
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Unable to constrain HPS peripheral pins on intel agilex fpga dev kit
I'm having trouble getting the Hard Processor System (HPS, the embedded hard processor of the agilex fpga series) to work properly on the Intel Agilex Dev kit version 3. The issue says that that there ...
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What value to use for Byte Count field in PCI Express (PCIe) IO read completion?
In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read.
A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this ...
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Can transceiver replace SPI, I2C and other "normal" methods for high speed data transfer between FPGAs? If so, how? [closed]
SPI, I2C and UART are some well known serial methods for data transfer between devices on the same PCB. However, they all have a data rate bottleneck which is significantly lower than Multi Gigabit ...
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how use text file as input for sinewave and produce sample each clock in tesbench(VHDL)?
so there error is
Fatal error in process sinewave_proc at C/..../sin_from_text_tb.vhd at if if not endfile(file_sinewave)
I have made a very simple code in vhdl so I can understand how reading a file ...
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Maximum rate between ADC-FPGA link for Igloo 2 vs Max 10
An ADC has a source synchronous output interface and is to be interfaced with an FPGA. The ADC can communicate using single ended CMOS, DDR CMOS and DDR LVDS. How do I know what is the fastest rate ...
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clkp and clkn inputs in Intel MAX10 FPGAs
The clkp and clkn can be used to insert a differential clock signal into the Intel MAX10 FPGA.
Intel MAX10 FPGA Datasheet
My question is, can we have 2 separate independent single ended clock signals ...
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How does Quartus pin planner know about voltage in each I/O bank?
It is possible to specify a range of I/O standard options in Quartus pin planner. I am trying to understand a few things:
How does Quartus know what voltage is supplied to each bank?
Why does Quartus ...
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LCD 16x2 (I2C) with FPGA (Altera Cyclone II)
this is the question, a few days ago I bought the FPGA Cyclone II development board from altera (I am a big fan of arduino and I have a variety of modules and others) at first I started studying ...
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What is the FPGA with the highest LEs / $?
Well, what is the FPGA with more Logic Elements per Dollar? I already tried to search some sites but the filters for the products do not include that option.
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How to implement neural network using FPGA? [closed]
I want to design neural networks using FPGAs and make neuromorphic chip. Is there a tutorial or course to learn how to do that and to implement neural network using FPGA especially for evaluating the ...
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Why is my FPGA clock so slow
To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this:
<...
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Quartus Prime Lite: Error (209053): Unexpected error in JTAG server -- error code 35 and Error 202940 Can't access JTAG chain with SSH
Today I received a Terasic USB Blaster and I want to program an Altera 10M04SCE144C8G FPGA. I am using the Intel Quartus Prime 20.1.1 Lite Edition installed in Ubuntu 20.04. This FPGA has already been ...
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Pipelined designs with outputs in differentes delay clocks
I have a pipelined design that ends in 13 clock cycles when the input value is not close to zero, but when the input is close to zero, the design only needs about 4 clock cycles, because of all the ...
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Is there a "universal" JTAG controller peripheral?
JTAG can be used to read/write data from/to FPGAs. I want to know if there is any device with an interpreter that can be used with user written STAPL files. Basically the peripheral shall wiggle the ...
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Altera Quartus detects 2 CPLD devices instead of 1
I try to program a design I made using 5M40ZE64C5N CPLD. The software side was successful and I got a .pof file without any critical warnings or errors. The problem occurs when I try to upload the ...
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How to transfer blocks of data into FPGA to aid in testing?
How can one transfer data from PC to FPGA and read back result for test purpose where the data must not get corrupted i.e resend if data integrity was lost or use some other error recovery mechanism. ...
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What timing constrains would I need to set for a handshake based clock transfer
I want to transfer a couple of bits between two clocks, so I build a small handshake logic, but my timing analyzer shows me some violations.
Setup/hold violations and in addition some rule check ...
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Help me debug these VHDL errors please
There are just 6 errors now
Can't trace errors in this VHDL
...
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Output waveform of TCS3200
I am trying to use TCS3200 color sensor for my project with De0 nano FPGA board. The output of TCS3200 is a square waveform and i am confused how to use that waveform for a particular task.
I searched ...
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MAX10 Flash and separating NIOS Firmware from FPGA config for remote updates
I'm trying to get to grips with how MAX10 memories work, especially if you want to split firmware and FPGA config into completely separate sections. I have read and reread the MAX memory guide, but I'...
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FPGA - synchronise “very close” clock from signal
This is more of a learning question, I can solve the problem but it would be good to know how to do it - can a clock be reconstructed from a signal, and is it easier when the frequency of the clock is ...
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Intel De1-SoC VGA controller in VHDL
I have implemented a VGA controller in VHDL using the timing specifications for a 600x480 monitor as described in the attached photos. The module takes in a 50MHz clock and is supposed to draw a ...
