Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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87 views

How to constrain a source-synchronous FPGA input?

I have a source-synchronous input to my FPGA (an Intel Cyclone 10 GX 10CX085), coming from an external chip whose datasheet gives the following information: fmax = 300 MHz (single data rate) tsetup = ...
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Nios2 - GDB Server Timeout

I am programming an Intel Nios2 softcore processor using VS Code and the available command line tools (Ubuntu Linux 18.04.6, Quartus 18.1). The FPGA is an Intel MAX10 device. Everything works fine ...
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62 views

How effective is the Intel video Frame Buffer core when storing in memory?

The Intel Video and Image Processing (VIP) Suite IP has a Video Frame Buffer (VFB) core, named Frame Buffer II IP Core, that can take streaming images on the Avalon-ST IF and save them into memory ...
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JTAG Communication Failure in ARRIA 10 FPGA

Has anyone bricked an ARRIA 10 FGPA (or any FPGA) and successfully unbricked it? I have an ARRIA 10 that uses an EPCQ-L256 external memory to configure the FPGA. When I uploaded some code, I think I ...
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73 views

Constraining combinatorial path delays in Intel Cyclone-V FPGA

I am working on a design with a Cyclone-V FPGA. I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother. 4 DFFs running on each of these respective ...
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80 views

Software to program a Cyclone 10 via JTAG with microcontroller?

I've designed a small circuit board with a Cyclone 10 LP FPGA and an EZ-USB FX2LP microcontroller. My current revision has a 10-pin header for connecting a USB Blaster, and it works just fine that ...
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34 views

How to convert from Avalon-MM 128-bit to 48-bit IF?

Some Intel FPGA DDR memory controller only offers 48-bit Avalon-MM IF, when implementing the hard External Memory IF (EMIF) controller. For connection from a 128-bit Avalon-MM IF, it is therefore ...
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93 views

Verilog truth tables [closed]

I am starting in verilog, I am very confused with truth tables, how do I do it in verilog using "if-else", my instructor introduced us to the topic with the following example: after seeing ...
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185 views

Quartus cannot place PLL

I am using Intel/Altera Cyclone V 5CSEMA4U23C6 on DE0-nano-SoC board. My design is using one PLL that I added a while ago in Platform Designer. Though it isn't explicitly calling Fractional PLL based ...
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74 views

Is it possible to write an "interconnect" in VHDL by hand?

An interconnect connects one or more masters to one or more slaves in a sort of system on chip design. In such a scenario there would be a master containing a standard bus like Avalon-MM, AMBA AXI, ...
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72 views

Implement glDrawArrays function in FPGA [duplicate]

I need to implement glDrawArrays function in FPGA. I understand it's part of the OpenGL library. I'm trying to get to its source code to figure out what it contains. Does anyone know of a tool that ...
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65 views

How to use command-line to cause Qsys to generate only synthesis or only simulation files?

In my project there are several Qsys files. Some of them are for synthesis but most are for testbench. When changes are made to source code, I usually just run generate Qsys system from the GUI and ...
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How to make Quartus generated programming files for two different but pin compatible FPGAs?

On most porotype boards there is a smaller FPGA which does fit the design but cannot fit a lot of signal tap tap to aid in debugging. Thus, I got a few boards modified with the largest pin compatible ...
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28 views

Manually override Quartus Fitter/Pin Assignment constraints

I have a design that I want to synthesize for / upload to a Max 10 FPGA. One of the inputs goes to a PLL. Quartus now claims, that the neighbouring IO pin is too close to the PLL input pin and won't ...
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81 views

Unexpected change when reading input signals in a VHDL Finite State Machine

I implemented a FSM in vhdl using two processes; A sync process for state transition ...
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112 views

Is there a reason to have different files or entities with same name in FPGA project?

In FPGA projects, the files are usually named after the entity they contain. I am trying to figure out these things: Is it a good practice to have multiple entities in same file? What if entity and ...
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66 views

Unable to constrain HPS peripheral pins on intel agilex fpga dev kit

I'm having trouble getting the Hard Processor System (HPS, the embedded hard processor of the agilex fpga series) to work properly on the Intel Agilex Dev kit version 3. The issue says that that there ...
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1answer
124 views

What value to use for Byte Count field in PCI Express (PCIe) IO read completion?

In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read. A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this ...
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What "portable" NOC architectures exist for use in FPGA designs to be implemented across multiple vendors?

I have used Qsys in Intel Quartus and am aware that it generates an "interconnect fabric" that connects the different peripherals together. The generation of this interconnect is done ...
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100 views

Can transceiver replace SPI, I2C and other "normal" methods for high speed data transfer between FPGAs? If so, how? [closed]

SPI, I2C and UART are some well known serial methods for data transfer between devices on the same PCB. However, they all have a data rate bottleneck which is significantly lower than Multi Gigabit ...
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52 views

how use text file as input for sinewave and produce sample each clock in tesbench(VHDL)?

so there error is Fatal error in process sinewave_proc at C/..../sin_from_text_tb.vhd at if if not endfile(file_sinewave) I have made a very simple code in vhdl so I can understand how reading a file ...
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2answers
89 views

Maximum rate between ADC-FPGA link for Igloo 2 vs Max 10

An ADC has a source synchronous output interface and is to be interfaced with an FPGA. The ADC can communicate using single ended CMOS, DDR CMOS and DDR LVDS. How do I know what is the fastest rate ...
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60 views

clkp and clkn inputs in Intel MAX10 FPGAs

The clkp and clkn can be used to insert a differential clock signal into the Intel MAX10 FPGA. Intel MAX10 FPGA Datasheet My question is, can we have 2 separate independent single ended clock signals ...
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143 views

How does Quartus pin planner know about voltage in each I/O bank?

It is possible to specify a range of I/O standard options in Quartus pin planner. I am trying to understand a few things: How does Quartus know what voltage is supplied to each bank? Why does Quartus ...
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163 views

LCD 16x2 (I2C) with FPGA (Altera Cyclone II)

this is the question, a few days ago I bought the FPGA Cyclone II development board from altera (I am a big fan of arduino and I have a variety of modules and others) at first I started studying ...
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76 views

What is the FPGA with the highest LEs / $?

Well, what is the FPGA with more Logic Elements per Dollar? I already tried to search some sites but the filters for the products do not include that option.
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95 views

How to implement neural network using FPGA? [closed]

I want to design neural networks using FPGAs and make neuromorphic chip. Is there a tutorial or course to learn how to do that and to implement neural network using FPGA especially for evaluating the ...
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Why is my FPGA clock so slow

To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this: <...
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740 views

Quartus Prime Lite: Error (209053): Unexpected error in JTAG server -- error code 35 and Error 202940 Can't access JTAG chain with SSH

Today I received a Terasic USB Blaster and I want to program an Altera 10M04SCE144C8G FPGA. I am using the Intel Quartus Prime 20.1.1 Lite Edition installed in Ubuntu 20.04. This FPGA has already been ...
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38 views

SPI Altera master IP not behaving as expected

Using Platform designer on Quartus, This is a system with Nios and SPI IP. The code on the nios is attached. This code is supposed to drive the MOSI output to 1 forever, the MOSI on the waveform is ...
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47 views

Pipelined designs with outputs in differentes delay clocks

I have a pipelined design that ends in 13 clock cycles when the input value is not close to zero, but when the input is close to zero, the design only needs about 4 clock cycles, because of all the ...
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54 views

Is there a "universal" JTAG controller peripheral?

JTAG can be used to read/write data from/to FPGAs. I want to know if there is any device with an interpreter that can be used with user written STAPL files. Basically the peripheral shall wiggle the ...
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2answers
127 views

Altera Quartus detects 2 CPLD devices instead of 1

I try to program a design I made using 5M40ZE64C5N CPLD. The software side was successful and I got a .pof file without any critical warnings or errors. The problem occurs when I try to upload the ...
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74 views

How to transfer blocks of data into FPGA to aid in testing?

How can one transfer data from PC to FPGA and read back result for test purpose where the data must not get corrupted i.e resend if data integrity was lost or use some other error recovery mechanism. ...
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70 views

What timing constrains would I need to set for a handshake based clock transfer

I want to transfer a couple of bits between two clocks, so I build a small handshake logic, but my timing analyzer shows me some violations. Setup/hold violations and in addition some rule check ...
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158 views

Help me debug these VHDL errors please

There are just 6 errors now Can't trace errors in this VHDL ...
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235 views

Output waveform of TCS3200

I am trying to use TCS3200 color sensor for my project with De0 nano FPGA board. The output of TCS3200 is a square waveform and i am confused how to use that waveform for a particular task. I searched ...
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137 views

MAX10 Flash and separating NIOS Firmware from FPGA config for remote updates

I'm trying to get to grips with how MAX10 memories work, especially if you want to split firmware and FPGA config into completely separate sections. I have read and reread the MAX memory guide, but I'...
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169 views

FPGA - synchronise “very close” clock from signal

This is more of a learning question, I can solve the problem but it would be good to know how to do it - can a clock be reconstructed from a signal, and is it easier when the frequency of the clock is ...
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453 views

Intel De1-SoC VGA controller in VHDL

I have implemented a VGA controller in VHDL using the timing specifications for a 600x480 monitor as described in the attached photos. The module takes in a 50MHz clock and is supposed to draw a ...
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176 views

problem in adding IP to platform designer

I'm new to platform designer and I want to add an ALT PLL intel FPGA IP to a platfrom designer project but after opening Mega wizard plugin manager and setting up the requirements, IP does not add to ...
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180 views

Verilog design to display character using "16x2 Character Display" IP from Quartus IP Library

I was trying to display a single character on 16x2 display. I created simple Verilog design for "Altera Cyclone V Development Kit". In the project I used "16x2 Character Display" ...
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240 views

Possible to use Segger J-Link with Intel Quartus to flash FPGA?

Does anybody know if it's possible to use a Segger J-Link with Intel Quartus to flash an FPGA?
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How can Quartus Prime System Console be used to read/write a whole file?

I want to find a way to read/write whole file from/to my Intel FPGA design. The file being written provides data to be processed and the file being read shall contain the results of the processing ...
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80 views

Audio Demos on DE10 Standard not Working

I bought the Terasic DE10 Standard and am having issues trying to run the demos related to audio. I am trying to run the two demos, DE10_Standard_Audio, and DE10_Standard_i2sound, while connecting ...
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135 views

How Does One Do Block RAM Inference on Altera Cyclone 10 LP FPGA Boards in Verilog [closed]

I have tried to google for this a lot but I can't seem to find anything.
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314 views

How to create on-board USB blaster for Intel FPGAs?

Intel/Altera FPGA development boards only require a USB cable to configure the FPGAs. There is no need to buy a byte blaster. How is the USB blaster implemented on these boards, is this method/design ...
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194 views

Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
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79 views

Generating error condition randomly inside a digital design inside FPGA

In order to aid in testing of the design, it is required that we put it into a "debug mode" whereby specific type of error conditions will occur at random intervals. We must then monitor the ...
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197 views

How do you select pin functions on an EPM7128 CPLD?

I have some old Altera MAX EPM7128SLC84-15N CPLDs kicking around that I want to use to interface with 5v TTL logic. If you look at the pinout, some of the pins have more than one function (eg. Pin 2 ...

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