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Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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Weird FSM behavior on the start only

I am a vhdl beginner working on this entity that goes through 256 12bits inputs alternating with even index inputs in "a_s" and odd ones in "b_s" and this 16 inputs at a time (8 in ...
Anis Bensidhoum's user avatar
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1 answer
59 views

Altera FLEX 8000: Extracting "bitstream" from .sof file?

I've acquired an Altera FLEX 8282A FPGA and I'd like to have a bit of a play with it. Yes, I know these are prehistoric parts, but I like playing around with old stuff. :-) I've installed MAX+Plus II ...
Tom S's user avatar
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How to fix erased On-Board Usb-Blaster FPGA (MAX II EPM240T100C3 on board Terasic DE10-Lite)

I have Terasic DE10-Lite board (with Altera MAX10 fpga), which use Altera Max II EPM240T100C3N (and usb-b + ftdi chip) for on-board usb-blaster logic. After explore 8 pins jtag holes on the board, i ...
Lion's user avatar
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How to flash Altera EPM7256E?

I am working on legacy bit of hardware. I see that EPM7256S can be flashed as usual, via JTAG using standard (modern) tools, so this is quite clear. But how to flash EPM7256E? Are the any inexpensive ...
BarsMonster's user avatar
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Quartus: too long compilation time problem - Stratix 10

I have a big design the suffering from very long compilation times, The time is about 7hours to 8hours. I would like to know if its normal according to the following details: FPGA Device: Intel ...
Michael Rahav's user avatar
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3 answers
53 views

When does the tRAMP timing begin for Cyclone 5 Power Supplies?

I am currently designing a power supply setup for a Cyclone 5 FPGA. In the datasheet, it is stated that if power supplies do not reach operating conditions within the maximum tRAMP time allowed (100ms ...
DownInFlames's user avatar
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1 answer
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Is it possible to use registers on Intel‑based FPGAs ? If not what’s the alternative for solving the bandwidth issue?

In order to bruteforce a key where the first private’s key bytes are known (leaving 270 possible private key to search) I’d like to do the following: pick up a 64‑bit private key range split that ...
user2284570's user avatar
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Guidelines for reducing levels of logic cells in FPGAs while using HDL operators in behavioral modelling

Timing closure in FPGAs is a challenging subject. There are many guidelines, one of them: pipelining, is to introduce new registers in the data path so that the overall combinational logic gets ...
lousycoder's user avatar
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75 views

Issue with Running Two Separate Codes on Intel Cyclone V SoC ARM Cortex A9 Dual Core via QSPI

I am working on an Intel Cyclone V SoC ARM Cortex A9 Dual Core setup and aiming to execute two distinct codes on Core 0 and Core 1 in bare-metal mode. While I've successfully executed this setup using ...
Support's user avatar
3 votes
1 answer
454 views

How do FPGAs implement the inequality operator?

From curiosity and to understand the cost of the operator I often using in FPGA design. Let's assume I am doing the following equation in Verilog: ...
Michael Rahav's user avatar
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Assistance Needed: Trouble Running Bare-Metal Code on second core in Cyclone V SoC

I am working on intel cyclone 5 hps I have two cores in a processor Core 0 core 1, I want two code to run on two different cores core 0 and core 1 in bare metal. When I run in jtag mode it works, for ...
Support's user avatar
2 votes
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39 views

Channel-style routing on Altera FPGAs

A Tutorial on FPGA Routing claims that there are two different FPGA routing styles; channel-style ASIC routing and island style routing: Academic research has adopted as FPGA architecture a ...
Gaslight Deceive Subvert's user avatar
1 vote
1 answer
185 views

Unable to write to MT25QU256 from Arria 10 SOM

I am using module Arria 10 SOM by iWave with IC Flash MT25QU256. I am trying to read and write from NIOS II processor to different sectors of this flash. Currently, I'm using the IP Core Generic Quad ...
LowK's user avatar
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How to obtain the counting of TTL pulses from an FPGA?

I'm currently working on a project in which I need to program an FPGA in order to connect it to a photon detector, that generates a TTL pulse when detecting a photon; I need to count this pulses, ...
Jorsa's user avatar
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Storing Data and Instructions in Memory

I have implemented a RiscV32 single cycle processor using Verilog. Now I am trying to upload it to a FPGA (DE2 - 115 board) and check the functioning. But how do I store instructions and data in the ...
KS Hewa's user avatar
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Intel DCFIFO IP crashing when using a clock with decimal place

I need to build a FIFO with a 96 MHz write clock and a 25.175 MHz read clock. The data are read from an SDRAM and are fed into the VGA output. To do that I use the intel DCFIFO IP and PLL IP. The PLL ...
TimSch's user avatar
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2 votes
1 answer
729 views

Error while trying to bind SystemVerilog module with properties module

I have a SystemVerilog module that I want to test using assertions. For simplicity let's say the DUT is this: ...
Kyriafinis Vasilis's user avatar
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51 views

SDRAM Voltage and pin planner consequences

I have this SDRAM module: According to the docs: am I right that it's the 3,3V version? If yes: what are the consequences of that fact using the Pin Planner? Is it correct that I have to set the I/O ...
TimSch's user avatar
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Cyclone III FPGA 16x2 LCD repeat one character instead of displaying complete word

So I am trying to use the LCD on the cyclone III FPGA. I have written this verilog code that should display numbers 0 to 9 then letters A to G Compiling the code has no errors at all However, when ...
Mahmoud Khodier's user avatar
4 votes
1 answer
147 views

Debuging verilog SDRAM controller

I've been working on a project that involves the creation of a SDRAM Controller in verilog for an Altera DE2 prototyping board. Despite reading the documentation for the memory chip on the board, ...
bieux's user avatar
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1 answer
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Difficulty in understanding the USB interfacing for Altera DE 2

So I am planning to establish connection between my mouse and the USB Host port of the Altera DE-2 board. As per the documentation the Altera DE-2 board uses the Philips ISP1362 chip which follows the ...
Rezef's user avatar
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1 vote
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190 views

How to generate 3 pulses of varying lengths with an FPGA and Verilog?

I am trying to generate 3 pulses of 2 different lengths at specific times using an Arduino MKR Vidor 4000 which has an Intel Cyclone 10 on board. I need to generate one pulse with 5 µs length followed ...
solomonsanderson's user avatar
2 votes
1 answer
622 views

Problem in programming ALTERA MAX 7000S CPLD with homemade Byte Blaster

I am trying to read back an ALTERA MAX 7000S CPLD (EPM7064SLC84-10) mounted on a board (a part of the board's schematic is shown below) and copy it on another CPLD. In the schematic, X4 is a male 10 ...
pooya's user avatar
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Getting the warning WARNING:Xst:1710 and WARNING:Xst:1895 while running my top module

My aim is to find the pulse width of an unknown incoming signal. To that I have written the following synthesizable verilog code but I am getting the warning XST 1710 and XST 1895. When I try to ...
Bojack Horseman's user avatar
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The routing delay is 0 ns in quartus chipplanner

I designed a program about TDC. However, I found the routing delay is 0 ns when I check its timming by Timequest. Shown below, the Tco is 0.073 ns, but the routing delay is 0 ns. Obviously, there is ...
rushi's user avatar
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2 votes
2 answers
597 views

FPGA to SDRAM communication

I am working with a DE0-nano board, on which is a Cyclone IV EP4CE22F17C6 FPGA, connected to an ISSI IS42S16160G-7TLI 16Mx16 SDRAM chip. In order to setup the communication between the FPGA, I've ...
Jambon's user avatar
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1 answer
1k views

Error (209025): Can't recognize silicon ID for device 1

I migrated project from DE0-Nano to custom board with Altera Cyclone IV EP4CE22E22 (TQFP-144). I don't know if I migrated it correctly since I am not the author of the project and it's first project ...
Jirka Picek's user avatar
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2 answers
121 views

Way to transfer large amount of data between NIOS and FPGA

I'm searching a method to transfer large amount of data (350 bytes) from NIOS processor to FPGA via Avalon Interface. The board I'm using is DE0-Nano from Altera, therefore, I'm trying to implement ...
LowK's user avatar
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1 vote
1 answer
2k views

What is the Intel FPGA configuration file .pof used for, and how is it different from the file .jic?

The Intel FPGAs have a number of different programming files, among these the files: .pof (Programmer Object File) .jic (JTAG Indirect Configuration) I know that the file .jic can be used to program ...
EquipDev's user avatar
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1 vote
2 answers
539 views

FPGA Bank Voltage

If an FPGA bank is physically connected to a regulator voltage of 2.5V and in the software the bank is defined as 1.8V and the I/O standard used for the buffers is also 1.8V, the code compiles without ...
Shannon's user avatar
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62 views

What sequence of events happen inside FPGA as we power on?

I am using Cyclone V FPGA from Intel on my board. It is configured using external flash. I would like to understand what happens (sequence of events) inside the FPGA when I power on the board. Any ...
VINAY DESAI's user avatar
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57 views

How do I find out what pins of an Intel FPGA can be used to connect to different pin groups in EMIF?

If I want to connect my Intel FPGA using EMIF to a high speed DDR Memory e.g Cyclone IV E to DDR3 memory or Max 10 to DDR2 memory, how do I find out what pins can be used for the data, strobe, clock, ...
quantum231's user avatar
0 votes
1 answer
526 views

Altera JTAG: No device found

I got a task to create a custom board from DE0-Nano dev board. So I used EP4CE22E22C6N as similar chip for hand soldering. But when we ordered USB Blaster, Quartus says No device found. I try the JTAG ...
Jirka Picek's user avatar
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1 answer
656 views

Change clock frequency from 50MHz to 40MHz using Altera Cyclone IV and Quartus Lite 20.1

I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating ...
Yury Euceda's user avatar
2 votes
1 answer
644 views

create_generated_clock quartus for derived clock

I am working in a design that creates a 1Hz clock from 20MHz PLL out. For that purpose, I have created a counter that switches its out when its value arrives to 10 000 000. That 1Hz clock is used as ...
mugurumov's user avatar
2 votes
1 answer
224 views

Intel FPGA: Source-synchronous input using PHY Lite

I have been trying for several months to get hold of information about how to use an Intel PHY Lite IP (for Arria 10 or Cyclone 10 GX) to implement a source-synchronous input interface: Last December,...
Harry's user avatar
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1 answer
922 views

Intel FPGA Avalon I2C (Master) Core IP: Where are SCL_OUT and SDA_OUT?

This is for Intel MAX10 (10M08) FPGA, NIOS 2 soft core, Quartus (free version), windows 10. I'm trying to understand this ip core because I need to connect external tri-state buffer to it. The thing ...
Rodo's user avatar
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1 vote
1 answer
151 views

What is the easiest way to replace a design inside an Intel Cyclone SoC? [closed]

I would like to integrate my VHDL submodule to the FPGA fabric of an Intel Cyclone SoC and make it communicating with an App on its Linux. There is lot of documentation on the internet but I am not ...
dsp_curious's user avatar
2 votes
1 answer
674 views

How to constrain a source-synchronous FPGA input?

I have a source-synchronous input to my FPGA (an Intel Cyclone 10 GX 10CX085), coming from an external chip whose datasheet gives the following information: fmax = 300 MHz (single data rate) tsetup = ...
Harry's user avatar
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0 votes
1 answer
190 views

How effective is the Intel video Frame Buffer core when storing in memory?

The Intel Video and Image Processing (VIP) Suite IP has a Video Frame Buffer (VFB) core, named Frame Buffer II IP Core, that can take streaming images on the Avalon-ST IF and save them into memory ...
EquipDev's user avatar
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0 votes
1 answer
183 views

JTAG Communication Failure in ARRIA 10 FPGA

Has anyone bricked an ARRIA 10 FGPA (or any FPGA) and successfully unbricked it? I have an ARRIA 10 that uses an EPCQ-L256 external memory to configure the FPGA. When I uploaded some code, I think I ...
Aaron's user avatar
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3 votes
2 answers
423 views

Constraining combinatorial path delays in Intel Cyclone-V FPGA

I am working on a design with a Cyclone-V FPGA. I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother. 4 DFFs running on each of these respective ...
cplusruss's user avatar
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0 votes
4 answers
634 views

Software to program a Cyclone 10 via JTAG with microcontroller?

I've designed a small circuit board with a Cyclone 10 LP FPGA and an EZ-USB FX2LP microcontroller. My current revision has a 10-pin header for connecting a USB Blaster, and it works just fine that ...
Andrew's user avatar
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1 vote
0 answers
61 views

How to convert from Avalon-MM 128-bit to 48-bit IF?

Some Intel FPGA DDR memory controller only offers 48-bit Avalon-MM IF, when implementing the hard External Memory IF (EMIF) controller. For connection from a 128-bit Avalon-MM IF, it is therefore ...
EquipDev's user avatar
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-4 votes
1 answer
508 views

Verilog truth tables [closed]

I am starting in verilog, I am very confused with truth tables, how do I do it in verilog using "if-else", my instructor introduced us to the topic with the following example: after seeing ...
Rafael Lozano's user avatar
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1 answer
2k views

Quartus cannot place PLL

I am using Intel/Altera Cyclone V 5CSEMA4U23C6 on DE0-nano-SoC board. My design is using one PLL that I added a while ago in Platform Designer. Though it isn't explicitly calling Fractional PLL based ...
Martin Vana's user avatar
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1 answer
261 views

Is it possible to write an "interconnect" in VHDL by hand?

An interconnect connects one or more masters to one or more slaves in a sort of system on chip design. In such a scenario there would be a master containing a standard bus like Avalon-MM, AMBA AXI, ...
quantum231's user avatar
-2 votes
1 answer
84 views

Implement glDrawArrays function in FPGA [duplicate]

I need to implement glDrawArrays function in FPGA. I understand it's part of the OpenGL library. I'm trying to get to its source code to figure out what it contains. Does anyone know of a tool that ...
ohad's user avatar
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-1 votes
1 answer
712 views

How to use command-line to cause Qsys to generate only synthesis or only simulation files?

In my project there are several Qsys files. Some of them are for synthesis but most are for testbench. When changes are made to source code, I usually just run generate Qsys system from the GUI and ...
quantum231's user avatar
3 votes
3 answers
619 views

How to make Quartus generated programming files for two different but pin compatible FPGAs?

On most porotype boards there is a smaller FPGA which does fit the design but cannot fit a lot of signal tap tap to aid in debugging. Thus, I got a few boards modified with the largest pin compatible ...
quantum231's user avatar

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