Newest 'intel-fpga' Questions

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Verilog 'if' statement error

Why are LEDs on after executing this? LEDs on pattern is 1010: ...

asked Jul 17 at 20:31

misha

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1answer

56 views

Intel FPGA equivalents of Xilinx IBUFDS Primitives?

Im trying to migrate an Design from using Xilinx primitives to Intel Altera FPGA. The original design uses the IBUFDS for the clock signals. ...

fpga xilinx intel-fpga buffer

asked Jun 19 at 9:50

Bá Anh Đào

31 bronze badge

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2answers

28 views

How can Qsys component configuration be accessed in software?

I'm designing a Qsys component which I want to be user-configurable. It has config parameters which are defined in the TCL file. For example, for a GPIO bank component I would write: ...

c intel-fpga quartus soc

asked Jun 16 at 10:31

Dmitry Grigoryev

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83 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...

fpga intel-fpga pll quartus

asked Jun 11 at 8:03

Olupo

337 bronze badges

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LMS7002M: I & Q DATA formats from LIMESDR

Can any one tell me what is the data format of LMS7002m I & Q sample? Are they unsigned int or floating or double? how are they ? Also kindly anyone show me any hint of proof for their answer.... ...

intel-fpga sdr

asked Jun 4 at 18:48

ARKARUP7304

11 bronze badge

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70 views

altera FPGA acting like OR gate when programed as AND gate

I'm new to altera fpga , I've bought development board based on EP4CE6E22 cyclon IV and tryed to program it with basic program in quartus environment ...

fpga intel-fpga quartus

asked Jun 1 at 10:00

Ron Vaisman

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1answer

842 views

what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and ...

fpga vhdl intel-fpga virtex-series-fpga microsemi-fpga

asked May 31 at 6:10

srihari

332 bronze badges

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38 views

Custom PCIe DMA on Cyclone 10GX FPGA burst read stucks

I'm writing a custom DMA machine to read and write data to the host system from FPGA memory. I use the Altera PCIe IP core as end point device in Avalon-MM mode. BAR0 is set as 64bit bar, Avalon-MM ...

intel-fpga linux pcie dma

asked Mar 28 at 16:18

mishaskt

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In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...

intel-fpga timing-analysis quartus

asked Mar 27 at 19:43

shparekh

1378 bronze badges

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36 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...

fpga verilog intel-fpga register synthesis

asked Feb 17 at 20:34

axk

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52 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...

fpga xilinx intel-fpga timing-analysis

asked Feb 17 at 18:04

Sourabh Tapas

13410 bronze badges

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159 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...

fpga vhdl spi intel-fpga quartus

asked Feb 6 at 13:26

SDwarfs

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How can I check if an IO pin is dead?

I've been playing around with I2C for a couple days now with a DE10-Nano dev board: I'm implementing an I2C master in CLaSH so that I can talk to the HDMI encoder chip, but for now I'm talking to an ...

fpga gpio pins intel-fpga

asked Feb 6 at 8:59

Cactus

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27 views

Why does functional simulation generate Zs?

I have a very simple project, I share the files in this github repo If I run a functional simulation (Waveform.vwf in the repository) I get some 'Z' in the value of an internal register, see the ...

simulation intel-fpga quartus

asked Feb 5 at 10:57

Fabio Dalla Libera

1339 bronze badges

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76 views

What's wrong with this schematic for powering up Cyclone IV FPGA?

I have followed all the guide lines for powering up the Cyclone IV. However, the 3.3v Regulator is heating too much and also the Cyclone IV FPGA. What's wrong with my schematic? Is there a problem in ...

fpga intel-fpga cyclone

asked Jan 16 at 14:00

Alpha0

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Altera FlipFlop stuck at GND

I'm trying to make a counter that counts: 0,1,2,3,4,5 I need this for a frequency divider of 6 So I made this table: From this I get: J0= 1 K0= 1 J1 = NOT Q0 AND Q1 K1 = Q1 J2 = Q1 AND Q2 K2 =...

simulation flipflop counter intel-fpga

asked Dec 31 '18 at 20:13

Fox Alex

51 bronze badge

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43 views

Identify valid FPGA configuration image in serial flash device?

How can I know if there's valid FPGA configuration image in the specific location of the serial configuration device before I perform reconfiguration and experience successful or faulty attempt? ...

intel-fpga cyclone

asked Dec 25 '18 at 10:27

Anonymous

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67 views

can't send characters using fpga cyclone iv

I'm trying to connect my FPGA Cylone IV (CoreEP4CE6) with Raspberry Pi 3 for communication through UART. The process (uart_rx) for receiving data is working fine, however, when I place another process ...

fpga uart intel-fpga

asked Dec 20 '18 at 18:54

Alpha0

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236 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...

fpga intel-fpga quartus intel max10

asked Dec 18 '18 at 19:42

quantum231

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Altera has created EPCS and EPCQ devices, can only these be used to store FPGA configuration data?

FPGA configuration data must be stored in external non-volatile memory. Can we use just any flash memory or only specific types? What about EEPROMs or any other nonvolatile memory device? Edit: I am ...

fpga intel-fpga configuration intel

asked Dec 16 '18 at 17:18

quantum231

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2answers

234 views

Program FPGA using STM32

I am interested in using an STM32 to flash an sof or pof file onto a Cyclone IV FPGA. The sof/pof will be stored in SPI flash memory, and the plan is to use the STM32 as a programmer. I haven't been ...

fpga stm32 intel-fpga

asked Dec 5 '18 at 23:20

jgaro

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Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...

fpga vhdl verilog xilinx intel-fpga

asked Dec 1 '18 at 15:54

Sourabh Tapas

13410 bronze badges

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75 views

Get more AS-attached flash chip information from ALTASMI

I am playing with the attaching various configuration flash devices to the Altera Cyclone 3. In particular, I want to replace EPCS16 (2MB) with W25Q128 (16MB) - for both size and cost reasons. Is ...

flash intel-fpga quartus configuration

asked Nov 28 '18 at 7:05

Anonymous

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302 views

Word alignment / bitslip in LVDS Receiver

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...

intel-fpga lvds

asked Nov 15 '18 at 9:25

SMS

83 bronze badges

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161 views

How to compare a re-writable 4 bit value to a given 4 bit input in Verilog?

The goal of this project to design a computational lock alarm in Verilog to be run on an Altera board (note on the board 0 is actually ON and 1 is OFF). Based on the design criteria I created a state ...

verilog intel-fpga hdl

asked Nov 11 '18 at 23:31

Akila Kavisinghe

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1answer

40 views

Is it possible to power down all the PLLs and VCO of a MAX 10 Device?

We are developing a board in which we would like not to use the analog features, like PLL, VCO and ADCs of a MAX10. UG-M10CLKPLL par. 2.3.6 states : "The only time that the VCO is completely disabled ...

intel-fpga pll vco max10

asked Oct 31 '18 at 13:57

MRigh

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0answers

47 views

Two-Terminal Passive Analog Component Tester Using the DE1-SoC Development Board

I am having hard time understanding this problem. I have to draw a Level 1 block diagram for this system. I really appreciated it if somebody can help me. I am new to DE1-Soc. use the Intel DE1-SoC ...

microcontroller embedded intel-fpga intel

asked Oct 28 '18 at 19:19

dhruv

133 bronze badges

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1answer

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How to have an in-system check in an FPGA based system that it has been reset?

I have a system based on Altera's MAX10 device that is doing the following tasks: receives the data and stores it on an on-chip flash memory only once. reads all the data from on-chip flash, stores ...

vhdl verilog intel-fpga hdl programmable-logic

asked Oct 19 '18 at 10:56

SMS

83 bronze badges

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vote

1answer

322 views

I2S output in VHDL

I am making an I2S output in VHDL for a project. This is my first project using VHDL and the problem may be my basic VHDL understanding. This is my code: ...

vhdl intel-fpga i2s

asked Oct 8 '18 at 17:49

keffe

1271 silver badge9 bronze badges

3

votes

1answer

302 views

Altera Cyclone II Quartus II JTAG Programming Error

I'm trying to program a Cyclone II I bought here using Quartus II 13.0sp1 on Arch Linux. I'm trying to program it with a very simple Verilog program with three inputs and two outputs and a few simple ...

fpga intel-fpga jtag quartus cyclone

asked Oct 5 '18 at 4:07

Chris Loonam

1469 bronze badges

2

votes

1answer

456 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...

fpga intel-fpga timing-analysis quartus sdc

asked Oct 1 '18 at 14:29

fhw72

1112 bronze badges

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1answer

116 views

Altera Cyclone IV clock-to-output delay

Trying to find what is the clock-to-output delay for registers inside EP4CE6E22C6. Have looked through the 3 Cyclone IV handbooks searching by delay but have not found any values specified. All the ...

flipflop delay intel-fpga

asked Sep 23 '18 at 15:11

axk

4134 silver badges16 bronze badges

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vote

1answer

261 views

Altera Cyclone IV PLL: What limits the available multiplication/division factor values

Altera Cyclone IV EP4CE6E22 with a 50 MHz input clock. I want to get 24 MHz out of the ALTPLL megafunction. The requested multiplication/division settings are 12/25 but actual settings turn out to be ...

intel-fpga pll

asked Sep 13 '18 at 21:05

axk

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1answer

113 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...

fpga verilog intel-fpga pll cyclone

asked Aug 29 '18 at 2:21

thebionicandroid

83 bronze badges

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1answer

113 views

Intel max 10 dimensions - datasheet & BSDL mismatch

TL;DR: The BSD file from Intel doesn't match the datasheet. What are the right dimensions? BSD: https://www.intel.com/content/dam/altera-www/global/en_US/others/support/devices/bsdl/10M02SCM153.bsd ...

eagle intel-fpga packages dimensions max10

asked Aug 28 '18 at 6:41

Eggi

589 bronze badges

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1answer

187 views

Quartus II selected a signal as a clock in combinational circuit

...

vhdl clock intel-fpga quartus

asked Aug 26 '18 at 13:34

Hassan Ibrahim

133 bronze badges

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1answer

389 views

How can I connect a USB keyboard to a DE1-SoC?

I recently got a DE1-SoC development board from Intel and I wanted to use it to instantiate a computer design I created while following along the Nand2Tetris course on Coursera. Unfortunately, this ...

usb fpga intel-fpga

asked Aug 25 '18 at 19:44

Guacho Perez

1052 bronze badges

-2

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1answer

141 views

Error (10327): VHDL error at clkdivider.vhd(27): can't determine definition of operator “”not“” — found 0 possible definitions

I am still a beginner and I keep getting this error, can anyone help pls? ...

vhdl intel-fpga quartus

asked Aug 3 '18 at 19:54

Ahmad Al-Sayed

42 bronze badges

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votes

1answer

107 views

Intel Altera MAX 10 DEV KIT Interface - Can a RS232 6 pin PMOD module by Digilent be used seamlessly with MAX 10 for PC-FPGA UART communication?

I am planning to either purchase a MAX 10 or a DE2-115 dev kit to implement communication via both ethernet and RS-232. DE2-115 has both ports soldered onto the board, but MAX-10 has 2 ethernet ports ...

rs232 intel-fpga intel max10

asked Jul 29 '18 at 17:01

Sid Mahapatra

11 bronze badge

1

vote

1answer

75 views

How does FPGA knows the configuraton file is present in Flash memory during bootup?

Which areas in flash memory are scanned during bootup to make sure that there is configuration file present in the external flash memory?

fpga intel-fpga

asked Jul 25 '18 at 12:42

Rakhil Pv

62 bronze badges

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1answer

297 views

Problem FIFO in the implementation (VHDL)

I was working in that for the past five days and I don't know what happened. I must implement a FIFO to send some information, I attach the FIFO that I use. As you can see in the code, this FIFO using ...

fpga vhdl intel-fpga fifo

asked Jul 19 '18 at 15:01

Jairo Mejia

31 bronze badge

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273 views

How to #include files in other folders in Eclipse IDE?

Here is the directory structure of a project I have downloaded: The problem is that when I compile I keep getting fatal error message that say that the specific header file does not exist. For ...

intel-fpga eclipse nios-ii

asked Jul 9 '18 at 19:53

quantum231

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Can Nios II read addresses in increments of 1 or only increments of 4?

There is some confusion here. I think that the Nios II having 32 bit data bus. Therefore, it is not capable of individual byte addressing. Therefore, the address bus increases as 0, 4, 8 e.t.c and not ...

intel-fpga nios-ii

asked Jun 21 '18 at 19:24

quantum231

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1answer

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register enable line usage in `case` block (verilog synthesis for altera cpld)

I have the following in a verilog design aimed at an altera CPLD (currently targeting EPM240, although the target device isn't set in stone): ...

verilog intel-fpga programmable-logic quartus

asked Jun 19 '18 at 21:30

Jules

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104 views

What is the minimal schematic (needed capactiors/resistors) to use FPGA Altera Cyclone 4 EP4CE6E22C8N? [closed]

I can't find any information about how wire the Cyclone 4 FPGA. I do not want to use development boards.

fpga wiring intel-fpga cyclone

asked Jun 6 '18 at 22:08

Alpha0

82 bronze badges

3

votes

1answer

316 views

VHDL - Subtype or type has null range

What is the meaning of the following warning (raised by Quartus)? ...

fpga vhdl quartus intel-fpga

asked May 31 '18 at 23:19

Jet Blue

4974 silver badges16 bronze badges

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1answer

342 views

MAX10 .pof file issue, quartus II and usb blaster

After a MAX10 board revision. When programming the MAX10 with .pof, the MAX10 board do not start when power-on or after .pof programming is completed. However, normal operation is achieved when ...

fpga intel-fpga programmable-logic quartus max10

asked May 27 '18 at 17:41

ggadde29

305 bronze badges

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1answer

370 views

How does one read a FIFO outside Qsys system using Nios II?

There is a FIFO block that has Avalon interface compatible with Qsys that can be used in Qsys systems. However, in my case there is an external block that generates data that is to be read by a Nios ...

intel-fpga nios-ii

asked May 19 '18 at 12:15

quantum231

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1answer

60 views

Nios 2 softcore IP

The SOPC board contains an Altera Stratix Processor, but the description mentions use of an Alteras NIOS II soft core IP. If its a soft core then why are we using a Stratix processor. PIC from: ...

fpga intel-fpga

asked Apr 25 '18 at 3:00

Siddharth

249 bronze badges

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1answer

91 views

Incomprehensible FPGA error

I try and upload my design, which worked previously, using quartus prime 17.1 to an Altera DE2-115. It fails like this: ...

intel-fpga

asked Apr 22 '18 at 1:24

Niklas Rosencrantz

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