Newest 'intel-fpga' Questions

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Generating error condition randomly inside a digital design inside FPGA

In order to aid in testing of the design, it is required that we put it into a "debug mode" whereby specific type of error conditions will occur at random intervals. We must then monitor the ...

asked Jun 16 at 21:27

Quantum0xE7

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How do you select pin functions on an EPM7128 CPLD?

I have some old Altera MAX EPM7128SLC84-15N CPLDs kicking around that I want to use to interface with 5v TTL logic. If you look at the pinout, some of the pins have more than one function (eg. Pin 2 ...

intel-fpga programmable-logic quartus

asked May 24 at 16:03

santonel

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FPGA Timing Constrain Problem

I am using the Cyclone V DE1-SoC in transferring data between HPS and ...

verilog intel-fpga fifo

asked May 16 at 11:05

johnny2231

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Error while building project in Quartus with Eclipse tool

I'm pretty new to the forum so if something is wrong with the question, sorry in advance. Currently, I'm working on a free project for school. My teammates and I decided to make a 'drawing glove'. ...

vhdl intel-fpga quartus eclipse

asked May 6 at 13:11

Arie Hoekstra

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7answers

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What do HDLs compile/synthesize to?

I'm a software engineer. As a programmer, I have an understanding of what my compiler does for me because I've manually written a close textual representation of what it outputs (e.g. assembly). For ...

fpga simulation intel-fpga compiler

asked May 4 at 22:59

Jake

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Interface mpu6050 with de2-115 board i2c

I'm currently working on a project for school. My teammates and I want to make a magic glove, that can draw on a VGA monitor with data from an accelerometer and gyrosensor. Therefore we are using a ...

vhdl embedded intel-fpga quartus

asked Apr 28 at 20:10

Arie Hoekstra

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What is the easiest way to simulate and experiment with FPGA using simulated external DDR3?

For a computer architecture school project I have to implement an algorithm in verilog, such design have to input and output a VERY large ammount of data that wouldn't fit in on-chip memory, hence I ...

intel-fpga quartus modelsim ddr3 nios-ii

asked Apr 27 at 1:33

sujeto1

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What are <device_name>@<device_index> to quartus_pgm?

I am trying to download the firmware of a MAX 10 FPGA with the "examine" operation. The help for the command line interface quartus_pgm to Quartus Prime says ...

fpga intel-fpga jtag programmer quartus

asked Apr 26 at 8:19

nalzok

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Access elements randomly in RAM based FIFO VHDL FPGA

The thing is: new data is being generated every "time step" that can be few clock cycles. So I want to store the data generated for few time steps in a "buffer". The data must be stored like in a ...

fpga vhdl intel-fpga ram

asked Apr 21 at 14:27

Fabio

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How to use array in Verilog actually?

I found that inVerilog, the array can only be declared in reg. And I found that it seems ...

verilog intel-fpga

asked Mar 30 at 14:12

johnny2231

51 bronze badge

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18 views

Multiplexer Simulation failed in Quartus II Web Edition 15.0

I'm currently working on some assignment for digital electronics. Before this, as in , before I reformat my laptop, everything works just fine. After that, After i reinstall Quartus II, the same ...

simulation multiplexer intel-fpga quartus vhf

asked Mar 28 at 3:02

nelson wong

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48 views

Present two images side by side on the VGA screen from FPGA

Im trying to get a clue how to present two images on the screen using VGA. I using Altera Cyclone 2 DE2 and VGA, I have already working vga sync driver for 640*480 res: ...

fpga verilog intel-fpga vga

asked Mar 26 at 10:57

Michael Astahov

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Cyclone III FPGA 3.3V LVTTL output rise and fall time restoration at 25MHz

I am using this signal to drive MD1822 mosfet driver to get high voltage pulses but fpga output rise time and fall time almost 40nS and underdamped I can not get good pulses. How can i improve this? I ...

circuit-analysis pcb fpga intel-fpga cyclone

asked Mar 24 at 21:32

Ahmet Atcı

12 bronze badges

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vote

2answers

89 views

Variable Bit shift within 1 Clock Cycle (Verilog)

I have a 64-bit register that I would like to right shift n times, with 0<=n<=64, implemented as such always_ff data[63:0] <= (data >> n); I ...

fpga verilog intel-fpga

asked Feb 27 at 21:28

Rudy Montoya

212 bronze badges

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vote

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55 views

How can i export synthesized netlist from Quartus 2?

I need to get a netlist that creates by synthesis and optimization from different hdl languages in Quartus 2. I need a netlist in basic logic. Rtl viewer shows me something similar, but i need it in ...

vhdl intel-fpga quartus

asked Jan 6 at 14:29

Timofey Bolgarin

112 bronze badges

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vote

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77 views

Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...

fpga verilog intel-fpga quartus

asked Dec 14 '19 at 23:26

user3818491

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UART not fast enough for debug purpose, what alternatives exist?

This problem is related with debugging an FPGA design implemented in Intel/Altera FPGA. A custom debug mechanism has been introduced into the design. This new part of the design writes into a FIFO ...

uart intel-fpga debugging jtag

asked Dec 5 '19 at 19:44

quantum231

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PIN Placement Errors In Quartus

So I am writing a simple blinking LED Verilog code that will be run on a Cyclone10 LP (Device is called 10CL025YU256I7G) and will be tested on a Cyclone 10 Evaluation Kit (6XX-44504R-0D) All code is ...

fpga verilog intel-fpga pinout quartus

asked Nov 27 '19 at 18:31

Coder Motor

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Setting Pin Assignments For Quartus

So I have written a simple Verilog module which works well in the ModelSim emulator. I would like to now program my Cyclone 10 Dev board to perform this simple task, but I need to set up the pin ...

fpga pins intel-fpga quartus

asked Nov 26 '19 at 21:47

Coder Motor

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109 views

Raw programming of an Altera FPGA

I have an Altera Cyclone IV FPGA (for ie) and my question is: is it possible a raw programming of the FPGA? Is it possible to set "manually" the gates for making experiments? Thank you

digital-logic fpga programming intel-fpga

asked Oct 21 '19 at 10:19

rikicecchi

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Can the altera_virtual_jtag be used to store critical design information for read out?

Can critical design information like design version number, compilation date e.t.c be stored inside the FPGA and be read out via JTAG while using the altera_virtual_jtag? I assume that the ...

intel-fpga debugging jtag

asked Oct 8 '19 at 21:33

quantum231

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28 views

How to initialize/load Intel HBM memory in simulation

I am trying to simulate the Intel HBM example design using ModelSim. Is there a way to initialize/load the HBM memory with some data before the simulation? If so, how can we do it?

intel-fpga quartus

asked Oct 8 '19 at 14:52

Shreyas Kolala Venkataramanaia

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2answers

75 views

dual purpose pins on max 10 fpga

I am breaking into the world of FPGA development at my internship for an aerospace company. I keep coming across the term "Dual-Purpose Pin" in the documentation for the Max 10 family of FPGA devices. ...

fpga intel-fpga max10

asked Sep 25 '19 at 20:48

Hannah Did

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22 views

EP53F8QI Short to GND fault

We have a design with an EP53F8QI that multiple ICs have been burned both at room temperature and +80 °.C. We are using it to create a +3.3V and on fault we have found that the +3.3V supply is shorted ...

power-supply pcb-design voltage-regulator intel-fpga switching-regulator

asked Sep 12 '19 at 11:58

shmueld

363 bronze badges

0

votes

3answers

51 views

Measuring the external memory power consumption in FPGAs?

I am trying to get a power/energy breakdown of DDR3 and core logic. I used Quartus power analyzer tool to get the power estimates, but I am not sure whether it includes the power consumption of ...

power fpga intel-fpga quartus

asked Sep 2 '19 at 18:27

Shreyas Kv

31 bronze badge

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vote

1answer

127 views

Is it possible to add an existing IP variant to a Platform Designer/Qsys system through TCL?

I have a .ip file that contains a parameterized component which I'd like to use in my Qsys system. I can add the component via the GUI but I would like to be able to add it via TCL or another ...

intel-fpga quartus

asked Aug 21 '19 at 15:49

PlasticGlass

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44 views

Altera Cyclone IV Setting Impedance

I'm trying to learn how to implement a 3V LVTTL interface using a Cyclone IV E (EP4CE10) FPGA. However, I would like to ensure that the input/output impedances of the IO is at 50R. I see that it is ...

fpga impedance intel-fpga io

asked Aug 13 '19 at 13:13

Arnold Hucks

232 bronze badges

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VHDL: case when using constants constructs

I'm having some trouble with the following statement ...

fpga vhdl intel-fpga programmable-logic quartus

asked Aug 4 '19 at 21:13

diegogmx

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Register value is not updated inside always @ loop

I am relatively new to verilog, please help with this issue I am having. Attached is a snippet of the code I am working on. The issue I am facing is, the regs - del1 and del2 are not correctly ...

verilog intel-fpga

asked Jul 31 '19 at 18:22

Am1T

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What is purpose of exporting system using tcl scripts generated by Qsys?

To "Export" a Qsys system we merely need the .qsys file. Inside Qsys (now called Platform Designer) we have the option where we can export the system as a .tcl script. The options are the in the file ...

intel-fpga

asked Jul 30 '19 at 6:47

Quantum0xE7

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Is it possible to create a Qsys system with VHDL generics at its top level?

Some components in my Qsys system have test modes. These are controlled via generics on their top level. These components are currently in a Qsys system. In Qsys, I can click on them and change the ...

vhdl intel-fpga

asked Jul 29 '19 at 13:08

Quantum0xE7

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What is the difference between words and symbols in Qsys, how to know which one to use?

Qsys offers options to select address unit or address type. All I know is that my custom components shall write 32 or 64 bit data to a specific address and it is not byte addressable. How do I decide ...

intel-fpga

asked Jul 25 '19 at 8:42

Quantum0xE7

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Verifying custom Qsys component?

A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also. These copies ...

vhdl intel-fpga verification

asked Jul 23 '19 at 15:13

Quantum0xE7

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Verilog 'if' statement error

Why are LEDs on after executing this? LEDs on pattern is 1010: ...

fpga verilog intel-fpga if

asked Jul 17 '19 at 20:31

misha

132 bronze badges

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166 views

Intel FPGA equivalents of Xilinx IBUFDS Primitives?

Im trying to migrate an Design from using Xilinx primitives to Intel Altera FPGA. The original design uses the IBUFDS for the clock signals. ...

fpga xilinx intel-fpga buffer

asked Jun 19 '19 at 9:50

Bá Anh Đào

31 bronze badge

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votes

2answers

54 views

How can Qsys component configuration be accessed in software?

I'm designing a Qsys component which I want to be user-configurable. It has config parameters which are defined in the TCL file. For example, for a GPIO bank component I would write: ...

c intel-fpga quartus soc

asked Jun 16 '19 at 10:31

Dmitry Grigoryev

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vote

2answers

109 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...

fpga intel-fpga pll quartus

asked Jun 11 '19 at 8:03

Olupo

387 bronze badges

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131 views

LMS7002M: I & Q DATA formats from LIMESDR

Can any one tell me what is the data format of LMS7002m I & Q sample? Are they unsigned int or floating or double? how are they ? Also kindly anyone show me any hint of proof for their answer.... ...

intel-fpga sdr

asked Jun 4 '19 at 18:48

ARKARUP7304

11 bronze badge

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86 views

altera FPGA acting like OR gate when programed as AND gate

I'm new to altera fpga , I've bought development board based on EP4CE6E22 cyclon IV and tryed to program it with basic program in quartus environment ...

fpga intel-fpga quartus

asked Jun 1 '19 at 10:00

Ron Vaisman

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1answer

878 views

what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and ...

fpga vhdl intel-fpga virtex-series-fpga microsemi-fpga

asked May 31 '19 at 6:10

srihari

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Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...

fpga verilog intel-fpga register synthesis

asked Feb 17 '19 at 20:34

axk

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110 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...

fpga xilinx intel-fpga timing-analysis

asked Feb 17 '19 at 18:04

Sourabh Tapas

16411 bronze badges

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1answer

326 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...

fpga vhdl spi intel-fpga quartus

asked Feb 6 '19 at 13:26

SDwarfs

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122 views

How can I check if an IO pin is dead?

I've been playing around with I2C for a couple days now with a DE10-Nano dev board: I'm implementing an I2C master in CLaSH so that I can talk to the HDMI encoder chip, but for now I'm talking to an ...

fpga gpio pins intel-fpga

asked Feb 6 '19 at 8:59

Cactus

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What's wrong with this schematic for powering up Cyclone IV FPGA?

I have followed all the guide lines for powering up the Cyclone IV. However, the 3.3v Regulator is heating too much and also the Cyclone IV FPGA. What's wrong with my schematic? Is there a problem in ...

fpga intel-fpga cyclone

asked Jan 16 '19 at 14:00

Alpha0

132 bronze badges

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39 views

Altera FlipFlop stuck at GND

I'm trying to make a counter that counts: 0,1,2,3,4,5 I need this for a frequency divider of 6 So I made this table: From this I get: J0= 1 K0= 1 J1 = NOT Q0 AND Q1 K1 = Q1 J2 = Q1 AND Q2 K2 =...

simulation flipflop counter intel-fpga

asked Dec 31 '18 at 20:13

Fox Alex

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Identify valid FPGA configuration image in serial flash device?

How can I know if there's valid FPGA configuration image in the specific location of the serial configuration device before I perform reconfiguration and experience successful or faulty attempt? ...

intel-fpga cyclone

asked Dec 25 '18 at 10:27

Anonymous

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104 views

can't send characters using fpga cyclone iv

I'm trying to connect my FPGA Cylone IV (CoreEP4CE6) with Raspberry Pi 3 for communication through UART. The process (uart_rx) for receiving data is working fine, however, when I place another process ...

fpga uart intel-fpga

asked Dec 20 '18 at 18:54

Alpha0

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374 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...

fpga intel-fpga quartus intel max10

asked Dec 18 '18 at 19:42

quantum231

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1

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2answers

609 views

Altera has created EPCS and EPCQ devices, can only these be used to store FPGA configuration data?

FPGA configuration data must be stored in external non-volatile memory. Can we use just any flash memory or only specific types? What about EEPROMs or any other nonvolatile memory device? Edit: I am ...

fpga intel-fpga configuration intel

asked Dec 16 '18 at 17:18

quantum231

8,18617 gold badges69 silver badges146 bronze badges

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