Questions tagged [intel-fpga]
A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).
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Intel De1-SoC VGA controller in VHDL
I have implemented a VGA controller in VHDL using the timing specifications for a 600x480 monitor as described in the attached photos. The module takes in a 50MHz clock and is supposed to draw a ...
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Improve Quartus partial compile or recompile time
I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. ...
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Is it possible to add an existing IP variant to a Platform Designer/Qsys system through TCL?
I have a .ip file that contains a parameterized component which I'd like to use in my Qsys system. I can add the component via the GUI but I would like to be able to add it via TCL or another ...
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What is the easiest way to replace a design inside an Intel Cyclone SoC? [closed]
I would like to integrate my VHDL submodule to the FPGA fabric of an Intel Cyclone SoC and make it communicating with an App on its Linux.
There is lot of documentation on the internet but I am not ...
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Illegal bus range or name for logic function for instance "instMyAdder" of type 4 Bit Adder
I am using QuartusII for designing a Four bit ripple carry adder.
I keep getting this error:
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Output waveform of TCS3200
I am trying to use TCS3200 color sensor for my project with De0 nano FPGA board. The output of TCS3200 is a square waveform and i am confused how to use that waveform for a particular task.
I searched ...
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How to create on-board USB blaster for Intel FPGAs?
Intel/Altera FPGA development boards only require a USB cable to configure the FPGAs. There is no need to buy a byte blaster. How is the USB blaster implemented on these boards, is this method/design ...
CommunityBot
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How effective is the Intel video Frame Buffer core when storing in memory?
The Intel Video and Image Processing (VIP) Suite IP has a Video Frame Buffer (VFB) core, named Frame Buffer II IP Core, that can take streaming images on the Avalon-ST IF and save them into memory ...
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JTAG Communication Failure in ARRIA 10 FPGA
Has anyone bricked an ARRIA 10 FGPA (or any FPGA) and successfully unbricked it?
I have an ARRIA 10 that uses an EPCQ-L256 external memory to configure the FPGA. When I uploaded some code, I think I ...
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How to convert from Avalon-MM 128-bit to 48-bit IF?
Some Intel FPGA DDR memory controller only offers 48-bit Avalon-MM IF, when implementing the hard External Memory IF (EMIF) controller.
For connection from a 128-bit Avalon-MM IF, it is therefore ...
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How to make Quartus generated programming files for two different but pin compatible FPGAs?
On most porotype boards there is a smaller FPGA which does fit the design but cannot fit a lot of signal tap tap to aid in debugging. Thus, I got a few boards modified with the largest pin compatible ...
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Verilog truth tables [closed]
I am starting in verilog, I am very confused with truth tables, how do I do it in verilog using "if-else", my instructor introduced us to the topic with the following example:
after seeing ...
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Quartus cannot place PLL
I am using Intel/Altera Cyclone V 5CSEMA4U23C6 on DE0-nano-SoC board.
My design is using one PLL that I added a while ago in Platform Designer.
Though it isn't explicitly calling Fractional PLL based ...
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Quartus II: Suppress warnings by Verilog module
In my FPGA project I use the Quartus II PCIe megafunction. The number of warning messages this Altera library module produces baffles me.
Is there a way to have Quartus II suppress all the warnings ...
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Is it possible to write an "interconnect" in VHDL by hand?
An interconnect connects one or more masters to one or more slaves in a sort of system on chip design. In such a scenario there would be a master containing a standard bus like Avalon-MM, AMBA AXI, ...
Null♦
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Implement glDrawArrays function in FPGA [duplicate]
I need to implement glDrawArrays function in FPGA.
I understand it's part of the OpenGL library.
I'm trying to get to its source code to figure out what it contains.
Does anyone know of a tool that ...
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How to use command-line to cause Qsys to generate only synthesis or only simulation files?
In my project there are several Qsys files. Some of them are for synthesis but most are for testbench. When changes are made to source code, I usually just run generate Qsys system from the GUI and ...
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Manually override Quartus Fitter/Pin Assignment constraints
I have a design that I want to synthesize for / upload to a Max 10 FPGA.
One of the inputs goes to a PLL. Quartus now claims, that the neighbouring IO pin is too close to the PLL input pin and won't ...
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Unexpected change when reading input signals in a VHDL Finite State Machine
I implemented a FSM in vhdl using two processes;
A sync process for state transition
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Is there a reason to have different files or entities with same name in FPGA project?
In FPGA projects, the files are usually named after the entity they contain. I am trying to figure out these things:
Is it a good practice to have multiple entities in same file?
What if entity and ...
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What value to use for Byte Count field in PCI Express (PCIe) IO read completion?
In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read.
A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this ...
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How to read firmware from Altera's FPGA (Cyclone IV) with USB Blaster?
I'm starting to investigate Altera's Cyclone IV FPGA to use in my projects. Now I borrowed from neighboring company a real device with USB Baster Rev.C. I'd try to use one instead of evaluation board ...
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MAX10 Flash and separating NIOS Firmware from FPGA config for remote updates
I'm trying to get to grips with how MAX10 memories work, especially if you want to split firmware and FPGA config into completely separate sections. I have read and reread the MAX memory guide, but I'...
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Can transceiver replace SPI, I2C and other "normal" methods for high speed data transfer between FPGAs? If so, how? [closed]
SPI, I2C and UART are some well known serial methods for data transfer between devices on the same PCB. However, they all have a data rate bottleneck which is significantly lower than Multi Gigabit ...
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How does Quartus pin planner know about voltage in each I/O bank?
It is possible to specify a range of I/O standard options in Quartus pin planner. I am trying to understand a few things:
How does Quartus know what voltage is supplied to each bank?
Why does Quartus ...
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Altera Cyclone II JTAG after AS Programming
I've been playing with FPGA(Cyclone II EP2C5T144C8) with Quartus II 13.0 WebEdition 64bit and Altera USB Blaster.
At first, I was using JTAG mode for programming FPGA into RAM. When I wanted to ...
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quartus signaltap not accurate?
I am using Quartus SignalTap to debug my FPGA design:
I always been persuaded SignalTap is not accurate !!
This is what i found:
I monitor the reset signal with SignalTap :Reset toggles around, ...
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Maximum rate between ADC-FPGA link for Igloo 2 vs Max 10
An ADC has a source synchronous output interface and is to be interfaced with an FPGA. The ADC can communicate using single ended CMOS, DDR CMOS and DDR LVDS. How do I know what is the fastest rate ...
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clkp and clkn inputs in Intel MAX10 FPGAs
The clkp and clkn can be used to insert a differential clock signal into the Intel MAX10 FPGA.
Intel MAX10 FPGA Datasheet
My question is, can we have 2 separate independent single ended clock signals ...
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LCD 16x2 (I2C) with FPGA (Altera Cyclone II)
this is the question, a few days ago I bought the FPGA Cyclone II development board from altera (I am a big fan of arduino and I have a variety of modules and others) at first I started studying ...
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What is the FPGA with the highest LEs / $?
Well, what is the FPGA with more Logic Elements per Dollar? I already tried to search some sites but the filters for the products do not include that option.
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How to implement neural network using FPGA? [closed]
I want to design neural networks using FPGAs and make neuromorphic chip. Is there a tutorial or course to learn how to do that and to implement neural network using FPGA especially for evaluating the ...
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Why is my FPGA clock so slow
To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this:
<...
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Pipelined designs with outputs in differentes delay clocks
I have a pipelined design that ends in 13 clock cycles when the input value is not close to zero, but when the input is close to zero, the design only needs about 4 clock cycles, because of all the ...
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Getting started with Altera FPGAs
I am getting a Cyclone II-based Altera DE1 FPGA board to experiment with. I know a lot about programming, a bit about electronics and very little about FPGAs. What books or other resources would you ...
Null♦
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Is there a "universal" JTAG controller peripheral?
JTAG can be used to read/write data from/to FPGAs. I want to know if there is any device with an interpreter that can be used with user written STAPL files. Basically the peripheral shall wiggle the ...
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Altera Quartus detects 2 CPLD devices instead of 1
I try to program a design I made using 5M40ZE64C5N CPLD. The software side was successful and I got a .pof file without any critical warnings or errors. The problem occurs when I try to upload the ...
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How to transfer blocks of data into FPGA to aid in testing?
How can one transfer data from PC to FPGA and read back result for test purpose where the data must not get corrupted i.e resend if data integrity was lost or use some other error recovery mechanism. ...
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What timing constrains would I need to set for a handshake based clock transfer
I want to transfer a couple of bits between two clocks, so I build a small handshake logic, but my timing analyzer shows me some violations.
Setup/hold violations and in addition some rule check ...
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Help me debug these VHDL errors please
There are just 6 errors now
Can't trace errors in this VHDL
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What is purpose of exporting system using tcl scripts generated by Qsys?
To "Export" a Qsys system we merely need the .qsys file.
Inside Qsys (now called Platform Designer) we have the option where we can export the system as a .tcl script. The options are the in the file ...
CommunityBot
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FPGA - synchronise “very close” clock from signal
This is more of a learning question, I can solve the problem but it would be good to know how to do it - can a clock be reconstructed from a signal, and is it easier when the frequency of the clock is ...
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How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave? [duplicate]
I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
CommunityBot
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Altera Quartus "Warning (18236): Number of processors has not been specified...", how to suppress?
My Altera Quartus builds show this warning...
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PCI-Express and FPGA Development Boards [closed]
I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
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Verilog design to display character using "16x2 Character Display" IP from Quartus IP Library
I was trying to display a single character on 16x2 display. I created simple Verilog design for "Altera Cyclone V Development Kit". In the project I used "16x2 Character Display" ...
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Possible to use Segger J-Link with Intel Quartus to flash FPGA?
Does anybody know if it's possible to use a Segger J-Link with Intel Quartus to flash an FPGA?
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How can Quartus Prime System Console be used to read/write a whole file?
I want to find a way to read/write whole file from/to my Intel FPGA design. The file being written provides data to be processed and the file being read shall contain the results of the processing ...
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Raw programming of an Altera FPGA
I have an Altera Cyclone IV FPGA (for ie) and my question is: is it possible a raw programming of the FPGA?
Is it possible to set "manually" the gates for making experiments?
Thank you
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Audio Demos on DE10 Standard not Working
I bought the Terasic DE10 Standard and am having issues trying to run the demos related to audio.
I am trying to run the two demos, DE10_Standard_Audio, and DE10_Standard_i2sound, while connecting ...
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