Stack Exchange Network

Stack Exchange network consists of 175 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange

Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

0
votes
1answer
242 views

Help with Flash memory to GPIO pins on FPGA dev board

Been trying to access the FLASH memory on this DE1 dev board, but having no luck. I'm using this to interface with a Super Nintendo system, and I'm trying to read a small test ROM file stored on the ...
1
vote
0answers
33 views

Are there any methods to simulate time-base power usage of a Xilinx/Altera FPGA?

Old versions of Xilinx ISE suite got XPower tool which had -tb option to simulate time-based power usage of an FPGA by an input .vcd file like this: ...
0
votes
2answers
463 views

Altera MAX10 CPLD initialization IO state

I'm designing a pcb with an Altera MAX10 (10M02) CPLD used to do, amongst other things, bus arbitration between several memory chips (one /CS per chip). All the memory chip are on same bus so only ...
0
votes
1answer
370 views

How to see the content of the SDRAM in my DE1-SOC while running (JTAG Altera cable)?

I have made a simple design in Quartus Prime, in verilog code, not using megawizard, but directly accessing the pins of the SDRAM. I am saving 2 x 16 bits binary numbers on 3 of the 4 banks of the ...
0
votes
1answer
1k views

Altera equivalent of the Xilinx Zynq UltraScale+ MPSoC [closed]

I'm new the the FPGA world. I was wondering if anybody could tell me the Altera equivalent of the Xilinx Zynq UltraScale+ MPSoC? I'm looking to buy a development board but it needs to be from Altera....
0
votes
1answer
592 views

Failing to program Cyclone IV GX device via JTAG

I just got the aforementioned device and, upon writing a simple program (it compiles) and going into Programmer, when I try to program the device with the .sof file, I see is ...
0
votes
1answer
368 views

Replacing an FT2232 chip with a custom microcontroller?

I want to make a circuit board having the capability of configuring (not sure if this is the correct term, but burning a VHDL design (svf, pof file generated by Quartus)) into Altera CPLDs and FPGAs ...
0
votes
1answer
124 views

nrf24l01 transceiver on altera board de2-115 [closed]

I'm trying to use the nrf24l01 transceiver on altera board de2-115. I would like to send a signal from the altera board using this spi module to another spi module and use the spi module on the ...
1
vote
1answer
152 views

FPGA CDMA tracking

Consider a CDMA transmitter using DSSS that is in motion with respect to the receiver (satellite). Suppose the PN code is synchronized to within one chip, i.e. acquisition has been completed. How is ...
-1
votes
1answer
85 views

Any ideas for a hardware to do AM and FM modulation? [closed]

I'm trying to do some signal processing (AM/FM Modulation) for signals from 0 - 60kHz. Any recommendations for hardware? Preferably something I can use MATLAB with (or Python) as I'll most likely be ...
0
votes
1answer
4k views

Vhdl error 10327 - can't determine definition of operator “”&“” — found 0 possible definitions

I'm adjusting some vhdl code an am getting the following error: Error (10327): VHDL error at myfile.vhd(87): can't determine definition of operator ""&"" -- found 0 possible definitions The ...
0
votes
1answer
139 views

How to connect to this FPGA board?

I got this board from ebay, seemed to be a cheap deal. It is decent product from what I can say at this time. The question is, what is the most appropriate way to connect a daughter board to this ...
0
votes
1answer
188 views

Unexpected behaviour in Altera clock crossing FIFO

As far as I am aware, in a FIFO as we keep reading it will eventually become empty i.e no more data inside and its output shall become 0x0. If we keep reading it after it has become empty, we shall ...
0
votes
1answer
712 views

Output CLOCK signal to GPIO pin of CYCLONE IV E

I am new to FPGA and I am trying to send a CLOCK signal as an output of a GPIO pin of an Altera Cyclone IV E. I first made a program: ...
0
votes
1answer
89 views

Is there a method to provide physical stimulus to design inside FPGA like we do in VHDL test bench?

Basically I need to find out if there is a feature that allows one to enter stimulus into an FPGA without using things like signal generators. Altera FPGAs have a feature implemented via Quartus ...
3
votes
1answer
164 views

Inferring RAM ALTERA from vhdl of HDL CODER

I've generated vhdl from Simple port RAM and Dual port RAM in simulink and I tried to synthesize with Quartus 14 and 16 on Arria V and 10. The option to allow RAM for any size is ON but I don't ...
0
votes
2answers
179 views

How do I put a high-speed pulse through a digital logic chip?

I have a system which uses a 3ns pulse to trigger some downstream circuitry. When I hook up the trigger generating circuit directly to the downstream circuit, everything works fine. When I route the ...
-1
votes
2answers
275 views

Can I shield noise inside an FPGA with a ground plane?

I am routing some external signals through an Altera FPGA and noise is coupling into the signals from something else in the FPGA. I have an idea to physically distance the signal route from the rest ...
1
vote
1answer
235 views

Driving dots (periods) next to digits on Terasic DE1

I have a Terasic DE1, and have imported the maker's pinout file, which contains pin assignments for HEX digits. However, I noticed that each HEX digit has a dot next to it and I cannot find any pin ...
0
votes
2answers
729 views

How to know power consumption of core FPGA

I am using a DE0-Nano board in my project. It has an Altera Cyclone IV E FPGA chip in it plus other components such as ADC, RAM, etc. When connected to a USB power supply, the DE0-Nano requires around ...
0
votes
1answer
592 views

Altera FPGA Reset System

I having a hard time understanding the best way to setup a NIOS II system with external code and the resets and clocks. One of the reasons why I'd like to figure this out is the JTAG system really ...
2
votes
2answers
712 views

How is a signal physically routed in an FPGA?

I've looked at this similar question, but it does not provide the answer I'm looking for. The documents from Xilinx also confuse me and the diagram provided in the Implementation view of the Xilinx ...
1
vote
5answers
2k views

FPGA BRAM initialization

I need to create a lot of BRAM blocks in my (Altera) design. Each one has unique memory contents, determined a priori using an algorithm. Before, I was setting a parameter for each BRAM cell to read ...
2
votes
1answer
242 views

Why some MAX 10 chips don't support ADC while the datasheet says they do?

I'm using an Altera MAX 10 chip 10M50SCE144C8G. I want to use its ADC. In datasheet, it says that this chip has a "Single ADC that supports 1 dedicated analog input pin and 8 dual-function pins". ...
0
votes
0answers
207 views

Not port with test bench vhdl, altera quartus prime

I wanted to test this simple VHDL model ...
3
votes
2answers
3k views

Configure (upload bitstream) to MAX10 without Altera tools using Linux

I am currently using the flash-based Altera MAX10 in designed attached to main processor which runs Linux on a custom board (the FPGA itself just implements a few peripherals; the processor running ...
0
votes
2answers
79 views

Is there a VHDL (or Quartus2-specific) compiler directive for disregarding certain lines of code for synthesis?

Is there a VHDL (or Quartus2-specific) compiler directive for disregarding certain lines of code for synthesis? I want to have certain signals going out for my simulation, but Quartus2 throws errors ...
0
votes
2answers
215 views

Adaptative Logic Module : Logic Element equivalence

I have implemented some circuitry with Quartus on a Cyclone 5 FPGA. This has be done for my master thesis. I have to justify wether the number of logic element used by my implementation is "expected" ...
1
vote
2answers
139 views

Signal alias for Altera SignalTap

In my experience, some signals disappear from SignalTap possible nodes because of optimization. I wanted to make aliases to several signals and tried using noprune so they will be available at ...
0
votes
1answer
912 views

Altera Quartus not creating symbol files

I'm looking to create a schematic block from a vhdl file in Altera'a Quartus software. I've been using File->Create/Update->Create Symbol Files for Current file The file compiles okay and I get the ...
1
vote
1answer
62 views

Effective Capacitance of an FPGA board

I am currently designing a processor on an Altera DE0 Nano and found out that the power consumption of my design may be computed by this equation: P = C * V^2 * (a * f) where P is the power ...
1
vote
1answer
312 views

Altera FPGA Configuration using Flash

During my current PCB design using Altera FPGA, I happened to come across knowledge that Altera EPCS devices are to be used for FPGA configuration. After further research, I realized the same job can ...
2
votes
3answers
2k views

Why does Altera DE2-115 board GPIO expansion header contain 5V & 3.3V power but the IO standard has no 5V?

The altera DE2-115 board user manual section 4.8 page 47 describes the GPIO expansion header. It is clear that it has 3.3V and 5V power supply. However, it later says that "The voltage level of the I/...
0
votes
1answer
104 views

Nios II system generated by Qsys looks awful (All pin are at one side). Can we make it look better?

I have tried Quartus 16.0 and 14.1. Both of them generate Nios II system that looks very awful as shown in the figure below. Is there any way to make it look better like the previous version as shown ...
6
votes
2answers
1k views

Improve Quartus partial compile or recompile time

I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. ...
0
votes
1answer
2k views

Simulating RAM in modelsim - cannot find library

I have a design in Quartus that includes an (on chip) RAM module that was created using the altera mega wizard. The wizard warns me that to simulate i need to include the ...
3
votes
1answer
803 views

Best utillization of M9K memory in max10 or other altera fpga's

I've got a max10 with a nios processor built in my memory utillization on the part is: 414,198 / 562,176 ( 74 % ) but I've used up every M9K block on the FPGA. Here is a table for the utillization As ...
3
votes
1answer
940 views

Altera Cyclone II JTAG after AS Programming

I've been playing with FPGA(Cyclone II EP2C5T144C8) with Quartus II 13.0 WebEdition 64bit and Altera USB Blaster. At first, I was using JTAG mode for programming FPGA into RAM. When I wanted to ...
2
votes
1answer
6k views

Bus to wire in quartus

I sometimes run into a problem with altera's Quartus that I would like a better solution to. Sometimes I use the graphical interface for design and I have a bus that I would like to pull off just one ...
0
votes
0answers
159 views

Altera Quartus - structural architecture

I am relatively new to VHDL and I am supposed to use structural architecture and Altera Quartus on my assignments. But, I have noticed that the Unisim library is not compatible with Altera Quartus, so ...
1
vote
2answers
293 views

Altera Cyclone IV FPGA and jtag debugging

G'day All, Is there a method comparable to jtag debugging on a microcontroller (ATMEGA32) for the Cyclone IV family of FPGA? I am trying to debug my Verilog code so ideally I just want to be able to ...
0
votes
1answer
271 views

Altera Quartus. Technology Map Viewer looks different from expected

Recently, I've installed Altera Quartus 15.1 and now follow the "getting started" instructions, you can read it here. At the step: to see the resulting circuit go to Tools →Netlist Viewers →Technology ...
1
vote
1answer
164 views

What is configuration image zero and one?

Currently, I am working in Broadwell-DE based module design. In this circuit, There is an FPGA (p/n :10M02SCU169C8G ) Please see the configuration user guide added. ( ref page 14) https://www.altera....
2
votes
2answers
6k views

What the FPGA dev board to choose: Xilinx or Altera? [closed]

I'm very new to programmable logic world and have never worked with any HDL languages, but I certainly want to get started with FPGA. At the moment the goal is to develop/simulate simple 8bit CPU and ...
1
vote
1answer
148 views

Implementation of NIOS Softcore alongwith HDL modules on Aletra Cyclone IVGX

My question is not on 'how can' but 'if can'. So I believe people with sufficient experience on any FPGA family might be able to help me out here. Problem Statement: I need to model a very basic ...
0
votes
2answers
255 views

Simple LED FPGA Circuit

I am new to digital design, and have recently purchased a Bemicro MAX10 FPGA development board to help get my feet wet. I am trying to learn VHDL, and have downloaded a few PDFs to get me started. The ...
7
votes
2answers
4k views

Do I need to reset my FPGA design after startup?

I usually initialize state registers of my FSMs by specifying an initial value in my VHDL code, so that, I do not require a reset pulse after startup of the configured FPGA. The following example ...
-1
votes
1answer
122 views

Clock port and any other port of a register should not be driven by the same signal source

I get this Warning from Altera Design Assistant for the below: Clock port and any other port of a register should not be driven by the same signal source Critical Warning (308012): Node "App_Logic:...
0
votes
1answer
186 views

Altera Quartus Design Assistant Critical Warnings

I get a number of Critical Warnings with respect to lpm_ff and lpm_counter: Below are few: Rule A102: Register output should not drive its own control signal directly or through combinational ...
4
votes
2answers
2k views

Dual port RAM on Altera and Xilinx FPGA

I have always managed to synthesis a 256 x 32 bits dual-port RAM (not true dual port RAM) in Xilinx ISE with just 1 x 18K BRAM. The example code from here was used: ...