Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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Synthesizeable D Flip flop for FPGA

Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite. Starting with a simple D flip flop, I face the ...
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1answer
3k views

Illegal bus range or name for logic function for instance “instMyAdder” of type 4 Bit Adder

I am using QuartusII for designing a Four bit ripple carry adder. I keep getting this error: ...
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1answer
468 views

Design of carry chain on Cyclone IV

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "cin" goes high, signal starts to ...
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3answers
396 views

Use ancient Altera MAX II board in modern environment

Years ago (in 2004) my university got an Altera MAX-II devboard, but nobody used it. Now it's me who must teach students FPGA programming, but I still cannot get the board programmed. I faced the ...
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1answer
762 views

Verilog SPI module functioning in unpredicted ways

I am currently trying to implement a simple SPI Master module in Verilog using Quartus Prime Lite V15.1.0 Build 185 for compilation and Simulation Waveform Editor as my simulation tool. The module has ...
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2answers
1k views

How to make an .sof upload to an Altera Max10 stick [duplicate]

I have a Max10 dev board with a 10m08 chip on it. I made a simple counter to blink the LED's. My counters have asynchronous resets, and my asynchronous reset has a circuit to keep it low for two clock ...
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1answer
1k views

Altera Cyclone V: Timing issues with routing (interconnect)

I'm designing an application with an Altera Cyclone V SoC (5CSXFC6C6U23I7N) and interfacing ADCs and DACs at 250MS/s. In the meantime, the design complexity has increased a bit and now there are ...
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1answer
267 views

Cyclone V LVTTL GPIO Termination

On the DE1-SoC (from Terasic) schematic, I found 47 Ohm series resistors connected to GPIOs, they are using 3.3V VCCIO. The cyclone V datasheet show that no external termination is required as shown ...
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How can I set a delay in Verilog using a clock?

I'm trying to write an always block that will open a valve and then keep it open for a few seconds and then close it if needed. The valve opens when the input is 1 and it closes when it's zero. How ...
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1answer
2k views

how to set pin in verilog (atera)

I am beginner in Altera DE2-115. I am asked to make a project using Verilog language. My idea was connect an infrared sensor and if it is cut with something, a buzzer starts. The infra has 3 ...
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2answers
6k views

verilog error left-hand side of assignment must have a variable data type

I have a verilog as module I get the error Error (10137): Verilog HDL Procedural Assignment error object "result" on ...
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1answer
1k views

Active serial configuration flash (EPCS & EPCQ) vs normal SPI flash

Is there a difference between the serial configuration devices from Altera and any other SPI flash memories? I see Terasic uses S25FL256S in their development board instead of EPCQ256, so I wondered ...
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1answer
2k views

Loading and displaying on VGA monitor a Background image in DE2-115's SDRAM

I would like to load a background image which I currently have saved as a .bmp into the DE2-115's SDRAM. I would then like to display this background image on a VGA-monitor (640x480). I will then be ...
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1answer
11k views

How can I generate a 1 Hz clock from 50 MHz clock coming from an Altera board? [duplicate]

I have an Altera DE2 board that outputs a 50 MHz clock and I'm trying to write a verilog module that can bring it down to 1 Hz. How can I do this?
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3answers
956 views

Implementing an ADC Interface to connect to a FPGA

I want to implement an ADC Interface for an ADC - ADS 7230 (TI) in VHDL. I am not very familiar with ADCs to implement it in VHDL. I already have an ADC Interface for a 10 bit ADC (MAX 1030) and a ...
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1answer
573 views

Possible causes of dead cyclone IV on custom board

i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes: I am using 3.3V VCCIO for all IO banks. I misread the handbook and ...
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1answer
188 views

CycloneIV PCIe hard IP fixedclk_serdes generation

I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says ...
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1answer
113 views

Altera FPGA Pinout help [closed]

I recently bought an Altera FPGA Cyclone II board off of ebay, it says BAIXUN on the LCD display. It didnt come with any documentation. I'm trying to program the FPGA board but I have no idea what pin ...
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3k views

hexadecimal seven segment display verilog

I have a 4 bit output number as output. How can it be seen on seven segment display as hexadecimal number? I'm new and mentioning verilog. case example: ...
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2answers
602 views

usb interface for fpga & Nios

I need some advice: i want to connect an altera FPGA to a computer by USB interface. i want to avoid placing an microcontroller in my board.. i want to set a nios II to "talk" to the computer i only ...
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1answer
3k views

Help with resolving warning “inferring latch(es) for signal or variable ”..“, which holds its previous value in one or more paths through the process”

Below is the code for my branch unit implementation. This unit calculates the jump destination address and writes it into the PC register. There are a few different types of jumps, etc, standard ...
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1k views

Quartus/SignalTap: Is there an equivalent to Xilinx's ICON, VIO, ILA IP-Cores in Altera's SignalTap?

Xilinx offers an Integrated Logic Analyzer (ILA) / called ChipScope. Altera's Quartus II comes with SignalTap - an equivalent solution. As an advance user\$^1\$, I'm using ChipScope as pre-compiled ...
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2answers
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Quartus II - Can I include other files into a *.qsf file?

An Altera Quartus II project consists of one *.qpf and one or more *.qsf files. The qsf seems to be a TCL script like other EDA related settings and config files (e.g. xdc, sdc, ...). Is is possible ...
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1answer
2k views

CDC Synchonisation primitives for an Altera FPGA

I am working on my first non-trival FPGA design and finally have a need for Clock Domain Crossing (CDC). There are multiple resources (amongst others) which discuss various architectures for CDC and ...
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1answer
293 views

Nesting entities in VHDL (Altera Quartus)

I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU. The first part is composed of a FIFO buffer, Cache memory for ...
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1answer
149 views

Benefits of using Altera IP in FPGA designs?

I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
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2answers
169 views

How are FPGA's configured when operating independently?

I have a DE0 Altera board with a Cyclone III FPGA from my VHDL class, and I want to learn how to use it in an independent device. Right now I have a Raspberry Pi and wanted to try playing with using ...
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1answer
251 views

Does the altera ROM megafunction have a startup delay?

I'm trying to make a very simple single cycle CPU in VHDL. My machine code is stored in a ROM that was made by the Altera MegaWizard. The first word that is stored in this ROM is 0x1111. After writing ...
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1answer
297 views

VHDL code works well in ModelSim and strange behavior in Altera FPGA

I'm trying to understand a strange (for me) behavior of a simple VHDL code. I have realized a stupid code that works well in ModelSim and doesn't work in a real FPGA (Altera MAX 10). ...
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2answers
7k views

How to read firmware from Altera's FPGA (Cyclone IV) with USB Blaster?

I'm starting to investigate Altera's Cyclone IV FPGA to use in my projects. Now I borrowed from neighboring company a real device with USB Baster Rev.C. I'd try to use one instead of evaluation board ...
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Using GPIO in Altera

I'm trying to test the GPIO functionality of Altera (DE1, Cyclone II) with this simple program. If the GPIO_0[0] gets a high (1) signal, LEDG[0] will light up. If it receives a low (0) signal, LEDG[0]...
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1answer
788 views

Write an I2C code for Cyclone 2 architecture

I really need to I2C interface my FPGA with some slave device. I figured I could use the audio codec in my FPGA as a slave.I have gone through some codes from the internet for I2C. But I do not get ...
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3answers
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sine wave in FPGA

I am supposed to generate a sine wave in cyclone 2 altera? I get that I have to store the values in LUT or some memory. I think cyclone 2 uses a 4 input LUT. I am not sure how I should go on with the ...
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3answers
1k views

PCI-Express and FPGA Development Boards

I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
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2answers
1k views

Altera Clock + PLL

I am using an Altera devkit from terasic, DE0-CV. I am also new to the FPGA business. How to connect the onboard clock to the FPGA and use it with my design? As the clock is a 50 MHz one, surely I ...
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1answer
1k views

Altera's DRAM Controller with UniPHY

I am trying to port a design from Xilinx to Altera, and I have issues with the DRAM controller IP (for a Cyclone-V and a LPDDR2 mem). I have managed to generate the IP, but I don't understand which ...
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1answer
646 views

Using the ROM megafunction in VHDL code

I have created a ROM megafunction using the MegaWizard plug-in Manager. This created a new file which I named rom.vhd. My code: ...
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1answer
31 views

Node assigned to IOBANK

I'm working with an Altera FPGA. In the Pin Planner there is a choice in the combo box for a 1-bit inout node to be connected to an "IOBANK_n" (under "Location" row). I was expecting only "PIN_nn" are ...
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3answers
10k views

How to define a clock in Quartus II?

I have this piece of code here: ...
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2answers
1k views

FPGA SPI slave not working well

I'm tring to integrate a SPI Slave in VHDL (opencores) http://opencores.org/project,spi_master_slave the idea is to interface a Microcontroller and an FPGA I'm Using Quartus.. more info: ...
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1answer
813 views

Why does this Verilog code produce no output on my FPGA?

I am trying to learn Verilog on my own using the DE1-Soc and the Altera university program labs. I am on the very first lab and trying to make a 4 bit-wide two input multiplexer. I wrote this verilog ...
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2answers
1k views

Reading ADC using Altera DE2 Board (Beginner)

Question: Would it be possible and feasible for a beginner to use Verilog HDL and an Altera DE2 board to read input from a weight sensor's HX711 ADC (see below), and if so: What kind of data am I ...
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1answer
203 views

Why build errors when connecting timers in Quartus ii?

I use the Nios 2 IDE from Altera with the Altera DE2. I add a file Functions.c with code that needs a timer e.g. ...
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1answer
1k views

Simulating IP core (i.e ALT_FP_DIV) on Altera modelSim gives “z” (high impedance) as output

I'm trying to simulate (functional Test) a project that contains both my own codes and some instances of Altera Floating Point IP Core generated using MegaWizard on ModelSim. All the instantiated IP ...
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1answer
596 views

Can DE2-115 handle more than 3.3V on its GPIO

In my current project I want to connect some logic to Altera DE2-115 using 40-pin exapnsion header (JP5). Unfortunately, I can't ...
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1answer
3k views

How to install Altera USB master driver for Windows 8 (64 bit)?

I am trying to connect Altera Stratix 4 board with my PC in which Quartus 11.0 is per-installed. But my PC is not detecting USB JTAG connection from the board. What I am guessing is that, this ...
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2answers
2k views

Code to add two 4bit numbers in verilog doesn't work

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... ...
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1answer
402 views

reuse Cyclone IV fpga Pasive serial configuration pin for SPI

Can i reuse pins DATA0 & DCLK in my application as FPGA SPI interface after configuration (PS) has been completed ? This are the dual purpose pin options: if i set "use as Regular I/O" , i will ...
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1answer
170 views

Is it technically feasible to design a microchip that won't fail foreign characters? [closed]

I used to work as web developer and did the same part of the project for several decades: Making sure that our Scandinavian characters åäöÅÄÖ... will work. It was feasible and it did work, basically ...
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1answer
37 views

What's the order of the array generated by Verilog? Syntax

What is the correct interpretation between these two lines: wire[2:0] w = SW[17:15] = {SW[17], SW[16], SW[15]} wire[2:0] w = SW[17:15] = {SW[15], SW[16], SW[17]} When I call w[0] will I get SW[15] ...