Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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3answers
28k views

What is clock skew, and why can it be negative?

My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24): To ...
10
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4answers
23k views

Using both edges of a clock

I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here ...
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2answers
203 views

Cycle-Accurate Power Estimation for Altera Devices

I'll be doing some analysis which requires at least cycle-accurate power estimations. From what I gather, the PowerPlay tool only calculates total power consumption. I've also looked into Synplify, ...
2
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2answers
1k views

Merge a differential pair into one signal

I have an LVDS ADC connecting to an Altera Cyclone IV FPGA. The data pins come in 7 differential pair channels, for a total of 14 pins. Although each differential pair is physically 2 pins, my ...
4
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3answers
3k views

Altera optimisation: “Stuck at GND due to stuck port data_in”

I am compiling Verilog code with the Quartus II compiler, and it seems that almost all my code is being optimised away. The "compilation report" says that many of my registers are being removed during ...
3
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1answer
5k views

What's wrong with this 4-bit ALU?

I've put together a 4-bit ALU that seemed to perform correct in simulation but when downloaded to the board it is not behaving correctly. The operation OR behaves correctly while addition and AND are ...
1
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3answers
6k views

How to make Quartus II find the Altera DE2 board?

I use Quartus II web edition and using that driver my computer can find the card: And the card appears in the device manager so it indeed looks correct so far. But when I start Quartus Programmer ...
3
votes
1answer
964 views

Altera Cyclone IV memory block Verilog module

This document explains the various characteristics of the Altera Cyclone IV memory blocks (known as "M9K"). However, there is no mention as to how these modules should be instantiated in Verilog. ...
3
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1answer
848 views

Cyclone II FPGA Starter Kit Configuration Seems to be Giving Bogus Results

I've been trying to get my Cyclone II FPGA (from the Starter Kit, EP2C20) to work. I've gotten the Quartus II software to work on my Ubuntu setup and it' ALMOST working - I can write some Verilog, ...
5
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2answers
14k views

Why do I get a failure in Quartus while trying to programming my FPGA?

I followed with this tutorial into the end of it, but I got an error while trying to programming my DE2 altera kit. the design is input pin output pin (pin_name1 ...
3
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1answer
89 views

Does FLEX10k support SignalTap? [closed]

Can I make an embedded logic analyzer for FLEX (flex10k) devices using SignalTap by JTAG?
2
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1answer
341 views

FPGA project sanity check, PCIE and video processeing

I have an Altera DE4 education FPGA that I'd like to use for video processing... But the thing doesn't have many ports to work with, and I don't have the funds to purchase any daughter boards. My ...
0
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1answer
188 views

Serial Camera recommendations? [closed]

I have an altera stratix iv FPGA, given to me by my professor to do a project that involves video processing. The ports I have to work with are RS232 (female), an IDE port and several SATA ports, and ...
3
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1answer
900 views

Do I need to buy USB Blaster with DE0-Nano?

I am moving this question here to separate question altogether: [DE0-Nano] [l]ooks really good, but do I need to buy the USB Blaster (or another programmer) too? Please, explain the context in a ...
1
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2answers
958 views

Quartus - Export Verilog as Gate Level (FPGA)

I've got a project in Altera's Quartus II software which is written in Verilog. I'm curious if anyone here has figured out how to export the Verilog as a gate level netlist. I'd like to simulate the ...
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2answers
11k views

Verilog: Check for two negedges in always block

i try to do something like this: always @ (negedge speed_dec or negedge speed_inc) begin do something end This doesn't work as checking for 2 negative edges ...
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1answer
519 views

FSM Using Excitation Equations and VHDL

I have been trying to create a FSM using the excitation equations I developed. I have not had much luck. The circuit has no output. I DO NOT WANT TO USE 'TYPE' and custom state types. That is the ...
2
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2answers
4k views

UART core Altera De2

I have to implement a rs232 receiver for my project. Does any one have any idea on how do I start learning / implementing this. Do i have to use the nios ii software or just implement it using verilog ...
2
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1answer
2k views

Trying to program an FPGA. (Altera Cyclone II)

I have got FPGA development board (Cyclone II EP2C20F484C7) and am trying to implement a simple counter program as shown below (and maybe link it to the LEDs). ...
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2answers
1k views

DE2 Expansion Header Mystery

I recently received an Atera DE2 board with a Cyclone II FPGA. I have been experimenting with the expansion headers and I am having trouble understanding why my daughter card is not receiving any ...
3
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2answers
582 views

How to configure my favorite editor in Quartus?

Altera Quartus, as most other EDA tools, allows users to use their favorite editor, instead of the built-in editors. For Quartus, this feature can be activated in Tools > Options > Preferred Text ...
4
votes
1answer
521 views

Do DDR2 chips and controllers have on-die termination?

I am going to try to interface a low-speed 8-bit DDR2 chip with an FPGA, and I've got some questions crucial to make it work: Is that correct that there is on-die termination on both DDR2 memory and ...
4
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1answer
1k views

Getting started with Altera FPGAs

I am getting a Cyclone II-based Altera DE1 FPGA board to experiment with. I know a lot about programming, a bit about electronics and very little about FPGAs. What books or other resources would you ...
0
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2answers
657 views

Reading the configuration array of a MAX7000 PLD

Well, I have a little problem in my hands, I need to clone an Altera Max EPM7128ELC84, luckily the PLD comes in a socketable PLCC84 package and has a JTAG interface. Now my question: what approach ...