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Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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How to check receiving 16-bit data using a serial terminal?

I am using an FPGA vhdl UART code to send 16bits of data with a 1 start bit, 1 stop bits and even parity bit. I need to check whether the sent 16bit packets are correctly receiving using a terminal ...
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1answer
394 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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1answer
889 views

FDCE flip flop primitive on altera quartus?

I would like to know the altera quartus primitive equivalent to the FDCE flip flop on Xilinx ISE. I think that DFFE primitive might work however I am not sure about the CE and CLR pins equivalency. ...
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1answer
75 views

How does FPGA knows the configuraton file is present in Flash memory during bootup?

Which areas in flash memory are scanned during bootup to make sure that there is configuration file present in the external flash memory?
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1answer
297 views

MAX10 .pof file issue, quartus II and usb blaster

After a MAX10 board revision. When programming the MAX10 with .pof, the MAX10 board do not start when power-on or after .pof programming is completed. However, normal operation is achieved when ...
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1answer
36 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...
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1answer
62 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...
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1answer
269 views

Word alignment / bitslip in LVDS Receiver

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...
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1answer
104 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
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1answer
220 views

For Altera LPM_MULT to have registered output, is it enough to set latency to 1?

It is recommended that the inputs and the output of the LPM_MULT be registered. This will make it possible to achieve highest frequency for the design, although introduce latency. With latency of 0, ...
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1answer
1k views

verilog - altera fpga “error pin x has multiple drivers due to the non-tri-state driver”

I have a 32 bit parellel IO interface (PIO) defined in a NIOS II soft processor. It is for a 32 pin connector on a board. I instantiate the NIOS in a top level verilog module called ...
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0answers
62 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...
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0answers
47 views

Two-Terminal Passive Analog Component Tester Using the DE1-SoC Development Board

I am having hard time understanding this problem. I have to draw a Level 1 block diagram for this system. I really appreciated it if somebody can help me. I am new to DE1-Soc. use the Intel DE1-SoC ...
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0answers
89 views

Intel/Altera FPGA bidirectional DQS timing constraint

I have a DDR controller implemented in an FPGA using Altera/Intel/Quartus, and I'm trying to get the constraints correct for the bidirectional DQS pin. This pin is a data strobe pin that the DDR ...
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0answers
194 views

VHDL: How to instantiate different component depending on value of generic?

I have a memory block which is initialized with different values. Therefore, I have created different entities in which the actual hardware is the same - a dual port RAM, but the files used to ...
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0answers
984 views

Debugging FPGA VGA connection

I want to display images on the screen and to do this I used this git and this article as references. The specs of my screen are 1280x1024, including porch pixels the dimensions are 1688x1066. From ...
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379 views

Troubleshooting FPGA VGA connection

I have DE1 Soc development board. I have been following this youtube video in order to start casting some stuff onto the screen. I am unable to display anything on the screen at the moment unless ...
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0answers
33 views

Are there any methods to simulate time-base power usage of a Xilinx/Altera FPGA?

Old versions of Xilinx ISE suite got XPower tool which had -tb option to simulate time-based power usage of an FPGA by an input .vcd file like this: ...
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1k views

Bidirectional FPGA implementations (parallel ADC)

New FPGA convert here. I am trying to interface with a parallel ADC as part of a data acquisition project. The pins on the ADC are used for both input and output (not simultaneously). Therefore, I ...
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0answers
972 views

Shematics of the BeMicro CV eval board from Arrow

Where can I find the complete schematics of the board? Arrow sells an ultra low cost FPGA platform with a Cyclone V device on it for around 30$. Ok, for that price it has the bear minimum: 2 buttons, ...
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0answers
1k views

Altera ModelSim simulating PLL

In my design, I make use of the ATLPLL Library/IP which is to convert the clock frequency accordingly for my design. I am Using De0-Nano board for my project which has cyclone IV FPGA. The ATLPLL ...
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36 views

Custom PCIe DMA on Cyclone 10GX FPGA burst read stucks

I'm writing a custom DMA machine to read and write data to the host system from FPGA memory. I use the Altera PCIe IP core as end point device in Avalon-MM mode. BAR0 is set as 64bit bar, Avalon-MM ...
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In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...
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0answers
27 views

Why does functional simulation generate Zs?

I have a very simple project, I share the files in this github repo If I run a functional simulation (Waveform.vwf in the repository) I get some 'Z' in the value of an internal register, see the ...
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42 views

Identify valid FPGA configuration image in serial flash device?

How can I know if there's valid FPGA configuration image in the specific location of the serial configuration device before I perform reconfiguration and experience successful or faulty attempt? ...
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0answers
63 views

can't send characters using fpga cyclone iv

I'm trying to connect my FPGA Cylone IV (CoreEP4CE6) with Raspberry Pi 3 for communication through UART. The process (uart_rx) for receiving data is working fine, however, when I place another process ...
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0answers
237 views

How to #include files in other folders in Eclipse IDE?

Here is the directory structure of a project I have downloaded: The problem is that when I compile I keep getting fatal error message that say that the specific header file does not exist. For ...
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0answers
243 views

How to specify library to low level Verilog component in VHDL testbench

I have written a VHDL testbench to test a Verilog design. A lower level Verilog module instantiates some FIFOs through Altera Megawizard. The read FIFO code is below: ...
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0answers
122 views

Unable to use the VGA port correctly, De1 Soc distorts signal depending on the output pin

This is a followup to my previous question. The code I was using, pin assigmnets and the theoretical timings for VSYNC and HSYNCH were correct. I have used to oscilloscope to look at the signals, ...
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0answers
207 views

Not port with test bench vhdl, altera quartus prime

I wanted to test this simple VHDL model ...
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0answers
159 views

Altera Quartus - structural architecture

I am relatively new to VHDL and I am supposed to use structural architecture and Altera Quartus on my assignments. But, I have noticed that the Unisim library is not compatible with Altera Quartus, so ...