Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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Word alignment / bitslip in LVDS Receiver

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...
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RTL Simulation Error, Can't Launch ModelSim

I am new on FPGAs so I am using the Altera Cyclone II EP2C5T144 The Quartus Prime version that supports Cyclone II is 13.0 ; I am trying to run a very simple code to turn on a LED ...
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9 views

Can the altera_virtual_jtag be used to store critical design information for read out?

Can critical design information like design version number, compilation date e.t.c be stored inside the FPGA and be read out via JTAG while using the altera_virtual_jtag? I assume that the ...
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How to initialize/load Intel HBM memory in simulation

I am trying to simulate the Intel HBM example design using ModelSim. Is there a way to initialize/load the HBM memory with some data before the simulation? If so, how can we do it?
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546 views

Design of carry chain on Cyclone IV

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "cin" goes high, signal starts to ...
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683 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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dual purpose pins on max 10 fpga

I am breaking into the world of FPGA development at my internship for an aerospace company. I keep coming across the term "Dual-Purpose Pin" in the documentation for the Max 10 family of FPGA devices. ...
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1k views

FDCE flip flop primitive on altera quartus?

I would like to know the altera quartus primitive equivalent to the FDCE flip flop on Xilinx ISE. I think that DFFE primitive might work however I am not sure about the CE and CLR pins equivalency. ...
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For Altera LPM_MULT to have registered output, is it enough to set latency to 1?

It is recommended that the inputs and the output of the LPM_MULT be registered. This will make it possible to achieve highest frequency for the design, although introduce latency. With latency of 0, ...
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EP53F8QI Short to GND fault

We have a design with an EP53F8QI that multiple ICs have been burned both at room temperature and +80 °.C. We are using it to create a +3.3V and on fault we have found that the +3.3V supply is shorted ...
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verilog - altera fpga “error pin x has multiple drivers due to the non-tri-state driver”

I have a 32 bit parellel IO interface (PIO) defined in a NIOS II soft processor. It is for a 32 pin connector on a board. I instantiate the NIOS in a top level verilog module called ...
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Measuring the external memory power consumption in FPGAs?

I am trying to get a power/energy breakdown of DDR3 and core logic. I used Quartus power analyzer tool to get the power estimates, but I am not sure whether it includes the power consumption of ...
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33 views

Is it possible to add an existing IP variant to a Platform Designer/Qsys system through TCL?

I have a .ip file that contains a parameterized component which I'd like to use in my Qsys system. I can add the component via the GUI but I would like to be able to add it via TCL or another ...
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97 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...
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Altera Cyclone IV Setting Impedance

I'm trying to learn how to implement a 3V LVTTL interface using a Cyclone IV E (EP4CE10) FPGA. However, I would like to ensure that the input/output impedances of the IO is at 50R. I see that it is ...
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616 views

How to check receiving 16-bit data using a serial terminal?

I am using an FPGA vhdl UART code to send 16bits of data with a 1 start bit, 1 stop bits and even parity bit. I need to check whether the sent 16bit packets are correctly receiving using a terminal ...
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62 views

VHDL: case when using constants constructs

I'm having some trouble with the following statement ...
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51 views

Register value is not updated inside always @ loop

I am relatively new to verilog, please help with this issue I am having. Attached is a snippet of the code I am working on. The issue I am facing is, the regs - del1 and del2 are not correctly ...
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42 views

What is purpose of exporting system using tcl scripts generated by Qsys?

To "Export" a Qsys system we merely need the .qsys file. Inside Qsys (now called Platform Designer) we have the option where we can export the system as a .tcl script. The options are the in the file ...
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Is it possible to create a Qsys system with VHDL generics at its top level?

Some components in my Qsys system have test modes. These are controlled via generics on their top level. These components are currently in a Qsys system. In Qsys, I can click on them and change the ...
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27 views

What is the difference between words and symbols in Qsys, how to know which one to use?

Qsys offers options to select address unit or address type. All I know is that my custom components shall write 32 or 64 bit data to a specific address and it is not byte addressable. How do I decide ...
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37 views

Verifying custom Qsys component?

A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also. These copies ...
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71 views

Verilog 'if' statement error

Why are LEDs on after executing this? LEDs on pattern is 1010: ...
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1answer
130 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
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Quartus II - Can I include other files into a *.qsf file?

An Altera Quartus II project consists of one *.qpf and one or more *.qsf files. The qsf seems to be a TCL script like other EDA related settings and config files (e.g. xdc, sdc, ...). Is is possible ...
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364 views

I2S output in VHDL

I am making an I2S output in VHDL for a project. This is my first project using VHDL and the problem may be my basic VHDL understanding. This is my code: ...
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Intel FPGA equivalents of Xilinx IBUFDS Primitives?

Im trying to migrate an Design from using Xilinx primitives to Intel Altera FPGA. The original design uses the IBUFDS for the clock signals. ...
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2answers
37 views

How can Qsys component configuration be accessed in software?

I'm designing a Qsys component which I want to be user-configurable. It has config parameters which are defined in the TCL file. For example, for a GPIO bank component I would write: ...
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53 views

LMS7002M: I & Q DATA formats from LIMESDR

Can any one tell me what is the data format of LMS7002m I & Q sample? Are they unsigned int or floating or double? how are they ? Also kindly anyone show me any hint of proof for their answer.... ...
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76 views

altera FPGA acting like OR gate when programed as AND gate

I'm new to altera fpga , I've bought development board based on EP4CE6E22 cyclon IV and tryed to program it with basic program in quartus environment ...
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857 views

what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and ...
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1answer
717 views

Error (209015): Can't configure device. Expected JTAG ID code 0x020B10DD for device 1, but found JTAG ID code 0x000210DD

I bought from ebay Altera Cyclone II EP2C5T144 development board. It came with USB Blaster. I'm using Quartus II 13.0sp1. FPGA is programmed with default settings as it should be (flashing onboard ...
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438 views

MAX10 .pof file issue, quartus II and usb blaster

After a MAX10 board revision. When programming the MAX10 with .pof, the MAX10 board do not start when power-on or after .pof programming is completed. However, normal operation is achieved when ...
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How to make Quartus II find the Altera DE2 board?

I use Quartus II web edition and using that driver my computer can find the card: And the card appears in the device manager so it indeed looks correct so far. But when I start Quartus Programmer ...
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282 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...
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84 views

Get more AS-attached flash chip information from ALTASMI

I am playing with the attaching various configuration flash devices to the Altera Cyclone 3. In particular, I want to replace EPCS16 (2MB) with W25Q128 (16MB) - for both size and cost reasons. Is ...
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Custom PCIe DMA on Cyclone 10GX FPGA burst read stucks

I'm writing a custom DMA machine to read and write data to the host system from FPGA memory. I use the Altera PCIe IP core as end point device in Avalon-MM mode. BAR0 is set as 64bit bar, Avalon-MM ...
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25 views

In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...
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64 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...
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37 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...
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214 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...
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97 views

How can I check if an IO pin is dead?

I've been playing around with I2C for a couple days now with a DE10-Nano dev board: I'm implementing an I2C master in CLaSH so that I can talk to the HDMI encoder chip, but for now I'm talking to an ...
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29 views

Why does functional simulation generate Zs?

I have a very simple project, I share the files in this github repo If I run a functional simulation (Waveform.vwf in the repository) I get some 'Z' in the value of an internal register, see the ...
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95 views

What's wrong with this schematic for powering up Cyclone IV FPGA?

I have followed all the guide lines for powering up the Cyclone IV. However, the 3.3v Regulator is heating too much and also the Cyclone IV FPGA. What's wrong with my schematic? Is there a problem in ...
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33 views

Altera FlipFlop stuck at GND

I'm trying to make a counter that counts: 0,1,2,3,4,5 I need this for a frequency divider of 6 So I made this table: From this I get: J0= 1 K0= 1 J1 = NOT Q0 AND Q1 K1 = Q1 J2 = Q1 AND Q2 K2 =...
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Identify valid FPGA configuration image in serial flash device?

How can I know if there's valid FPGA configuration image in the specific location of the serial configuration device before I perform reconfiguration and experience successful or faulty attempt? ...
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can't send characters using fpga cyclone iv

I'm trying to connect my FPGA Cylone IV (CoreEP4CE6) with Raspberry Pi 3 for communication through UART. The process (uart_rx) for receiving data is working fine, however, when I place another process ...
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381 views

Altera has created EPCS and EPCQ devices, can only these be used to store FPGA configuration data?

FPGA configuration data must be stored in external non-volatile memory. Can we use just any flash memory or only specific types? What about EEPROMs or any other nonvolatile memory device? Edit: I am ...
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290 views

Program FPGA using STM32

I am interested in using an STM32 to flash an sof or pof file onto a Cyclone IV FPGA. The sof/pof will be stored in SPI flash memory, and the plan is to use the STM32 as a programmer. I haven't been ...
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67 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...