Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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Intel De1-SoC VGA controller in VHDL

I have implemented a VGA controller in VHDL using the timing specifications for a 600x480 monitor as described in the attached photos. The module takes in a 50MHz clock and is supposed to draw a ...
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41 views

problem in adding IP to platform designer

I'm new to platform designer and I want to add an ALT PLL intel FPGA IP to a platfrom designer project but after opening Mega wizard plugin manager and setting up the requirements, IP does not add to ...
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Verilog design to display character using “16x2 Character Display” IP from Quartus IP Library

I was trying to display a single character on 16x2 display. I created simple Verilog design for "Altera Cyclone V Development Kit". In the project I used "16x2 Character Display" ...
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Possible to use Segger J-Link with Intel Quartus to flash FPGA?

Does anybody know if it's possible to use a Segger J-Link with Intel Quartus to flash an FPGA?
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How can Quartus Prime System Console be used to read/write a whole file?

I want to find a way to read/write whole file from/to my Intel FPGA design. The file being written provides data to be processed and the file being read shall contain the results of the processing ...
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Audio Demos on DE10 Standard not Working

I bought the Terasic DE10 Standard and am having issues trying to run the demos related to audio. I am trying to run the two demos, DE10_Standard_Audio, and DE10_Standard_i2sound, while connecting ...
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Can Quartus System Console be used via Ethernet instead of USB Byte Blaster?

The System Console communicates with the the design inside the Intel FPGA via a JTAG-Avalon MM master. The JTAG connection connects to the Byte Blaster and this is how the debugging works. Is there a ...
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38 views

Time to Digital Converter using FPGA with Coarse Counter in Verilog

I am currently using Verilog to program an FPGA and create a time-to-digital converter. What I am trying to do is measure the time interval when a square wave is high and then convert this to a binary ...
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The set_command_request procedure from altera_avalon_mm_master_bfm_vhdl_pkg does not return thus master BFM does nothing

I am trying to use the Altera Avalon MM Master BFM in my Qsys testbench. When we want the BFM to make a read or write request, we first call the set_command_request() which is described in the "...
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How Does One Do Block RAM Inference on Altera Cyclone 10 LP FPGA Boards in Verilog [closed]

I have tried to google for this a lot but I can't seem to find anything.
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Setting minimum and mximumu delay from register to asynchronous logic in sdc file

Is it possible to write design constrain in sdc file to tell synthesyser to limit absolut delay from register to asynchronous multiplexer. I have 4 phase shifted clocks and signals synchronized with ...
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47 views

How to create on-board USB blaster for Intel FPGAs?

Intel/Altera FPGA development boards only require a USB cable to configure the FPGAs. There is no need to buy a byte blaster. How is the USB blaster implemented on these boards, is this method/design ...
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171 views

Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
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Generating error condition randomly inside a digital design inside FPGA

In order to aid in testing of the design, it is required that we put it into a "debug mode" whereby specific type of error conditions will occur at random intervals. We must then monitor the ...
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63 views

How do you select pin functions on an EPM7128 CPLD?

I have some old Altera MAX EPM7128SLC84-15N CPLDs kicking around that I want to use to interface with 5v TTL logic. If you look at the pinout, some of the pins have more than one function (eg. Pin 2 ...
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FPGA Timing Constrain Problem

I am using the Cyclone V DE1-SoC in transferring data between HPS and ...
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14 views

Error while building project in Quartus with Eclipse tool

I'm pretty new to the forum so if something is wrong with the question, sorry in advance. Currently, I'm working on a free project for school. My teammates and I decided to make a 'drawing glove'. ...
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What do HDLs compile/synthesize to?

I'm a software engineer. As a programmer, I have an understanding of what my compiler does for me because I've manually written a close textual representation of what it outputs (e.g. assembly). For ...
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Interface mpu6050 with de2-115 board i2c

I'm currently working on a project for school. My teammates and I want to make a magic glove, that can draw on a VGA monitor with data from an accelerometer and gyrosensor. Therefore we are using a ...
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What is the easiest way to simulate and experiment with FPGA using simulated external DDR3?

For a computer architecture school project I have to implement an algorithm in verilog, such design have to input and output a VERY large ammount of data that wouldn't fit in on-chip memory, hence I ...
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What are <device_name>@<device_index> to quartus_pgm?

I am trying to download the firmware of a MAX 10 FPGA with the "examine" operation. The help for the command line interface quartus_pgm to Quartus Prime says ...
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2answers
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Access elements randomly in RAM based FIFO VHDL FPGA

The thing is: new data is being generated every "time step" that can be few clock cycles. So I want to store the data generated for few time steps in a "buffer". The data must be stored like in a ...
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48 views

How to use array in Verilog actually?

I found that inVerilog, the array can only be declared in reg. And I found that it seems ...
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Multiplexer Simulation failed in Quartus II Web Edition 15.0

I'm currently working on some assignment for digital electronics. Before this, as in , before I reformat my laptop, everything works just fine. After that, After i reinstall Quartus II, the same ...
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Present two images side by side on the VGA screen from FPGA

Im trying to get a clue how to present two images on the screen using VGA. I using Altera Cyclone 2 DE2 and VGA, I have already working vga sync driver for 640*480 res: ...
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Cyclone III FPGA 3.3V LVTTL output rise and fall time restoration at 25MHz

I am using this signal to drive MD1822 mosfet driver to get high voltage pulses but fpga output rise time and fall time almost 40nS and underdamped I can not get good pulses. How can i improve this? I ...
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139 views

Variable Bit shift within 1 Clock Cycle (Verilog)

I have a 64-bit register that I would like to right shift n times, with 0<=n<=64, implemented as such always_ff data[63:0] <= (data >> n); I ...
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65 views

How can i export synthesized netlist from Quartus 2?

I need to get a netlist that creates by synthesis and optimization from different hdl languages in Quartus 2. I need a netlist in basic logic. Rtl viewer shows me something similar, but i need it in ...
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137 views

Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...
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1answer
158 views

UART not fast enough for debug purpose, what alternatives exist?

This problem is related with debugging an FPGA design implemented in Intel/Altera FPGA. A custom debug mechanism has been introduced into the design. This new part of the design writes into a FIFO ...
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101 views

PIN Placement Errors In Quartus

So I am writing a simple blinking LED Verilog code that will be run on a Cyclone10 LP (Device is called 10CL025YU256I7G) and will be tested on a Cyclone 10 Evaluation Kit (6XX-44504R-0D) All code is ...
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1answer
54 views

Setting Pin Assignments For Quartus

So I have written a simple Verilog module which works well in the ModelSim emulator. I would like to now program my Cyclone 10 Dev board to perform this simple task, but I need to set up the pin ...
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151 views

Raw programming of an Altera FPGA

I have an Altera Cyclone IV FPGA (for ie) and my question is: is it possible a raw programming of the FPGA? Is it possible to set "manually" the gates for making experiments? Thank you
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dual purpose pins on max 10 fpga

I am breaking into the world of FPGA development at my internship for an aerospace company. I keep coming across the term "Dual-Purpose Pin" in the documentation for the Max 10 family of FPGA devices. ...
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Measuring the external memory power consumption in FPGAs?

I am trying to get a power/energy breakdown of DDR3 and core logic. I used Quartus power analyzer tool to get the power estimates, but I am not sure whether it includes the power consumption of ...
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1answer
183 views

Is it possible to add an existing IP variant to a Platform Designer/Qsys system through TCL?

I have a .ip file that contains a parameterized component which I'd like to use in my Qsys system. I can add the component via the GUI but I would like to be able to add it via TCL or another ...
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44 views

Altera Cyclone IV Setting Impedance

I'm trying to learn how to implement a 3V LVTTL interface using a Cyclone IV E (EP4CE10) FPGA. However, I would like to ensure that the input/output impedances of the IO is at 50R. I see that it is ...
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73 views

VHDL: case when using constants constructs

I'm having some trouble with the following statement ...
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1answer
74 views

Register value is not updated inside always @ loop

I am relatively new to verilog, please help with this issue I am having. Attached is a snippet of the code I am working on. The issue I am facing is, the regs - del1 and del2 are not correctly ...
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120 views

What is purpose of exporting system using tcl scripts generated by Qsys?

To "Export" a Qsys system we merely need the .qsys file. Inside Qsys (now called Platform Designer) we have the option where we can export the system as a .tcl script. The options are the in the file ...
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65 views

Is it possible to create a Qsys system with VHDL generics at its top level?

Some components in my Qsys system have test modes. These are controlled via generics on their top level. These components are currently in a Qsys system. In Qsys, I can click on them and change the ...
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225 views

What is the difference between words and symbols in Qsys, how to know which one to use?

Qsys offers options to select address unit or address type. All I know is that my custom components shall write 32 or 64 bit data to a specific address and it is not byte addressable. How do I decide ...
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55 views

Verifying custom Qsys component?

A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also. These copies ...
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1answer
75 views

Verilog 'if' statement error

Why are LEDs on after executing this? LEDs on pattern is 1010: ...
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1answer
191 views

Intel FPGA equivalents of Xilinx IBUFDS Primitives?

Im trying to migrate an Design from using Xilinx primitives to Intel Altera FPGA. The original design uses the IBUFDS for the clock signals. ...
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2answers
60 views

How can Qsys component configuration be accessed in software?

I'm designing a Qsys component which I want to be user-configurable. It has config parameters which are defined in the TCL file. For example, for a GPIO bank component I would write: ...
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114 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...
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154 views

LMS7002M: I & Q DATA formats from LIMESDR

Can any one tell me what is the data format of LMS7002m I & Q sample? Are they unsigned int or floating or double? how are they ? Also kindly anyone show me any hint of proof for their answer.... ...
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altera FPGA acting like OR gate when programed as AND gate

I'm new to altera fpga , I've bought development board based on EP4CE6E22 cyclon IV and tryed to program it with basic program in quartus environment ...
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886 views

what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and ...

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