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Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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3answers
28k views

What is clock skew, and why can it be negative?

My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24): To ...
10
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4answers
23k views

Using both edges of a clock

I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here ...
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4answers
5k views

Why FPGA's have latches when they are almost never used?

This question is a follow up question of the existing question: "When is using latches better than flip flops in an fpga that supports-both". If use of latches in FPGA's is limited to rarest or rare ...
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2answers
4k views

Do I need to reset my FPGA design after startup?

I usually initialize state registers of my FSMs by specifying an initial value in my VHDL code, so that, I do not require a reset pulse after startup of the configured FPGA. The following example ...
7
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1answer
14k views

What are ALMs, LEs and ALUTs?

Does ALM mean "Adaptive logic module"? www.altera.com/literature/ds/ds_nios2_perf.pdf‎ Jul 1, 2013 - One ALUT is equivalent to about 1.25 LEs. Does LE mean logic element and ALUT means adaptive ...
6
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1answer
857 views

what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and ...
6
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2answers
3k views

PCIe fails on “polling compliance” state

I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work. Debugging with SignalTap shows that ...
6
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2answers
5k views

Specify exact pin locations on FPGA

I have an Altera Cyclone IV FPGA, and I use the Quartus II software as the compiler. In the "PinPlanner" it is possible to specify groups of pins (e.g. data buses). For each group, an I/O bank and an ...
6
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2answers
2k views

Improve Quartus partial compile or recompile time

I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. ...
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4answers
4k views

What is a ripple clock?

I am reading Chapter 12. Recommended Design Practices from the Quartus II Handbook Version 13.1 Volume 1: Design and Synthesis which states (p. 8): Ripple counters use cascaded registers, in which ...
5
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3answers
444 views

Use ancient Altera MAX II board in modern environment

Years ago (in 2004) my university got an Altera MAX-II devboard, but nobody used it. Now it's me who must teach students FPGA programming, but I still cannot get the board programmed. I faced the ...
5
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4answers
13k views

Generating pulse train of varying frequency on an FPGA

I am working on generating a pulse train to control a motor that accepts a pulse train as an input. Each pulse corresponds to a pre-set movement increment; I can set one pulse equal to 1/1000 degree (...
5
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1answer
525 views

What does the FPGA do with unreferenced I/O pins?

Here's one thats been puzzling me for a while. I have an FPGA design in Altera, driving an audio chip and programmed through its serial interface. I monitor and debug this with an oscilloscope/...
5
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1answer
2k views

CDC Synchonisation primitives for an Altera FPGA

I am working on my first non-trival FPGA design and finally have a need for Clock Domain Crossing (CDC). There are multiple resources (amongst others) which discuss various architectures for CDC and ...
5
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1answer
7k views

How do for loops work in verilog? Why can't I achieve what I want?

This is my code for a simple 2-1 8 bit multiplexor, where SW[17] is my selector. If it is on, show Y = SW[15:8], if it is off, ...
5
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2answers
15k views

Why do I get a failure in Quartus while trying to programming my FPGA?

I followed with this tutorial into the end of it, but I got an error while trying to programming my DE2 altera kit. the design is input pin output pin (pin_name1 ...
5
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1answer
3k views

Altera: Change JTAG clock speed

I am having issues with JTAG with my Cyclone IV, specifically the JTAG clock. I am trying to change the JTAG clock frequency somewhere, but can't find where this is done in Quartus II. How can I ...
5
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1answer
950 views

Altera Cyclone V - Linux & FPGA interrupt handling

I need to propagate an interrupt from my custom FPGA IP core to the HPS system of a DE0_nano_SoC (Cyclone V HPS-FPGA architecture) and handle in Linux. I have googled quite a lot to confidently say ...
5
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1answer
1k views

Altera Cyclone V: Timing issues with routing (interconnect)

I'm designing an application with an Altera Cyclone V SoC (5CSXFC6C6U23I7N) and interfacing ADCs and DACs at 250MS/s. In the meantime, the design complexity has increased a bit and now there are ...
4
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2answers
6k views

Quartus II: Where are the worst-case paths?

In the Quartus II settings (under TimeQuest timing analyser), I have checked the Report worst-case paths during compilation checkbox. However, I do not see any ...
4
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2answers
2k views

Dual port RAM on Altera and Xilinx FPGA

I have always managed to synthesis a 256 x 32 bits dual-port RAM (not true dual port RAM) in Xilinx ISE with just 1 x 18K BRAM. The example code from here was used: ...
4
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3answers
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Altera optimisation: “Stuck at GND due to stuck port data_in”

I am compiling Verilog code with the Quartus II compiler, and it seems that almost all my code is being optimised away. The "compilation report" says that many of my registers are being removed during ...
4
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3answers
6k views

How to efficiently implement a single output pulse from a long input on Altera?

I have a fast clock and a switch called 'ready'. When the switch is flipped (ready goes HIGH), I would like the output pcEn to produce a pulse that lasts only for one clock cycle. pcEn will only ...
4
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2answers
863 views

OpenCL for Altera FPGAs

Recently I have been quite interested in OpenCL of the Khronos Group, and already gained some experiences with the language. I'm excited to know that OpenCL now works with Altera FPGA. http://www....
4
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2answers
310 views

Quartus II: Customise compiler messages

I am working with the Altera Quartus II compiler for my Cyclone IV. I am not happy with what is considered Info, Warning, ...
4
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2answers
11k views

Verilog: Check for two negedges in always block

i try to do something like this: always @ (negedge speed_dec or negedge speed_inc) begin do something end This doesn't work as checking for 2 negative edges ...
4
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1answer
6k views

Bus to wire in quartus

I sometimes run into a problem with altera's Quartus that I would like a better solution to. Sometimes I use the graphical interface for design and I have a bus that I would like to pull off just one ...
4
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1answer
1k views

Getting started with Altera FPGAs

I am getting a Cyclone II-based Altera DE1 FPGA board to experiment with. I know a lot about programming, a bit about electronics and very little about FPGAs. What books or other resources would you ...
4
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2answers
3k views

FPGA encoder counter running away randomly

I am programming an Altera FPGA using Quartus II v9.0 to count encoder pulses and output that count to an external LabVIEW program (see diagram below). I was able to debug one issue with my code ...
4
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1answer
609 views

Possible causes of dead cyclone IV on custom board

i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes: I am using 3.3V VCCIO for all IO banks. I misread the handbook and ...
4
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1answer
467 views

What are the jitter characteristics of PLLs internal to Stratix V FPGAs?

I am interested in knowing the deterministic and random jitter characteristics of PLLs internal to Stratix V FPGAs. I have looked through the Stratix V handbook but could not find numbers quantifying ...
4
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1answer
802 views

How do I make use of multipliers to generate a simple adder?

I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks ...
4
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1answer
522 views

Do DDR2 chips and controllers have on-die termination?

I am going to try to interface a low-speed 8-bit DDR2 chip with an FPGA, and I've got some questions crucial to make it work: Is that correct that there is on-die termination on both DDR2 memory and ...
4
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1answer
1k views

Altera's DRAM Controller with UniPHY

I am trying to port a design from Xilinx to Altera, and I have issues with the DRAM controller IP (for a Cyclone-V and a LPDDR2 mem). I have managed to generate the IP, but I don't understand which ...
3
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1answer
907 views

Best utillization of M9K memory in max10 or other altera fpga's

I've got a max10 with a nios processor built in my memory utillization on the part is: 414,198 / 562,176 ( 74 % ) but I've used up every M9K block on the FPGA. Here is a table for the utillization As ...
3
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2answers
276 views

Measuring Power from Altera Dev. Kit (CycloneIII)

The Altera CycloneIII starter kit that I have provides a jumper (J6) that is connected to VCCINT of the CycloneIII FPGA core for what seems to be the purpose of measuring the core's power consumption. ...
3
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1answer
7k views

Altera Quartus “Warning (18236): Number of processors has not been specified…”, how to suppress?

My Altera Quartus builds show this warning... ...
3
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1answer
304 views

What are retimers?

I am working with a low latency 10G MAC IP core for a Stratix V FPGA. One of the parameters is "High performance mode". The documentation states When enabled, high performance mode enables all ...
3
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1answer
6k views

Specify include path in Quartus II

I'm compiling Verilog using the Quartus II for the Altera platform. In my Verilog, I have a Verilog header global.vh, and Quartus II cannot find it: ...
3
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2answers
596 views

How to configure my favorite editor in Quartus?

Altera Quartus, as most other EDA tools, allows users to use their favorite editor, instead of the built-in editors. For Quartus, this feature can be activated in Tools > Options > Preferred Text ...
3
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3answers
6k views

Quartus II - Can I include other files into a *.qsf file?

An Altera Quartus II project consists of one *.qpf and one or more *.qsf files. The qsf seems to be a TCL script like other EDA related settings and config files (e.g. xdc, sdc, ...). Is is possible ...
3
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2answers
8k views

Can we run Quartus II on Ubuntu?

I can compile digital components and download them to the boards DE2 and DE2-115 I got. I do it from Windows 7 but I want to enable this on ubuntu while the files from Altera are for Red Hat Linux. I'...
3
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1answer
965 views

Altera Cyclone IV memory block Verilog module

This document explains the various characteristics of the Altera Cyclone IV memory blocks (known as "M9K"). However, there is no mention as to how these modules should be instantiated in Verilog. ...
3
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1answer
906 views

Do I need to buy USB Blaster with DE0-Nano?

I am moving this question here to separate question altogether: [DE0-Nano] [l]ooks really good, but do I need to buy the USB Blaster (or another programmer) too? Please, explain the context in a ...
3
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1answer
370 views

Altera Cyclone II Quartus II JTAG Programming Error

I'm trying to program a Cyclone II I bought here using Quartus II 13.0sp1 on Arch Linux. I'm trying to program it with a very simple Verilog program with three inputs and two outputs and a few simple ...
3
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2answers
3k views

Configure (upload bitstream) to MAX10 without Altera tools using Linux

I am currently using the flash-based Altera MAX10 in designed attached to main processor which runs Linux on a custom board (the FPGA itself just implements a few peripherals; the processor running ...
3
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1answer
1k views

Altera Cyclone II JTAG after AS Programming

I've been playing with FPGA(Cyclone II EP2C5T144C8) with Quartus II 13.0 WebEdition 64bit and Altera USB Blaster. At first, I was using JTAG mode for programming FPGA into RAM. When I wanted to ...
3
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1answer
229 views

Designing a peripheral for soft core CPU

I've been implementing a hardware module in VHDL for part of my university dissertation and I want to implement it as part of a NIOS II core in my cyclone 2 FPGA. This uses the Avalon interface, what ...
3
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4answers
362 views

Simulating Altera FPGAs with an old version of ModelSim?

I'm hoping to do some development work on Altera FPGAs that will likely be larger than is supported by the free edition of ModelSim. I have an old copy of the full version hanging around (version 6.5,...
3
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1answer
5k views

What's wrong with this 4-bit ALU?

I've put together a 4-bit ALU that seemed to perform correct in simulation but when downloaded to the board it is not behaving correctly. The operation OR behaves correctly while addition and AND are ...