Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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290 views

How to #include files in other folders in Eclipse IDE?

Here is the directory structure of a project I have downloaded: The problem is that when I compile I keep getting fatal error message that say that the specific header file does not exist. For ...
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105 views

Can Nios II read addresses in increments of 1 or only increments of 4?

There is some confusion here. I think that the Nios II having 32 bit data bus. Therefore, it is not capable of individual byte addressing. Therefore, the address bus increases as 0, 4, 8 e.t.c and not ...
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57 views

register enable line usage in `case` block (verilog synthesis for altera cpld)

I have the following in a verilog design aimed at an altera CPLD (currently targeting EPM240, although the target device isn't set in stone): ...
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106 views

What is the minimal schematic (needed capactiors/resistors) to use FPGA Altera Cyclone 4 EP4CE6E22C8N? [closed]

I can't find any information about how wire the Cyclone 4 FPGA. I do not want to use development boards.
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333 views

VHDL - Subtype or type has null range

What is the meaning of the following warning (raised by Quartus)? ...
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378 views

MAX10 .pof file issue, quartus II and usb blaster

After a MAX10 board revision. When programming the MAX10 with .pof, the MAX10 board do not start when power-on or after .pof programming is completed. However, normal operation is achieved when ...
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413 views

How does one read a FIFO outside Qsys system using Nios II?

There is a FIFO block that has Avalon interface compatible with Qsys that can be used in Qsys systems. However, in my case there is an external block that generates data that is to be read by a Nios ...
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65 views

Nios 2 softcore IP

The SOPC board contains an Altera Stratix Processor, but the description mentions use of an Alteras NIOS II soft core IP. If its a soft core then why are we using a Stratix processor. PIC from: ...
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94 views

Incomprehensible FPGA error

I try and upload my design, which worked previously, using quartus prime 17.1 to an Altera DE2-115. It fails like this: ...
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276 views

Can I connect all my components in my top level entity

I have finished writing a project with separate VHDL files. Most of the components have connections directly to the FPGA ( which I have instantiated and connected in the top level file) but a few do ...
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2answers
380 views

in what order does a VHDL program run in an FPGA

I am trying to wrap my head around exactly what goes on in an FPGA when I program it, specifically using VHDL. I know all code outside processes run concurrently but what about processes in different ...
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215 views

Altera Max10 altPLL slack

Regarding a MAX10 board. The whole design inside the MAX10 is clocked from a single clock using verilog's always@(posedge clockin). If connect directly a 80mhz clock to a Max10 input pin and define ...
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131 views

Altera HDL design techniques

Some many years ago my teacher taught us to program Xilinx Spartan II development board. He taught us to think of the hardware element we wanted to invoke (logic gate, adder, shift register, etc) and ...
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281 views

Is it possible to find the critical path in specific part of the design?

I have written RTL description of a circuit in VHDL which is hierarchical and I am using Altera Quartus II; my design meets timing. I had set 50MHz clock frequency (20ns period) constraint using ...
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251 views

FPGA Jtag Hooking to User Logic

After some primer reading on jtag it looks to be a nifty means to test a FPGA logic design in a consistent and sustainable way. Let's use altera max 10 as an example. I've read this MAX 10 JTAG ...
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76 views

Trouble understanding timing simulations in Quartus?

I have tried my ALU on the functional simulation and I get the correct waveforms. However, I am confused about how to interpret the timing simulations. What causes the ripples in the carry_out, and ...
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68 views

Is it possible to know what % of routing resources are used in an FPGA

FPGAs contain logic resources and routing resources to link them together. I think that, for a given number of logic blocks being used, there would be a % of routing resources being used that link ...
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53 views

Why am I getting my result as a string of Zs in Quartus?

I am new to Quartus, and have been trying to test out my 32-bit ALU on Quartus 13.1. When I try the functional simulation, I get a string of Zs. The results for the individual components, like the ...
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443 views

How do I implement a communications interface to an Altera FPGA?

I have a DE1-SoC with some data coming in through an A-D Card. After digital processing I want to transmit data to a host PC for records. I'm trying to figure out the easiest way to go about this. I'...
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310 views

FPGA Internal Timing constraint failing

I'm currently trying to implement an IP-Core on a Cyclone V 5CSEBA6U23I7 FPGA-HPS System using Altera Quartus II and TimeQuest Analyzer. The Verilog code pasted below produces a timing problem, namely ...
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272 views

How to specify library to low level Verilog component in VHDL testbench

I have written a VHDL testbench to test a Verilog design. A lower level Verilog module instantiates some FIFOs through Altera Megawizard. The read FIFO code is below: ...
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175 views

What options exist to verify Avalon-MM slave component?

I am writing an Avalon-MM slave. It shall connect to Nios II as master device. What options exist to write testbench for it? I must be sure that an Avalon-MM master can correctly read/write it. I ...
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189 views

Cyclone V data corruption at high frequency

I'm currently trying to implement a FPGA design using a 325 MHz clock, which writes to the SDRAM Controller of a Cyclone V 5CSEBA6U23I7 (Speed Grade 7). When running my IP Core with 2 MHz everything ...
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878 views

Altera Cyclone V - Linux & FPGA interrupt handling

I need to propagate an interrupt from my custom FPGA IP core to the HPS system of a DE0_nano_SoC (Cyclone V HPS-FPGA architecture) and handle in Linux. I have googled quite a lot to confidently say ...
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2answers
582 views

How to check receiving 16-bit data using a serial terminal?

I am using an FPGA vhdl UART code to send 16bits of data with a 1 start bit, 1 stop bits and even parity bit. I need to check whether the sent 16bit packets are correctly receiving using a terminal ...
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603 views

Error (209015): Can't configure device. Expected JTAG ID code 0x020B10DD for device 1, but found JTAG ID code 0x000210DD

I bought from ebay Altera Cyclone II EP2C5T144 development board. It came with USB Blaster. I'm using Quartus II 13.0sp1. FPGA is programmed with default settings as it should be (flashing onboard ...
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549 views

VHDL Component Instantiantion Failure, Entity or Architecture wrong?

I want to design a UART receiver/transmitter and by now I already developed the receiver vhdl file but when declare and instantiate the the receiver component on my Mainboard Design I get very much ...
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178 views

Can I learn VHDL on a CPLD device?

I need to learn and practice VHDL, so I wouldlike to buy a small FPGA dev board. I've found a board based on a MAX10 circuit with the exact form factor I need, but I've read this chip is a CPLD, not a ...
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2k views

“expecting endmodule” error, can't understand why?

I'm trying to build a counter with a-sync reset, that will be shown on the 7-segment display on the fpga board. I saw a few posts about my problem: "near text "if"; expecting endmodule" But still ...
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236 views

For Altera LPM_MULT to have registered output, is it enough to set latency to 1?

It is recommended that the inputs and the output of the LPM_MULT be registered. This will make it possible to achieve highest frequency for the design, although introduce latency. With latency of 0, ...
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1k views

FDCE flip flop primitive on altera quartus?

I would like to know the altera quartus primitive equivalent to the FDCE flip flop on Xilinx ISE. I think that DFFE primitive might work however I am not sure about the CE and CLR pins equivalency. ...
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84 views

FPGA Routing general criteria

I was implementing a simple circuit on an FPGA using Quartus (6 logical elements) and I noticed that the block containing the 6 cells is located near the perimeter. Is this a general criterion? The ...
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131 views

On Cyclone II FPGAs can I apply voltage directly on input pins?

On Cyclone II FPGAs can I apply voltage directly on input pins, maybe taking it from a Vcc pin? Or should I use a resistor? The Altera DE2 board's schematics below looks like some input switches don'...
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989 views

FPGA maximum frequency : limiting factor

I would like to know which in general may limit the maximum clock frequency of a circuit implemented in FPGA. In the specific case I am building some FIR filters using Quartus and simulating them on a ...
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99 views

Power on configuration for MCU using CPLD and pin multiplexing

simulate this circuit – Schematic created using CircuitLab Suppose we have simple same here. The logic behind this is very simple. During MCU boot it tests pins CONF1 and CONF2 for data on it (...
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247 views

routing jtag signals through an FPGA

I am routing a JTAG signals through an Altera FPGA to a TI MCU. The signals are TMS, TCK, TDO...
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185 views

How to direct input and output of circuit for multifunctional 4 bit calculator [closed]

I am trying to build a 4 bit calculator that can add subtract and multiply using a FPGA board (Altera DE2). I have an adder/subtractor and multiplier already built and functioning but need to know ...
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2answers
257 views

Can the same net-list file be used for ASIC design flow as well as FPGA design flow?

I have mostly worked on front-end part and don't know much about back-end stuff. I have gone through the reading about the various abstraction levels of design flows of FPGAs and ASICs. I was ...
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603 views

FPGA, accessing data in RAM

I'm using an Altera Cyclone V DE1-SoC for an image processing project and to be able to do the "processing" on the FPGA, I thought I probably needed to store the image data on the FPGA first. So I ...
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1k views

verilog - altera fpga “error pin x has multiple drivers due to the non-tri-state driver”

I have a 32 bit parellel IO interface (PIO) defined in a NIOS II soft processor. It is for a 32 pin connector on a board. I instantiate the NIOS in a top level verilog module called ...
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290 views

Quartus Prime Qsys HPS(Hard Processor System) Error

I'm trying to generate a system including HPS(Hard Processor System) of the Cyclone V SoC in Quartus Prime Qsys. At the "Generate HDL" stage I got the following errors. I'm not expecting all the error ...
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1answer
306 views

Altera's MAX10 remote update

I am going to implement a MAX10 remote update. Unfortunately, in Altera's documents i only see a NIOS implementation and everything looks very big and too complex. Also i already have a reliable ...
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521 views

What does the FPGA do with unreferenced I/O pins?

Here's one thats been puzzling me for a while. I have an FPGA design in Altera, driving an audio chip and programmed through its serial interface. I monitor and debug this with an oscilloscope/...
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7k views

Altera Quartus “Warning (18236): Number of processors has not been specified…”, how to suppress?

My Altera Quartus builds show this warning... ...
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3k views

QUARTUS II: Error: Port “cg” does not exist in macro function “ADD0”

So i got 8 error while compiling this 4 bit Carry-lookahead adder. I got the above error for ports cg and cp in macro functions ADD0-ADD3. For my code check the attachments. Edit: Here i've copied the ...
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1answer
70 views

Msg about opencore in Quartus programmer

I did some changes to a design in Quartus and in Qsys. Now when I load the design to my FPGA with Quartus programmer then I get a message about opencores and that there is unlimited time. The msg was ...
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755 views

Using Altera Max II Internal Oscillator

So I'm just getting my feet wet with CPLDs, in fact I programmed a chip successfully for the first time last night (success being programming it with the correct program, not the one recovered from it ...
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58 views

Using ieee.proposed package for a dft. Quartus showing just 10 logic elements corresponding to just 10 states. [closed]

Can anyone suggest possible reasons why this might be happening? Compilation is succesful. We have analyzed the code. Can't figure out any logical errors or syntax errors(else wouldn't compile).
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1k views

Debugging FPGA VGA connection

I want to display images on the screen and to do this I used this git and this article as references. The specs of my screen are 1280x1024, including porch pixels the dimensions are 1688x1066. From ...
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459 views

FPGA flash memory programming

I'm trying to run this example because I have a DE2-115. I get this debug output then I don't know what to do ...