Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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2answers
578 views

What does the FPGA do with unreferenced I/O pins?

Here's one thats been puzzling me for a while. I have an FPGA design in Altera, driving an audio chip and programmed through its serial interface. I monitor and debug this with an oscilloscope/...
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1answer
8k views

Altera Quartus “Warning (18236): Number of processors has not been specified…”, how to suppress?

My Altera Quartus builds show this warning... ...
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1answer
3k views

QUARTUS II: Error: Port “cg” does not exist in macro function “ADD0”

So i got 8 error while compiling this 4 bit Carry-lookahead adder. I got the above error for ports cg and cp in macro functions ADD0-ADD3. For my code check the attachments. Edit: Here i've copied the ...
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1answer
80 views

Msg about opencore in Quartus programmer

I did some changes to a design in Quartus and in Qsys. Now when I load the design to my FPGA with Quartus programmer then I get a message about opencores and that there is unlimited time. The msg was ...
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1answer
809 views

Using Altera Max II Internal Oscillator

So I'm just getting my feet wet with CPLDs, in fact I programmed a chip successfully for the first time last night (success being programming it with the correct program, not the one recovered from it ...
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1answer
61 views

Using ieee.proposed package for a dft. Quartus showing just 10 logic elements corresponding to just 10 states. [closed]

Can anyone suggest possible reasons why this might be happening? Compilation is succesful. We have analyzed the code. Can't figure out any logical errors or syntax errors(else wouldn't compile).
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0answers
1k views

Debugging FPGA VGA connection

I want to display images on the screen and to do this I used this git and this article as references. The specs of my screen are 1280x1024, including porch pixels the dimensions are 1688x1066. From ...
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1answer
484 views

FPGA flash memory programming

I'm trying to run this example because I have a DE2-115. I get this debug output then I don't know what to do ...
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0answers
142 views

Unable to use the VGA port correctly, De1 Soc distorts signal depending on the output pin

This is a followup to my previous question. The code I was using, pin assigmnets and the theoretical timings for VSYNC and HSYNCH were correct. I have used to oscilloscope to look at the signals, ...
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0answers
411 views

Troubleshooting FPGA VGA connection

I have DE1 Soc development board. I have been following this youtube video in order to start casting some stuff onto the screen. I am unable to display anything on the screen at the moment unless ...
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2answers
582 views

Why would IO pins be tied to VCC or GND with 0 Ohm resistor on FPGA Dev Board?

I have a cheap Altera Cyclone II EP2C5T144C8 Dev Board and a few (4) of the IO/LVDS pins are shorted to VCC or GND as shown in the schematic segment below. The pins are also brought out to headers on ...
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1answer
305 views

Altera DE1 and DE2 - same UART?

I wonder if the Altera DE1 and DE2 have the same UART? I got access to both the DE1 and the DE2 and I see a similar question but the manual isn't specific which FPGA is applicable. UART core Altera ...
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2answers
838 views

Altera Max10 3.3V interface

Regarding Altera's MAX10 Cpld, I got some questions regarding the interface of this CPLD with 3.3V devices. I have set pins to 3.3V LVCMOS and I got this warning message in quartus: "Warning (169177):...
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2answers
452 views

Trying to find out the voltage threshold for input of a GPIO pin in an FPGA development board

I need to use a camera module along with De1-SoC development board. Camera requires 3.3V to work and it provides outputs with a 2.5V output pin. I am trying to find what is the range of voltages that ...
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1answer
322 views

How to erase a bitstream from an FFPGA using a microcontroller?

How can I erase the bitstream that is stored in flash memory from an FFPGA (Flash FPGA, e.g. MAX10) using a microcontroller or any other logic? I analyzed MAX10 documentation and still didn't find ...
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1answer
272 views

Help with Flash memory to GPIO pins on FPGA dev board

Been trying to access the FLASH memory on this DE1 dev board, but having no luck. I'm using this to interface with a Super Nintendo system, and I'm trying to read a small test ROM file stored on the ...
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2answers
555 views

Altera MAX10 CPLD initialization IO state

I'm designing a pcb with an Altera MAX10 (10M02) CPLD used to do, amongst other things, bus arbitration between several memory chips (one /CS per chip). All the memory chip are on same bus so only ...
0
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1answer
405 views

How to see the content of the SDRAM in my DE1-SOC while running (JTAG Altera cable)?

I have made a simple design in Quartus Prime, in verilog code, not using megawizard, but directly accessing the pins of the SDRAM. I am saving 2 x 16 bits binary numbers on 3 of the 4 banks of the ...
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1answer
1k views

Altera equivalent of the Xilinx Zynq UltraScale+ MPSoC [closed]

I'm new the the FPGA world. I was wondering if anybody could tell me the Altera equivalent of the Xilinx Zynq UltraScale+ MPSoC? I'm looking to buy a development board but it needs to be from Altera....
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1answer
771 views

Failing to program Cyclone IV GX device via JTAG

I just got the aforementioned device and, upon writing a simple program (it compiles) and going into Programmer, when I try to program the device with the .sof file, I see is ...
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1answer
424 views

Replacing an FT2232 chip with a custom microcontroller?

I want to make a circuit board having the capability of configuring (not sure if this is the correct term, but burning a VHDL design (svf, pof file generated by Quartus)) into Altera CPLDs and FPGAs ...
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1answer
142 views

nrf24l01 transceiver on altera board de2-115 [closed]

I'm trying to use the nrf24l01 transceiver on altera board de2-115. I would like to send a signal from the altera board using this spi module to another spi module and use the spi module on the ...
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1answer
158 views

FPGA CDMA tracking

Consider a CDMA transmitter using DSSS that is in motion with respect to the receiver (satellite). Suppose the PN code is synchronized to within one chip, i.e. acquisition has been completed. How is ...
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1answer
86 views

Any ideas for a hardware to do AM and FM modulation? [closed]

I'm trying to do some signal processing (AM/FM Modulation) for signals from 0 - 60kHz. Any recommendations for hardware? Preferably something I can use MATLAB with (or Python) as I'll most likely be ...
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1answer
4k views

Vhdl error 10327 - can't determine definition of operator “”&“” — found 0 possible definitions

I'm adjusting some vhdl code an am getting the following error: Error (10327): VHDL error at myfile.vhd(87): can't determine definition of operator ""&"" -- found 0 possible definitions The ...
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1answer
144 views

How to connect to this FPGA board?

I got this board from ebay, seemed to be a cheap deal. It is decent product from what I can say at this time. The question is, what is the most appropriate way to connect a daughter board to this ...
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1answer
206 views

Unexpected behaviour in Altera clock crossing FIFO

As far as I am aware, in a FIFO as we keep reading it will eventually become empty i.e no more data inside and its output shall become 0x0. If we keep reading it after it has become empty, we shall ...
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1answer
801 views

Output CLOCK signal to GPIO pin of CYCLONE IV E

I am new to FPGA and I am trying to send a CLOCK signal as an output of a GPIO pin of an Altera Cyclone IV E. I first made a program: ...
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1answer
94 views

Is there a method to provide physical stimulus to design inside FPGA like we do in VHDL test bench?

Basically I need to find out if there is a feature that allows one to enter stimulus into an FPGA without using things like signal generators. Altera FPGAs have a feature implemented via Quartus ...
3
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1answer
195 views

Inferring RAM ALTERA from vhdl of HDL CODER

I've generated vhdl from Simple port RAM and Dual port RAM in simulink and I tried to synthesize with Quartus 14 and 16 on Arria V and 10. The option to allow RAM for any size is ON but I don't ...
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2answers
185 views

How do I put a high-speed pulse through a digital logic chip?

I have a system which uses a 3ns pulse to trigger some downstream circuitry. When I hook up the trigger generating circuit directly to the downstream circuit, everything works fine. When I route the ...
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2answers
292 views

Can I shield noise inside an FPGA with a ground plane?

I am routing some external signals through an Altera FPGA and noise is coupling into the signals from something else in the FPGA. I have an idea to physically distance the signal route from the rest ...
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1answer
267 views

Driving dots (periods) next to digits on Terasic DE1

I have a Terasic DE1, and have imported the maker's pinout file, which contains pin assignments for HEX digits. However, I noticed that each HEX digit has a dot next to it and I cannot find any pin ...
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2answers
812 views

How to know power consumption of core FPGA

I am using a DE0-Nano board in my project. It has an Altera Cyclone IV E FPGA chip in it plus other components such as ADC, RAM, etc. When connected to a USB power supply, the DE0-Nano requires around ...
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1answer
705 views

Altera FPGA Reset System

I having a hard time understanding the best way to setup a NIOS II system with external code and the resets and clocks. One of the reasons why I'd like to figure this out is the JTAG system really ...
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2answers
803 views

How is a signal physically routed in an FPGA?

I've looked at this similar question, but it does not provide the answer I'm looking for. The documents from Xilinx also confuse me and the diagram provided in the Implementation view of the Xilinx ...
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5answers
3k views

FPGA BRAM initialization

I need to create a lot of BRAM blocks in my (Altera) design. Each one has unique memory contents, determined a priori using an algorithm. Before, I was setting a parameter for each BRAM cell to read ...
2
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1answer
282 views

Why some MAX 10 chips don't support ADC while the datasheet says they do?

I'm using an Altera MAX 10 chip 10M50SCE144C8G. I want to use its ADC. In datasheet, it says that this chip has a "Single ADC that supports 1 dedicated analog input pin and 8 dual-function pins". ...
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0answers
227 views

Not port with test bench vhdl, altera quartus prime

I wanted to test this simple VHDL model ...
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2answers
3k views

Configure (upload bitstream) to MAX10 without Altera tools using Linux

I am currently using the flash-based Altera MAX10 in designed attached to main processor which runs Linux on a custom board (the FPGA itself just implements a few peripherals; the processor running ...
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2answers
84 views

Is there a VHDL (or Quartus2-specific) compiler directive for disregarding certain lines of code for synthesis?

Is there a VHDL (or Quartus2-specific) compiler directive for disregarding certain lines of code for synthesis? I want to have certain signals going out for my simulation, but Quartus2 throws errors ...
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2answers
271 views

Adaptative Logic Module : Logic Element equivalence

I have implemented some circuitry with Quartus on a Cyclone 5 FPGA. This has be done for my master thesis. I have to justify wether the number of logic element used by my implementation is "expected" ...
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2answers
150 views

Signal alias for Altera SignalTap

In my experience, some signals disappear from SignalTap possible nodes because of optimization. I wanted to make aliases to several signals and tried using noprune so they will be available at ...
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1answer
1k views

Altera Quartus not creating symbol files

I'm looking to create a schematic block from a vhdl file in Altera'a Quartus software. I've been using File->Create/Update->Create Symbol Files for Current file The file compiles okay and I get the ...
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1answer
66 views

Effective Capacitance of an FPGA board

I am currently designing a processor on an Altera DE0 Nano and found out that the power consumption of my design may be computed by this equation: P = C * V^2 * (a * f) where P is the power ...
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1answer
348 views

Altera FPGA Configuration using Flash

During my current PCB design using Altera FPGA, I happened to come across knowledge that Altera EPCS devices are to be used for FPGA configuration. After further research, I realized the same job can ...
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3answers
2k views

Why does Altera DE2-115 board GPIO expansion header contain 5V & 3.3V power but the IO standard has no 5V?

The altera DE2-115 board user manual section 4.8 page 47 describes the GPIO expansion header. It is clear that it has 3.3V and 5V power supply. However, it later says that "The voltage level of the I/...
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1answer
106 views

Nios II system generated by Qsys looks awful (All pin are at one side). Can we make it look better?

I have tried Quartus 16.0 and 14.1. Both of them generate Nios II system that looks very awful as shown in the figure below. Is there any way to make it look better like the previous version as shown ...
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2answers
2k views

Improve Quartus partial compile or recompile time

I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. ...
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1answer
2k views

Simulating RAM in modelsim - cannot find library

I have a design in Quartus that includes an (on chip) RAM module that was created using the altera mega wizard. The wizard warns me that to simulate i need to include the ...