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Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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1answer
90 views

Does FLEX10k support SignalTap? [closed]

Can I make an embedded logic analyzer for FLEX (flex10k) devices using SignalTap by JTAG?
3
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1answer
413 views

VHDL - Subtype or type has null range

What is the meaning of the following warning (raised by Quartus)? ...
3
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1answer
639 views

VHDL Component Instantiantion Failure, Entity or Architecture wrong?

I want to design a UART receiver/transmitter and by now I already developed the receiver vhdl file but when declare and instantiate the the receiver component on my Mainboard Design I get very much ...
3
votes
1answer
193 views

Inferring RAM ALTERA from vhdl of HDL CODER

I've generated vhdl from Simple port RAM and Dual port RAM in simulink and I tried to synthesize with Quartus 14 and 16 on Arria V and 10. The option to allow RAM for any size is ON but I don't ...
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2answers
491 views

Quartus FPGA migration issues

I have an FPGA design Quartus that compiles and works correctly for a cyclone IV EP4CE15F17C8 (42% used). I'm trying to migrate same design to a smaller FPGA EP4CE10F17C8, but when changing FPGA ...
3
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1answer
801 views

How to assign clock/reset to sram in Quartus?

I'm building a system in Quartus according to this question How to upgrade a Quartus II project from SOPC to QSys? Now a part of the problem is how to assign clock/reset pins to my sram. In Quartus ...
3
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1answer
5k views

Does it always make sense to constrain an I/O port?

I am following an Altera online course on their timing analyzer software called TimeQuest. In it, their recommend that, at the very least, all clock and I/O ports be constrained. In my FPGA design, I ...
3
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1answer
403 views

Is this display broken or is it a bug?

After being fine for several days and picked up after transport, I found that one part of the Altera DE2 display is not working, you see where it is a 9 there should be an 8 so it is just like that ...
3
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1answer
848 views

Cyclone II FPGA Starter Kit Configuration Seems to be Giving Bogus Results

I've been trying to get my Cyclone II FPGA (from the Starter Kit, EP2C20) to work. I've gotten the Quartus II software to work on my Ubuntu setup and it' ALMOST working - I can write some Verilog, ...
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2answers
988 views

Altera DE1-SoC Diagram

In this link is a description of the Altera DE1-SoC kit, and the bottom of the page shows the diagram of the SoC-FPGA chip. It shows some peripherals are connected to the FPGA and other are connected ...
3
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2answers
4k views

Verilog FIR filter using FPGA

I am implementing an FIR filter in Verilog, using the DE2 board. For some reason the output out of the speakers is full of static, although it does appear to filter out some frequencies. Here is the ...
3
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2answers
2k views

Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...
2
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2answers
799 views

How is a signal physically routed in an FPGA?

I've looked at this similar question, but it does not provide the answer I'm looking for. The documents from Xilinx also confuse me and the diagram provided in the Implementation view of the Xilinx ...
2
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3answers
2k views

Why does Altera DE2-115 board GPIO expansion header contain 5V & 3.3V power but the IO standard has no 5V?

The altera DE2-115 board user manual section 4.8 page 47 describes the GPIO expansion header. It is clear that it has 3.3V and 5V power supply. However, it later says that "The voltage level of the I/...
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4answers
2k views

Custom FPGA PCB with external programming circuit

My team has verified our logic design on a development board and we are ready to move to a final prototype. Due to the nature of the device, the FPGA board must contain minimal components and be ...
2
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2answers
1k views

Merge a differential pair into one signal

I have an LVDS ADC connecting to an Altera Cyclone IV FPGA. The data pins come in 7 differential pair channels, for a total of 14 pins. Although each differential pair is physically 2 pins, my ...
2
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2answers
3k views

What is the I/O standard for the PCIe data lines?

I am entering the pin information of my FPGA design using the Altera Quartus II PinPlanner. One of the components of my design is PCIe, and I am having troubles understanding the "I/O standard" ...
2
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2answers
576 views

Why would IO pins be tied to VCC or GND with 0 Ohm resistor on FPGA Dev Board?

I have a cheap Altera Cyclone II EP2C5T144C8 Dev Board and a few (4) of the IO/LVDS pins are shorted to VCC or GND as shown in the schematic segment below. The pins are also brought out to headers on ...
2
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1answer
842 views

Why does this Verilog code produce no output on my FPGA?

I am trying to learn Verilog on my own using the DE1-Soc and the Altera university program labs. I am on the very first lab and trying to make a 4 bit-wide two input multiplexer. I wrote this verilog ...
2
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2answers
2k views

FIFO wrfull asserted when FIFO is not full

I have an issue with Altera FIFOs. It seems that the full signal wrfull gets asserted even when the FIFO is not full. My FIFOs are of size 8. The SignalTap traces ...
2
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1answer
151 views

Benefits of using Altera IP in FPGA designs?

I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
2
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1answer
801 views

Set toggle rate in Quartus II

According to this document, I need to: assign 0 MHz toggle rate to Toggle Rate assignments for the pin in the Assignment Editor to place a non-differential pin ...
2
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1answer
2k views

Trying to program an FPGA. (Altera Cyclone II)

I have got FPGA development board (Cyclone II EP2C20F484C7) and am trying to implement a simple counter program as shown below (and maybe link it to the LEDs). ...
2
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2answers
6k views

What the FPGA dev board to choose: Xilinx or Altera? [closed]

I'm very new to programmable logic world and have never worked with any HDL languages, but I certainly want to get started with FPGA. At the moment the goal is to develop/simulate simple 8bit CPU and ...
2
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3answers
363 views

View more than 100 worst-case paths in Quartus II

I am using Quartus II to compile Verilog for my FPGA project. For debug, I use SignalTap, which introduces a lot of timing warnings. When I go to the TimeQuest report, and look at the worst-case ...
2
votes
1answer
3k views

Quartus II ignoring synthesis attribute noprune

There is a register in my design that I am using for debug purposes with zero fan-out. Since it isn't driving any logic, the synthesizer optimizes it away. However, as far as my knowledge goes, ...
2
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1answer
344 views

FPGA project sanity check, PCIE and video processeing

I have an Altera DE4 education FPGA that I'd like to use for video processing... But the thing doesn't have many ports to work with, and I don't have the funds to purchase any daughter boards. My ...
2
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2answers
84 views

FPGA Routing general criteria

I was implementing a simple circuit on an FPGA using Quartus (6 logical elements) and I noticed that the block containing the 6 cells is located near the perimeter. Is this a general criterion? The ...
2
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1answer
364 views

Altera's MAX10 remote update

I am going to implement a MAX10 remote update. Unfortunately, in Altera's documents i only see a NIOS implementation and everything looks very big and too complex. Also i already have a reliable ...
2
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1answer
4k views

How do I reset an FPGA development board to its factory settings?

I have programmed an Altera board in configuration mode so that it runs my program when booted up. Now I want to revert it back to factory configuration. How do I do that?
2
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1answer
3k views

Memory logic array blocks VS M20K

I am looking at the Altera Stratix V overview Table 1. In it, they distinguish two types of memories: M20K memory blocks Memory logic array blocks (MLAB) What are ...
2
votes
1answer
5k views

How can I avoid “Minimum Pulse Width” slack violations in Quartus FPGA synthesis?

I am synthesizing a toy application on DE2, but I hit a timing problem (despite every inputs and outputs are clocked in my design). These violations are related to "minimum pulse width"... How can I ...
2
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1answer
2k views

My design is not meeting timing. What can I do?

I am using the Altera Quartus II software to compile Verilog for a Cyclone IV FPGA. In my case, the FPGA is fixed; I cannot get a faster one. Now one isolated module in my design, which deals with ...
2
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2answers
4k views

UART core Altera De2

I have to implement a rs232 receiver for my project. Does any one have any idea on how do I start learning / implementing this. Do i have to use the nios ii software or just implement it using verilog ...
2
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1answer
215 views

What options exist to verify Avalon-MM slave component?

I am writing an Avalon-MM slave. It shall connect to Nios II as master device. What options exist to write testbench for it? I must be sure that an Avalon-MM master can correctly read/write it. I ...
2
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1answer
676 views

Using the ROM megafunction in VHDL code

I have created a ROM megafunction using the MegaWizard plug-in Manager. This created a new file which I named rom.vhd. My code: ...
2
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1answer
2k views

How to wire a system for Nios 2 in Qsys?

I've managed to reduce the number of errors but I still have some: ...
2
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1answer
3k views

Is De0-Nano an alternative to Arduino/RaspberryPi?

Arduino and Raspberry Pi are touted as ideal programming boards for beginners and hobbyists. Could De0-Nano fit in that role, too? What does Arduino or RaspberryPi have that De0-Nano does not?
2
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2answers
1k views

Alternate programming software to program Altera CPLD

I am using a Altera MAX V CPLD. When I try to program the CPLD using QUARTUS II, it is reading the device ID and silicon ID correctly, but it failing during verification. I tried to isolate the ...
2
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2answers
300 views

FPGA Jtag Hooking to User Logic

After some primer reading on jtag it looks to be a nifty means to test a FPGA logic design in a consistent and sustainable way. Let's use altera max 10 as an example. I've read this MAX 10 JTAG ...
2
votes
1answer
793 views

Error (209015): Can't configure device. Expected JTAG ID code 0x020B10DD for device 1, but found JTAG ID code 0x000210DD

I bought from ebay Altera Cyclone II EP2C5T144 development board. It came with USB Blaster. I'm using Quartus II 13.0sp1. FPGA is programmed with default settings as it should be (flashing onboard ...
2
votes
1answer
281 views

Why some MAX 10 chips don't support ADC while the datasheet says they do?

I'm using an Altera MAX 10 chip 10M50SCE144C8G. I want to use its ADC. In datasheet, it says that this chip has a "Single ADC that supports 1 dedicated analog input pin and 8 dual-function pins". ...
2
votes
1answer
191 views

CycloneIV PCIe hard IP fixedclk_serdes generation

I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says ...
2
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3answers
11k views

How to define a clock in Quartus II?

I have this piece of code here: ...
2
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1answer
1k views

Cyclone V FPGA SocKit - trying to use LCD from FPGA

I'm trying to use the LCD screen on a SocKit board with a Cyclone V FPGA. However, in the documentation I see that the chip is divided into an HPS and the FPGA and the LCD seems to be connected only ...
2
votes
1answer
470 views

Altera Quartus - How do I simulate a different Entity

I tested the first entity in my project successfully. Now, when I try to create a Vector Waveform File for my second entity, it only lets me add the pins of my first entity. I did set my new entity ...
2
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1answer
771 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
2
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1answer
1k views

FDCE flip flop primitive on altera quartus?

I would like to know the altera quartus primitive equivalent to the FDCE flip flop on Xilinx ISE. I think that DFFE primitive might work however I am not sure about the CE and CLR pins equivalency. ...
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2answers
1k views

FPGA maximum frequency : limiting factor

I would like to know which in general may limit the maximum clock frequency of a circuit implemented in FPGA. In the specific case I am building some FIR filters using Quartus and simulating them on a ...
1
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2answers
545 views

Verilog: is connection without wires possible?

I am sorry to ask this question, which I believe is very basic, but I cannot find an answer. The following example clearly works. But I would like to omit the declaration of the wires ay and by. <...