Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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CycloneIV PCIe hard IP fixedclk_serdes generation

I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says ...
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3answers
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How to define a clock in Quartus II?

I have this piece of code here: ...
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1answer
1k views

Cyclone V FPGA SocKit - trying to use LCD from FPGA

I'm trying to use the LCD screen on a SocKit board with a Cyclone V FPGA. However, in the documentation I see that the chip is divided into an HPS and the FPGA and the LCD seems to be connected only ...
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1answer
512 views

Altera Quartus - How do I simulate a different Entity

I tested the first entity in my project successfully. Now, when I try to create a Vector Waveform File for my second entity, it only lets me add the pins of my first entity. I did set my new entity ...
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Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...
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1answer
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FDCE flip flop primitive on altera quartus?

I would like to know the altera quartus primitive equivalent to the FDCE flip flop on Xilinx ISE. I think that DFFE primitive might work however I am not sure about the CE and CLR pins equivalency. ...
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Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
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2answers
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FPGA maximum frequency : limiting factor

I would like to know which in general may limit the maximum clock frequency of a circuit implemented in FPGA. In the specific case I am building some FIR filters using Quartus and simulating them on a ...
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3answers
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sine wave in FPGA

I am supposed to generate a sine wave in cyclone 2 altera? I get that I have to store the values in LUT or some memory. I think cyclone 2 uses a 4 input LUT. I am not sure how I should go on with the ...
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650 views

Verilog: is connection without wires possible?

I am sorry to ask this question, which I believe is very basic, but I cannot find an answer. The following example clearly works. But I would like to omit the declaration of the wires ay and by. <...
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Do I need to solder on my DE2 board to replace a broken segment?

I've already posted a question here about this when I realized that all things were not right with my Altera DE2 board: Is this display broken or is it a bug? After verifying that the segment indeed ...
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5answers
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Altera DE2 interfacing with analog sensor

Can Altera GPIO pins read the analog output of a light sensor? The light sensor output is analog and I want the Altera to turn an LED on whenever the signal of the sensor is greater than some specific ...
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DE2 Expansion Header Mystery

I recently received an Atera DE2 board with a Cyclone II FPGA. I have been experimenting with the expansion headers and I am having trouble understanding why my daughter card is not receiving any ...
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Altera has created EPCS and EPCQ devices, can only these be used to store FPGA configuration data?

FPGA configuration data must be stored in external non-volatile memory. Can we use just any flash memory or only specific types? What about EEPROMs or any other nonvolatile memory device? Edit: I am ...
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FPGA SPI slave not working well

I'm tring to integrate a SPI Slave in VHDL (opencores) http://opencores.org/project,spi_master_slave the idea is to interface a Microcontroller and an FPGA I'm Using Quartus.. more info: ...
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879 views

quartus signaltap not accurate?

I am using Quartus SignalTap to debug my FPGA design: I always been persuaded SignalTap is not accurate !! This is what i found: I monitor the reset signal with SignalTap :Reset toggles around, ...
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458 views

I2S output in VHDL

I am making an I2S output in VHDL for a project. This is my first project using VHDL and the problem may be my basic VHDL understanding. This is my code: ...
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5answers
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FPGA BRAM initialization

I need to create a lot of BRAM blocks in my (Altera) design. Each one has unique memory contents, determined a priori using an algorithm. Before, I was setting a parameter for each BRAM cell to read ...
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2answers
9k views

How to read firmware from Altera's FPGA (Cyclone IV) with USB Blaster?

I'm starting to investigate Altera's Cyclone IV FPGA to use in my projects. Now I borrowed from neighboring company a real device with USB Baster Rev.C. I'd try to use one instead of evaluation board ...
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3answers
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PCI-Express and FPGA Development Boards

I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
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1answer
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Internal fmax of FPGA program

When I compile my project in QUARTUS, it provides me with information about "internal fmax" ...
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1answer
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Starting FPGA project on Xilinx - trouble with some basics! Coming from Altera background

I'm just looking for a bit of help getting started with Xilinx FPGAs. Specifically, I'm looking for the analogue to Altera's HEX and ...
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1answer
682 views

Upgrading from Altera DE2 to DE2-115

I got a DE2 board that failed so they sent me a replacement board which is the finer DE2-115. But my config file (.sof) is not forward compatible. How can I migrate existing projects that I have for ...
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Can the same net-list file be used for ASIC design flow as well as FPGA design flow?

I have mostly worked on front-end part and don't know much about back-end stuff. I have gone through the reading about the various abstraction levels of design flows of FPGAs and ASICs. I was ...
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199 views

How are FPGA's configured when operating independently?

I have a DE0 Altera board with a Cyclone III FPGA from my VHDL class, and I want to learn how to use it in an independent device. Right now I have a Raspberry Pi and wanted to try playing with using ...
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1answer
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Solid color display on VGA not working

I'm trying to get VGA working on my Altera DE0 board using Verilog, but haven't had much luck. It has the same pins as a normal VGA interface except red, green, and blue are all 4 bits each. Here is ...
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1answer
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How to upgrade a Quartus II project from SOPC to QSys?

I don't understand my errors in QSys, can you help me? I'm trying to go through this exercise: http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf In Qsys when I connect the components I ...
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1answer
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Can't synthesize my VHDL in Qsys

I'm trying to make a module with VHDL for my DE2 where the easy thing ("Hello World") is nearly impossible. The bakground is that I'm trying to run Hello World: https://stackoverflow.com/questions/...
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1answer
242 views

Adjustable clock in HDL

I need to generate an adjustable clock in hdl (verilog) on altera cyclone II fpga using signal probes (blocks that can change their output value through jtag - there is no need to recompile the code). ...
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2answers
992 views

Quartus - Export Verilog as Gate Level (FPGA)

I've got a project in Altera's Quartus II software which is written in Verilog. I'm curious if anyone here has figured out how to export the Verilog as a gate level netlist. I'd like to simulate the ...
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2answers
120 views

Variable Bit shift within 1 Clock Cycle (Verilog)

I have a 64-bit register that I would like to right shift n times, with 0<=n<=64, implemented as such always_ff data[63:0] <= (data >> n); I ...
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1answer
400 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...
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1answer
416 views

Is it possible to find the critical path in specific part of the design?

I have written RTL description of a circuit in VHDL which is hierarchical and I am using Altera Quartus II; my design meets timing. I had set 50MHz clock frequency (20ns period) constraint using ...
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Altera Max10 3.3V interface

Regarding Altera's MAX10 Cpld, I got some questions regarding the interface of this CPLD with 3.3V devices. I have set pins to 3.3V LVCMOS and I got this warning message in quartus: "Warning (...
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693 views

Trying to find out the voltage threshold for input of a GPIO pin in an FPGA development board

I need to use a camera module along with De1-SoC development board. Camera requires 3.3V to work and it provides outputs with a 2.5V output pin. I am trying to find what is the range of voltages that ...
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1answer
291 views

Driving dots (periods) next to digits on Terasic DE1

I have a Terasic DE1, and have imported the maker's pinout file, which contains pin assignments for HEX digits. However, I noticed that each HEX digit has a dot next to it and I cannot find any pin ...
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393 views

Altera Cyclone IV FPGA and jtag debugging

G'day All, Is there a method comparable to jtag debugging on a microcontroller (ATMEGA32) for the Cyclone IV family of FPGA? I am trying to debug my Verilog code so ideally I just want to be able to ...
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1answer
5k views

Illegal bus range or name for logic function for instance “instMyAdder” of type 4 Bit Adder

I am using QuartusII for designing a Four bit ripple carry adder. I keep getting this error: ...
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1answer
237 views

Why build errors when connecting timers in Quartus ii?

I use the Nios 2 IDE from Altera with the Altera DE2. I add a file Functions.c with code that needs a timer e.g. ...
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1answer
3k views

How to install Altera USB master driver for Windows 8 (64 bit)?

I am trying to connect Altera Stratix 4 board with my PC in which Quartus 11.0 is per-installed. But my PC is not detecting USB JTAG connection from the board. What I am guessing is that, this ...
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1answer
1k views

Quartus II: Suppress warnings by Verilog module

In my FPGA project I use the Quartus II PCIe megafunction. The number of warning messages this Altera library module produces baffles me. Is there a way to have Quartus II suppress all the warnings ...
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1answer
844 views

How to find MAX V CPLD pinout

Can someone please explain how to find the pin-out of a 5M80Z CPLD device. The documentation on this page shows the names of the pins but does not indicate the pin numbers. I have not encountered ...
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399 views

Enabling uClinux to run on Altera DE2-115?

I'm trying to learn Qsys and Quartus II to define a system that can run linux according to this document: http://uuoc.org/uClinux_nios2_custom_hardware.pdf But I'm running into problem as the ...
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PCB design for Altera FPGA

I want to design a brand new PCB board for Altera Cyclone III FPGA with 144 IO pins, such as ep3c25e144. However, I am clueless of how the process can be done in Eagle Cadsoft. Even when they ...
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How to make Quartus II find the Altera DE2 board?

I use Quartus II web edition and using that driver my computer can find the card: And the card appears in the device manager so it indeed looks correct so far. But when I start Quartus Programmer ...
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1answer
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Setting Pin Assignments For Quartus

So I have written a simple Verilog module which works well in the ModelSim emulator. I would like to now program my Cyclone 10 Dev board to perform this simple task, but I need to set up the pin ...
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169 views

Is it possible to add an existing IP variant to a Platform Designer/Qsys system through TCL?

I have a .ip file that contains a parameterized component which I'd like to use in my Qsys system. I can add the component via the GUI but I would like to be able to add it via TCL or another ...
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204 views

What is the difference between words and symbols in Qsys, how to know which one to use?

Qsys offers options to select address unit or address type. All I know is that my custom components shall write 32 or 64 bit data to a specific address and it is not byte addressable. How do I decide ...
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Verifying custom Qsys component?

A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also. These copies ...

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