Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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413 views

Do I need to solder on my DE2 board to replace a broken segment?

I've already posted a question here about this when I realized that all things were not right with my Altera DE2 board: Is this display broken or is it a bug? After verifying that the segment indeed ...
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5answers
2k views

Altera DE2 interfacing with analog sensor

Can Altera GPIO pins read the analog output of a light sensor? The light sensor output is analog and I want the Altera to turn an LED on whenever the signal of the sensor is greater than some specific ...
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1k views

DE2 Expansion Header Mystery

I recently received an Atera DE2 board with a Cyclone II FPGA. I have been experimenting with the expansion headers and I am having trouble understanding why my daughter card is not receiving any ...
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410 views

Altera has created EPCS and EPCQ devices, can only these be used to store FPGA configuration data?

FPGA configuration data must be stored in external non-volatile memory. Can we use just any flash memory or only specific types? What about EEPROMs or any other nonvolatile memory device? Edit: I am ...
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3answers
3k views

sine wave in FPGA

I am supposed to generate a sine wave in cyclone 2 altera? I get that I have to store the values in LUT or some memory. I think cyclone 2 uses a 4 input LUT. I am not sure how I should go on with the ...
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1k views

FPGA SPI slave not working well

I'm tring to integrate a SPI Slave in VHDL (opencores) http://opencores.org/project,spi_master_slave the idea is to interface a Microcontroller and an FPGA I'm Using Quartus.. more info: ...
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809 views

quartus signaltap not accurate?

I am using Quartus SignalTap to debug my FPGA design: I always been persuaded SignalTap is not accurate !! This is what i found: I monitor the reset signal with SignalTap :Reset toggles around, ...
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1answer
367 views

I2S output in VHDL

I am making an I2S output in VHDL for a project. This is my first project using VHDL and the problem may be my basic VHDL understanding. This is my code: ...
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3k views

FPGA BRAM initialization

I need to create a lot of BRAM blocks in my (Altera) design. Each one has unique memory contents, determined a priori using an algorithm. Before, I was setting a parameter for each BRAM cell to read ...
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7k views

How to read firmware from Altera's FPGA (Cyclone IV) with USB Blaster?

I'm starting to investigate Altera's Cyclone IV FPGA to use in my projects. Now I borrowed from neighboring company a real device with USB Baster Rev.C. I'd try to use one instead of evaluation board ...
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3answers
1k views

PCI-Express and FPGA Development Boards

I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
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1answer
180 views

Starting FPGA project on Xilinx - trouble with some basics! Coming from Altera background

I'm just looking for a bit of help getting started with Xilinx FPGAs. Specifically, I'm looking for the analogue to Altera's HEX and ...
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669 views

Upgrading from Altera DE2 to DE2-115

I got a DE2 board that failed so they sent me a replacement board which is the finer DE2-115. But my config file (.sof) is not forward compatible. How can I migrate existing projects that I have for ...
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1answer
350 views

Altera Cyclone IV PLL: What limits the available multiplication/division factor values

Altera Cyclone IV EP4CE6E22 with a 50 MHz input clock. I want to get 24 MHz out of the ALTPLL megafunction. The requested multiplication/division settings are 12/25 but actual settings turn out to be ...
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217 views
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270 views

Can the same net-list file be used for ASIC design flow as well as FPGA design flow?

I have mostly worked on front-end part and don't know much about back-end stuff. I have gone through the reading about the various abstraction levels of design flows of FPGAs and ASICs. I was ...
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1answer
3k views

Solid color display on VGA not working

I'm trying to get VGA working on my Altera DE0 board using Verilog, but haven't had much luck. It has the same pins as a normal VGA interface except red, green, and blue are all 4 bits each. Here is ...
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1answer
1k views

Internal fmax of FPGA program

When I compile my project in QUARTUS, it provides me with information about "internal fmax" ...
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1answer
4k views

How to upgrade a Quartus II project from SOPC to QSys?

I don't understand my errors in QSys, can you help me? I'm trying to go through this exercise: http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf In Qsys when I connect the components I ...
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1answer
3k views

Can't synthesize my VHDL in Qsys

I'm trying to make a module with VHDL for my DE2 where the easy thing ("Hello World") is nearly impossible. The bakground is that I'm trying to run Hello World: https://stackoverflow.com/questions/...
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1answer
234 views

Adjustable clock in HDL

I need to generate an adjustable clock in hdl (verilog) on altera cyclone II fpga using signal probes (blocks that can change their output value through jtag - there is no need to recompile the code). ...
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2answers
963 views

Quartus - Export Verilog as Gate Level (FPGA)

I've got a project in Altera's Quartus II software which is written in Verilog. I'm curious if anyone here has figured out how to export the Verilog as a gate level netlist. I'd like to simulate the ...
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1answer
292 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...
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1answer
307 views

Is it possible to find the critical path in specific part of the design?

I have written RTL description of a circuit in VHDL which is hierarchical and I am using Altera Quartus II; my design meets timing. I had set 50MHz clock frequency (20ns period) constraint using ...
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751 views

Altera Max10 3.3V interface

Regarding Altera's MAX10 Cpld, I got some questions regarding the interface of this CPLD with 3.3V devices. I have set pins to 3.3V LVCMOS and I got this warning message in quartus: "Warning (169177):...
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1answer
261 views

Driving dots (periods) next to digits on Terasic DE1

I have a Terasic DE1, and have imported the maker's pinout file, which contains pin assignments for HEX digits. However, I noticed that each HEX digit has a dot next to it and I cannot find any pin ...
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2answers
340 views

Altera Cyclone IV FPGA and jtag debugging

G'day All, Is there a method comparable to jtag debugging on a microcontroller (ATMEGA32) for the Cyclone IV family of FPGA? I am trying to debug my Verilog code so ideally I just want to be able to ...
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1answer
4k views

Illegal bus range or name for logic function for instance “instMyAdder” of type 4 Bit Adder

I am using QuartusII for designing a Four bit ripple carry adder. I keep getting this error: ...
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1answer
209 views

Why build errors when connecting timers in Quartus ii?

I use the Nios 2 IDE from Altera with the Altera DE2. I add a file Functions.c with code that needs a timer e.g. ...
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1answer
3k views

How to install Altera USB master driver for Windows 8 (64 bit)?

I am trying to connect Altera Stratix 4 board with my PC in which Quartus 11.0 is per-installed. But my PC is not detecting USB JTAG connection from the board. What I am guessing is that, this ...
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1answer
910 views

Quartus II: Suppress warnings by Verilog module

In my FPGA project I use the Quartus II PCIe megafunction. The number of warning messages this Altera library module produces baffles me. Is there a way to have Quartus II suppress all the warnings ...
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1answer
746 views

How to find MAX V CPLD pinout

Can someone please explain how to find the pin-out of a 5M80Z CPLD device. The documentation on this page shows the names of the pins but does not indicate the pin numbers. I have not encountered ...
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1answer
389 views

Enabling uClinux to run on Altera DE2-115?

I'm trying to learn Qsys and Quartus II to define a system that can run linux according to this document: http://uuoc.org/uClinux_nios2_custom_hardware.pdf But I'm running into problem as the ...
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2answers
2k views

PCB design for Altera FPGA

I want to design a brand new PCB board for Altera Cyclone III FPGA with 144 IO pins, such as ep3c25e144. However, I am clueless of how the process can be done in Eagle Cadsoft. Even when they ...
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3answers
7k views

How to make Quartus II find the Altera DE2 board?

I use Quartus II web edition and using that driver my computer can find the card: And the card appears in the device manager so it indeed looks correct so far. But when I start Quartus Programmer ...
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1answer
32 views

What is the difference between words and symbols in Qsys, how to know which one to use?

Qsys offers options to select address unit or address type. All I know is that my custom components shall write 32 or 64 bit data to a specific address and it is not byte addressable. How do I decide ...
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1answer
40 views

Verifying custom Qsys component?

A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also. These copies ...
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2answers
98 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...
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1answer
226 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...
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1answer
99 views

How can I check if an IO pin is dead?

I've been playing around with I2C for a couple days now with a DE10-Nano dev board: I'm implementing an I2C master in CLaSH so that I can talk to the HDMI encoder chip, but for now I'm talking to an ...
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310 views

Program FPGA using STM32

I am interested in using an STM32 to flash an sof or pof file onto a Cyclone IV FPGA. The sof/pof will be stored in SPI flash memory, and the plan is to use the STM32 as a programmer. I haven't been ...
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1answer
478 views

MAX10 .pof file issue, quartus II and usb blaster

After a MAX10 board revision. When programming the MAX10 with .pof, the MAX10 board do not start when power-on or after .pof programming is completed. However, normal operation is achieved when ...
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1answer
483 views

How does one read a FIFO outside Qsys system using Nios II?

There is a FIFO block that has Avalon interface compatible with Qsys that can be used in Qsys systems. However, in my case there is an external block that generates data that is to be read by a Nios ...
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1answer
157 views

FPGA CDMA tracking

Consider a CDMA transmitter using DSSS that is in motion with respect to the receiver (satellite). Suppose the PN code is synchronized to within one chip, i.e. acquisition has been completed. How is ...
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2answers
150 views

Signal alias for Altera SignalTap

In my experience, some signals disappear from SignalTap possible nodes because of optimization. I wanted to make aliases to several signals and tried using noprune so they will be available at ...
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1answer
64 views

Effective Capacitance of an FPGA board

I am currently designing a processor on an Altera DE0 Nano and found out that the power consumption of my design may be computed by this equation: P = C * V^2 * (a * f) where P is the power ...
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1answer
346 views

Altera FPGA Configuration using Flash

During my current PCB design using Altera FPGA, I happened to come across knowledge that Altera EPCS devices are to be used for FPGA configuration. After further research, I realized the same job can ...
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1answer
184 views

What is configuration image zero and one?

Currently, I am working in Broadwell-DE based module design. In this circuit, There is an FPGA (p/n :10M02SCU169C8G ) Please see the configuration user guide added. ( ref page 14) https://www.altera....
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173 views

Implementation of NIOS Softcore alongwith HDL modules on Aletra Cyclone IVGX

My question is not on 'how can' but 'if can'. So I believe people with sufficient experience on any FPGA family might be able to help me out here. Problem Statement: I need to model a very basic ...
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1answer
813 views

Verilog SPI module functioning in unpredicted ways

I am currently trying to implement a simple SPI Master module in Verilog using Quartus Prime Lite V15.1.0 Build 185 for compilation and Simulation Waveform Editor as my simulation tool. The module has ...