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Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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Quartus/SignalTap: Is there an equivalent to Xilinx's ICON, VIO, ILA IP-Cores in Altera's SignalTap?

Xilinx offers an Integrated Logic Analyzer (ILA) / called ChipScope. Altera's Quartus II comes with SignalTap - an equivalent solution. As an advance user\$^1\$, I'm using ChipScope as pre-compiled ...
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172 views

How are FPGA's configured when operating independently?

I have a DE0 Altera board with a Cyclone III FPGA from my VHDL class, and I want to learn how to use it in an independent device. Right now I have a Raspberry Pi and wanted to try playing with using ...
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758 views

ALU once compiled giving errors of missing source signal?

This is ALU, not sure whether if it is all properly connected but all blocks are the correct ones. This has 3 4 bit latch registers, 5 2:1 ultiplexers, 4 4 bit adders. Can anyone help me? The problems ...
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172 views

Using a Counter to Determine next MSB position in polynomial division

I am working on implementing a polynomial divider the operation is as follows: Check MSB of Numerator: if 1 XOR with Denom then shift Denom right if 0 Num is the same and Denom also shift right When ...
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2answers
984 views

FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
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1answer
1k views

Leaving target processor paused nios ii multiprocessor application

I m using the multiprocessor tutorial, to have a MPSOC application, but when i finish all steps and running the nios application I have this message in the terminal, ...
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1answer
233 views

Different Altera DE2 boards do not behave the same way

I have a simple VHDL file which can be simulated correctly and that synthesizes with Quartus II-11.0 (web edition). I can interact with switches,leds, seven segments and push buttons. My problem is ...
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1answer
147 views

Avalon-ST interface properties of 10G MAC MegaFunction

I have an instance of the 10G MAC MegaFunction that contains an Avalon-ST interface. Reading through the Avalon-ST specification, I see that every Avalon-ST instance has "interface properties" (see ...
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1answer
83 views

Raw programming of an Altera FPGA

I have an Altera Cyclone IV FPGA (for ie) and my question is: is it possible a raw programming of the FPGA? Is it possible to set "manually" the gates for making experiments? Thank you
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43 views

dual purpose pins on max 10 fpga

I am breaking into the world of FPGA development at my internship for an aerospace company. I keep coming across the term "Dual-Purpose Pin" in the documentation for the Max 10 family of FPGA devices. ...
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1answer
36 views

Is it possible to add an existing IP variant to a Platform Designer/Qsys system through TCL?

I have a .ip file that contains a parameterized component which I'd like to use in my Qsys system. I can add the component via the GUI but I would like to be able to add it via TCL or another ...
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48 views

Two-Terminal Passive Analog Component Tester Using the DE1-SoC Development Board

I am having hard time understanding this problem. I have to draw a Level 1 block diagram for this system. I really appreciated it if somebody can help me. I am new to DE1-Soc. use the Intel DE1-SoC ...
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1answer
77 views

How does FPGA knows the configuraton file is present in Flash memory during bootup?

Which areas in flash memory are scanned during bootup to make sure that there is configuration file present in the external flash memory?
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1answer
67 views

register enable line usage in `case` block (verilog synthesis for altera cpld)

I have the following in a verilog design aimed at an altera CPLD (currently targeting EPM240, although the target device isn't set in stone): ...
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1answer
490 views

How do I implement a communications interface to an Altera FPGA?

I have a DE1-SoC with some data coming in through an A-D Card. After digital processing I want to transmit data to a host PC for records. I'm trying to figure out the easiest way to go about this. I'...
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1answer
310 views

Quartus Prime Qsys HPS(Hard Processor System) Error

I'm trying to generate a system including HPS(Hard Processor System) of the Cyclone V SoC in Quartus Prime Qsys. At the "Generate HDL" stage I got the following errors. I'm not expecting all the error ...
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1k views

Debugging FPGA VGA connection

I want to display images on the screen and to do this I used this git and this article as references. The specs of my screen are 1280x1024, including porch pixels the dimensions are 1688x1066. From ...
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399 views

Troubleshooting FPGA VGA connection

I have DE1 Soc development board. I have been following this youtube video in order to start casting some stuff onto the screen. I am unable to display anything on the screen at the moment unless ...
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1answer
554 views

Design of carry chain on Cyclone IV

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "cin" goes high, signal starts to ...
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2answers
1k views

Reading ADC using Altera DE2 Board (Beginner)

Question: Would it be possible and feasible for a beginner to use Verilog HDL and an Altera DE2 board to read input from a weight sensor's HX711 ADC (see below), and if so: What kind of data am I ...
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1answer
128 views

Modeling FPGA logic element responses

I'm working on modeling a circuit implemented on an FPGA, and the fundamental question I keep running into is this: what is a logic element? I need to be able to model the temporal response of the ...
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1k views

Bidirectional FPGA implementations (parallel ADC)

New FPGA convert here. I am trying to interface with a parallel ADC as part of a data acquisition project. The pins on the ADC are used for both input and output (not simultaneously). Therefore, I ...
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2answers
545 views

Simple FPGA serial communication not working

FPGA board (manual) USB-to-RS232 cable (controller) synthesis reports I created a simple schematic which shorts the TXD and RXD pins according to the manual. However, when I use RealTerm to send ...
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976 views

Shematics of the BeMicro CV eval board from Arrow

Where can I find the complete schematics of the board? Arrow sells an ultra low cost FPGA platform with a Cyclone V device on it for around 30$. Ok, for that price it has the bear minimum: 2 buttons, ...
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1k views

Altera ModelSim simulating PLL

In my design, I make use of the ATLPLL Library/IP which is to convert the clock frequency accordingly for my design. I am Using De0-Nano board for my project which has cyclone IV FPGA. The ATLPLL ...
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183 views

FPGA Synthesis = 0 LE (Altera Quartus II)

Just starting with FPGAs and stuck with a synthesis issue. Basically, the circuit I am designing is coming out with 0 logic units and 0 for all resources except for the pins assignment. The code ...
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422 views

in what order does a VHDL program run in an FPGA

I am trying to wrap my head around exactly what goes on in an FPGA when I program it, specifically using VHDL. I know all code outside processes run concurrently but what about processes in different ...
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1answer
201 views

Cyclone V data corruption at high frequency

I'm currently trying to implement a FPGA design using a 325 MHz clock, which writes to the SDRAM Controller of a Cyclone V 5CSEBA6U23I7 (Speed Grade 7). When running my IP Core with 2 MHz everything ...
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1answer
2k views

“expecting endmodule” error, can't understand why?

I'm trying to build a counter with a-sync reset, that will be shown on the 7-segment display on the fpga board. I saw a few posts about my problem: "near text "if"; expecting endmodule" But still ...
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2answers
627 views

usb interface for fpga & Nios

I need some advice: i want to connect an altera FPGA to a computer by USB interface. i want to avoid placing an microcontroller in my board.. i want to set a nios II to "talk" to the computer i only ...
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2answers
3k views

Code to add two 4bit numbers in verilog doesn't work

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... ...
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1answer
77 views

altera FPGA acting like OR gate when programed as AND gate

I'm new to altera fpga , I've bought development board based on EP4CE6E22 cyclon IV and tryed to program it with basic program in quartus environment ...
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420 views

Replacing an FT2232 chip with a custom microcontroller?

I want to make a circuit board having the capability of configuring (not sure if this is the correct term, but burning a VHDL design (svf, pof file generated by Quartus)) into Altera CPLDs and FPGAs ...
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84 views

Is there a VHDL (or Quartus2-specific) compiler directive for disregarding certain lines of code for synthesis?

Is there a VHDL (or Quartus2-specific) compiler directive for disregarding certain lines of code for synthesis? I want to have certain signals going out for my simulation, but Quartus2 throws errors ...
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70 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...
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71 views

Nios 2 softcore IP

The SOPC board contains an Altera Stratix Processor, but the description mentions use of an Alteras NIOS II soft core IP. If its a soft core then why are we using a Stratix processor. PIC from: ...
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259 views

routing jtag signals through an FPGA

I am routing a JTAG signals through an Altera FPGA to a TI MCU. The signals are TMS, TCK, TDO...
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1answer
205 views

Unexpected behaviour in Altera clock crossing FIFO

As far as I am aware, in a FIFO as we keep reading it will eventually become empty i.e no more data inside and its output shall become 0x0. If we keep reading it after it has become empty, we shall ...
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1answer
310 views

Altera Quartus. Technology Map Viewer looks different from expected

Recently, I've installed Altera Quartus 15.1 and now follow the "getting started" instructions, you can read it here. At the step: to see the resulting circuit go to Tools →Netlist Viewers →Technology ...
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568 views

Synthesizeable D Flip flop for FPGA

Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite. Starting with a simple D flip flop, I face the ...
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1answer
291 views

Cyclone V LVTTL GPIO Termination

On the DE1-SoC (from Terasic) schematic, I found 47 Ohm series resistors connected to GPIOs, they are using 3.3V VCCIO. The cyclone V datasheet show that no external termination is required as shown ...
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2answers
7k views

verilog error left-hand side of assignment must have a variable data type

I have a verilog as module I get the error Error (10137): Verilog HDL Procedural Assignment error object "result" on ...
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1answer
4k views

Help with resolving warning “inferring latch(es) for signal or variable ”..“, which holds its previous value in one or more paths through the process”

Below is the code for my branch unit implementation. This unit calculates the jump destination address and writes it into the PC register. There are a few different types of jumps, etc, standard ...
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1answer
4k views

50 MHz FPGA (Cyclone IV @ DE0-Nano) and 60 MHz input from FT2232H

I want to read data from FT2232H used in an FT245 style synchronous FIFO mode (http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf p.27) with DE0-Nano FPGA board: ...
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1answer
873 views

Quartus II - SignalTap II Getting the Period of Sampled Data

I am working on a VHDL project where I am trying to make an LCD controller. I have been trying to get the period of my scaled clocks using Signal Tap, however the time bar does not show the time ...
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2answers
4k views

Why no JTAG connection?

This used to work before I installed Quartus v10 to ensure backward-compatibility. Now I get no hardware found in Quartus both v13 and v10. The USB-Blaster used to show up, then I installed Quartus ...
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438 views

symbols for ep3c5e144 and ep3c25e144 in Eagle

I am using ep3c5e144 to design a PCB board. Sadly, in Eagle I cant find the exact library and symbol for this device, but only its near relative ep3c25e144. I have some questions: How different is ...
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256 views

Why is carry on for an adder that is simply on? [closed]

I've understood that the behaviour is correct when I make a simple adder: But why does carry on light up just because I switch on the + operation for my 4-bit system? http://www.ict.kth.se/courses/...
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2answers
663 views

Reading the configuration array of a MAX7000 PLD

Well, I have a little problem in my hands, I need to clone an Altera Max EPM7128ELC84, luckily the PLD comes in a socketable PLCC84 package and has a JTAG interface. Now my question: what approach ...
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1answer
62 views

VHDL: case when using constants constructs

I'm having some trouble with the following statement ...