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Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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How to have an in-system check in an FPGA based system that it has been reset?

I have a system based on Altera's MAX10 device that is doing the following tasks: receives the data and stores it on an on-chip flash memory only once. reads all the data from on-chip flash, stores ...
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112 views

What is the minimal schematic (needed capactiors/resistors) to use FPGA Altera Cyclone 4 EP4CE6E22C8N? [closed]

I can't find any information about how wire the Cyclone 4 FPGA. I do not want to use development boards.
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141 views

Altera HDL design techniques

Some many years ago my teacher taught us to program Xilinx Spartan II development board. He taught us to think of the hardware element we wanted to invoke (logic gate, adder, shift register, etc) and ...
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68 views

Is it possible to know what % of routing resources are used in an FPGA

FPGAs contain logic resources and routing resources to link them together. I think that, for a given number of logic blocks being used, there would be a % of routing resources being used that link ...
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54 views

Why am I getting my result as a string of Zs in Quartus?

I am new to Quartus, and have been trying to test out my 32-bit ALU on Quartus 13.1. When I try the functional simulation, I get a string of Zs. The results for the individual components, like the ...
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347 views

FPGA Internal Timing constraint failing

I'm currently trying to implement an IP-Core on a Cyclone V 5CSEBA6U23I7 FPGA-HPS System using Altera Quartus II and TimeQuest Analyzer. The Verilog code pasted below produces a timing problem, namely ...
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189 views

Can I learn VHDL on a CPLD device?

I need to learn and practice VHDL, so I wouldlike to buy a small FPGA dev board. I've found a board based on a MAX10 circuit with the exact form factor I need, but I've read this chip is a CPLD, not a ...
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4k views

Vhdl error 10327 - can't determine definition of operator “”&“” — found 0 possible definitions

I'm adjusting some vhdl code an am getting the following error: Error (10327): VHDL error at myfile.vhd(87): can't determine definition of operator ""&"" -- found 0 possible definitions The ...
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2answers
808 views

How to know power consumption of core FPGA

I am using a DE0-Nano board in my project. It has an Altera Cyclone IV E FPGA chip in it plus other components such as ADC, RAM, etc. When connected to a USB power supply, the DE0-Nano requires around ...
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2answers
266 views

Adaptative Logic Module : Logic Element equivalence

I have implemented some circuitry with Quartus on a Cyclone 5 FPGA. This has be done for my master thesis. I have to justify wether the number of logic element used by my implementation is "expected" ...
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2answers
1k views

How to make an .sof upload to an Altera Max10 stick [duplicate]

I have a Max10 dev board with a 10m08 chip on it. I made a simple counter to blink the LED's. My counters have asynchronous resets, and my asynchronous reset has a circuit to keep it low for two clock ...
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1k views

Active serial configuration flash (EPCS & EPCQ) vs normal SPI flash

Is there a difference between the serial configuration devices from Altera and any other SPI flash memories? I see Terasic uses S25FL256S in their development board instead of EPCQ256, so I wondered ...
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2k views

Loading and displaying on VGA monitor a Background image in DE2-115's SDRAM

I would like to load a background image which I currently have saved as a .bmp into the DE2-115's SDRAM. I would then like to display this background image on a VGA-monitor (640x480). I will then be ...
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1answer
304 views

VHDL code works well in ModelSim and strange behavior in Altera FPGA

I'm trying to understand a strange (for me) behavior of a simple VHDL code. I have realized a stupid code that works well in ModelSim and doesn't work in a real FPGA (Altera MAX 10). ...
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325 views

VHDL variable behaving strangely

I have the following snippet of VHDL code which is misbehaving and I don't know why: ...
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2answers
2k views

create Eagle library for bsdl file

I am designing a PCB Board for Altera Cyclone III EP3C5E144. However, I cant find any library for this device in Eagle. Is there anyways I could create the library and symbol for this device, based ...
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3answers
1k views

SignalTap II: OR trigger conditions, instead of AND

I'm using the Altera SignalTap II that comes with Quartus II. As far as I understand, each pin can be assigned a trigger condition. It seems that acquisition only stops when all the trigger conditions ...
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3answers
50 views

Measuring the external memory power consumption in FPGAs?

I am trying to get a power/energy breakdown of DDR3 and core logic. I used Quartus power analyzer tool to get the power estimates, but I am not sure whether it includes the power consumption of ...
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1answer
81 views

Intel FPGA equivalents of Xilinx IBUFDS Primitives?

Im trying to migrate an Design from using Xilinx primitives to Intel Altera FPGA. The original design uses the IBUFDS for the clock signals. ...
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2answers
38 views

How can Qsys component configuration be accessed in software?

I'm designing a Qsys component which I want to be user-configurable. It has config parameters which are defined in the TCL file. For example, for a GPIO bank component I would write: ...
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1answer
88 views

Get more AS-attached flash chip information from ALTASMI

I am playing with the attaching various configuration flash devices to the Altera Cyclone 3. In particular, I want to replace EPCS16 (2MB) with W25Q128 (16MB) - for both size and cost reasons. Is ...
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1answer
290 views

How to compare a re-writable 4 bit value to a given 4 bit input in Verilog?

The goal of this project to design a computational lock alarm in Verilog to be run on an Altera board (note on the board 0 is actually ON and 1 is OFF). Based on the design criteria I created a state ...
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1answer
49 views

Is it possible to power down all the PLLs and VCO of a MAX 10 Device?

We are developing a board in which we would like not to use the analog features, like PLL, VCO and ADCs of a MAX10. UG-M10CLKPLL par. 2.3.6 states : "The only time that the VCO is completely disabled ...
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1answer
158 views

Altera Cyclone IV clock-to-output delay

Trying to find what is the clock-to-output delay for registers inside EP4CE6E22C6. Have looked through the 3 Cyclone IV handbooks searching by delay but have not found any values specified. All the ...
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1answer
121 views

Intel max 10 dimensions - datasheet & BSDL mismatch

TL;DR: The BSD file from Intel doesn't match the datasheet. What are the right dimensions? BSD: https://www.intel.com/content/dam/altera-www/global/en_US/others/support/devices/bsdl/10M02SCM153.bsd ...
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470 views

How can I connect a USB keyboard to a DE1-SoC?

I recently got a DE1-SoC development board from Intel and I wanted to use it to instantiate a computer design I created while following along the Nand2Tetris course on Coursera. Unfortunately, this ...
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1answer
126 views

Intel Altera MAX 10 DEV KIT Interface - Can a RS232 6 pin PMOD module by Digilent be used seamlessly with MAX 10 for PC-FPGA UART communication?

I am planning to either purchase a MAX 10 or a DE2-115 dev kit to implement communication via both ethernet and RS-232. DE2-115 has both ports soldered onto the board, but MAX-10 has 2 ethernet ports ...
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1answer
141 views

Can Nios II read addresses in increments of 1 or only increments of 4?

There is some confusion here. I think that the Nios II having 32 bit data bus. Therefore, it is not capable of individual byte addressing. Therefore, the address bus increases as 0, 4, 8 e.t.c and not ...
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1answer
107 views

Incomprehensible FPGA error

I try and upload my design, which worked previously, using quartus prime 17.1 to an Altera DE2-115. It fails like this: ...
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1answer
251 views

Altera Max10 altPLL slack

Regarding a MAX10 board. The whole design inside the MAX10 is clocked from a single clock using verilog's always@(posedge clockin). If connect directly a 80mhz clock to a Max10 input pin and define ...
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2answers
625 views

How to check receiving 16-bit data using a serial terminal?

I am using an FPGA vhdl UART code to send 16bits of data with a 1 start bit, 1 stop bits and even parity bit. I need to check whether the sent 16bit packets are correctly receiving using a terminal ...
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264 views

For Altera LPM_MULT to have registered output, is it enough to set latency to 1?

It is recommended that the inputs and the output of the LPM_MULT be registered. This will make it possible to achieve highest frequency for the design, although introduce latency. With latency of 0, ...
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140 views

On Cyclone II FPGAs can I apply voltage directly on input pins?

On Cyclone II FPGAs can I apply voltage directly on input pins, maybe taking it from a Vcc pin? Or should I use a resistor? The Altera DE2 board's schematics below looks like some input switches don'...
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2answers
196 views

How to direct input and output of circuit for multifunctional 4 bit calculator [closed]

I am trying to build a 4 bit calculator that can add subtract and multiply using a FPGA board (Altera DE2). I have an adder/subtractor and multiplier already built and functioning but need to know ...
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1answer
620 views

FPGA, accessing data in RAM

I'm using an Altera Cyclone V DE1-SoC for an image processing project and to be able to do the "processing" on the FPGA, I thought I probably needed to store the image data on the FPGA first. So I ...
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1answer
78 views

Msg about opencore in Quartus programmer

I did some changes to a design in Quartus and in Qsys. Now when I load the design to my FPGA with Quartus programmer then I get a message about opencores and that there is unlimited time. The msg was ...
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1answer
477 views

FPGA flash memory programming

I'm trying to run this example because I have a DE2-115. I get this debug output then I don't know what to do ...
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1answer
300 views

Altera DE1 and DE2 - same UART?

I wonder if the Altera DE1 and DE2 have the same UART? I got access to both the DE1 and the DE2 and I see a similar question but the manual isn't specific which FPGA is applicable. UART core Altera ...
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2answers
423 views

Trying to find out the voltage threshold for input of a GPIO pin in an FPGA development board

I need to use a camera module along with De1-SoC development board. Camera requires 3.3V to work and it provides outputs with a 2.5V output pin. I am trying to find what is the range of voltages that ...
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1answer
319 views

How to erase a bitstream from an FFPGA using a microcontroller?

How can I erase the bitstream that is stored in flash memory from an FFPGA (Flash FPGA, e.g. MAX10) using a microcontroller or any other logic? I analyzed MAX10 documentation and still didn't find ...
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2answers
544 views

Altera MAX10 CPLD initialization IO state

I'm designing a pcb with an Altera MAX10 (10M02) CPLD used to do, amongst other things, bus arbitration between several memory chips (one /CS per chip). All the memory chip are on same bus so only ...
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1answer
398 views

How to see the content of the SDRAM in my DE1-SOC while running (JTAG Altera cable)?

I have made a simple design in Quartus Prime, in verilog code, not using megawizard, but directly accessing the pins of the SDRAM. I am saving 2 x 16 bits binary numbers on 3 of the 4 banks of the ...
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1answer
740 views

Failing to program Cyclone IV GX device via JTAG

I just got the aforementioned device and, upon writing a simple program (it compiles) and going into Programmer, when I try to program the device with the .sof file, I see is ...
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1answer
140 views

nrf24l01 transceiver on altera board de2-115 [closed]

I'm trying to use the nrf24l01 transceiver on altera board de2-115. I would like to send a signal from the altera board using this spi module to another spi module and use the spi module on the ...
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1answer
143 views

How to connect to this FPGA board?

I got this board from ebay, seemed to be a cheap deal. It is decent product from what I can say at this time. The question is, what is the most appropriate way to connect a daughter board to this ...
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1answer
792 views

Output CLOCK signal to GPIO pin of CYCLONE IV E

I am new to FPGA and I am trying to send a CLOCK signal as an output of a GPIO pin of an Altera Cyclone IV E. I first made a program: ...
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1answer
94 views

Is there a method to provide physical stimulus to design inside FPGA like we do in VHDL test bench?

Basically I need to find out if there is a feature that allows one to enter stimulus into an FPGA without using things like signal generators. Altera FPGAs have a feature implemented via Quartus ...
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2answers
185 views

How do I put a high-speed pulse through a digital logic chip?

I have a system which uses a 3ns pulse to trigger some downstream circuitry. When I hook up the trigger generating circuit directly to the downstream circuit, everything works fine. When I route the ...
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1answer
695 views

Altera FPGA Reset System

I having a hard time understanding the best way to setup a NIOS II system with external code and the resets and clocks. One of the reasons why I'd like to figure this out is the JTAG system really ...
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1answer
1k views

Altera Quartus not creating symbol files

I'm looking to create a schematic block from a vhdl file in Altera'a Quartus software. I've been using File->Create/Update->Create Symbol Files for Current file The file compiles okay and I get the ...