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Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

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3answers
974 views

Implementing an ADC Interface to connect to a FPGA

I want to implement an ADC Interface for an ADC - ADS 7230 (TI) in VHDL. I am not very familiar with ADCs to implement it in VHDL. I already have an ADC Interface for a 10 bit ADC (MAX 1030) and a ...
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1answer
317 views

Nesting entities in VHDL (Altera Quartus)

I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU. The first part is composed of a FIFO buffer, Cache memory for ...
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1answer
606 views

Can DE2-115 handle more than 3.3V on its GPIO

In my current project I want to connect some logic to Altera DE2-115 using 40-pin exapnsion header (JP5). Unfortunately, I can't ...
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0answers
887 views

Can Altera GPIO pins read the input voltage?

I have ALtera DE2-115, and I have a light sensor module, the output of the light sensor is a voltage, how can I use the Altera GPIO pins to read the coming voltage? Thanks
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1answer
349 views

PING Ultrasonic sensor output

I'm new to the world of Digital Systems :D I want to know whether the output of the Ultrasonic range finder sensor is analog or digital, so I can connect it to Altera DE2 GPIO directly or I need an ...
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2answers
2k views

Understanding timers

I'm studying timers for use in scheduling and embedded systems but I don't understand the detail, does the time count upwards or downwards? Is the timer like a hardware timer like the ones we learnt ...
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2answers
2k views

How to implement FIR filter for Altera DE2?

I understand that a DSP is preferred rather than FPGA for an FIR filter, but my task is to implement both fixed-point and floating-point software filters (in C) for the Altera DE2. I barely know what ...
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1answer
126 views

Clock port and any other port of a register should not be driven by the same signal source

I get this Warning from Altera Design Assistant for the below: Clock port and any other port of a register should not be driven by the same signal source Critical Warning (308012): Node "App_Logic:...
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2answers
139 views

Access to Quartus II beta

My FPGA card (a BittWare card, datasheet available here) comes with example designs which require Quartus II 14 (beta). I cannot find where the beta versions of Quartus II can be downloaded from the ...
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1answer
299 views

Can I connect all my components in my top level entity

I have finished writing a project with separate VHDL files. Most of the components have connections directly to the FPGA ( which I have instantiated and connected in the top level file) but a few do ...
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1answer
86 views

Any ideas for a hardware to do AM and FM modulation? [closed]

I'm trying to do some signal processing (AM/FM Modulation) for signals from 0 - 60kHz. Any recommendations for hardware? Preferably something I can use MATLAB with (or Python) as I'll most likely be ...
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2answers
292 views

Can I shield noise inside an FPGA with a ground plane?

I am routing some external signals through an Altera FPGA and noise is coupling into the signals from something else in the FPGA. I have an idea to physically distance the signal route from the rest ...
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1answer
138 views

How to constrain fitter to assign signals to specific LE input in Quartus II?

I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To ...
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0answers
101 views

Learning FPGA Design (Books, Resources, VHDL/Verilog) [closed]

I used to use FPGA's back in college and I really enjoyed it. Years have passed though and I haven't had much time to play with it since then. I have realized I have forgotten some stuff (quite a bit ...
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1answer
525 views

FSM Using Excitation Equations and VHDL

I have been trying to create a FSM using the excitation equations I developed. I have not had much luck. The circuit has no output. I DO NOT WANT TO USE 'TYPE' and custom state types. That is the ...
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2answers
1k views

Altera Clock + PLL

I am using an Altera devkit from terasic, DE0-CV. I am also new to the FPGA business. How to connect the onboard clock to the FPGA and use it with my design? As the clock is a 50 MHz one, surely I ...
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1answer
171 views

Error (10327): VHDL error at clkdivider.vhd(27): can't determine definition of operator “”not“” — found 0 possible definitions

I am still a beginner and I keep getting this error, can anyone help pls? ...
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1answer
2k views

how to set pin in verilog (atera)

I am beginner in Altera DE2-115. I am asked to make a project using Verilog language. My idea was connect an infrared sensor and if it is cut with something, a buzzer starts. The infra has 3 ...
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1answer
835 views

Write an I2C code for Cyclone 2 architecture

I really need to I2C interface my FPGA with some slave device. I figured I could use the audio codec in my FPGA as a slave.I have gone through some codes from the internet for I2C. But I do not get ...
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2answers
408 views

Need Quartis II CPLD tutorial for learning VHDL from ZERO [closed]

I am learning VHDL from zero using Altera CPLD. Already got Quartis II 12.1 and a 15-lines example VHDL (like Hello World for C learner). To avoid learning bad coding style or digging too deep too ...
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1answer
61 views

Using ieee.proposed package for a dft. Quartus showing just 10 logic elements corresponding to just 10 states. [closed]

Can anyone suggest possible reasons why this might be happening? Compilation is succesful. We have analyzed the code. Can't figure out any logical errors or syntax errors(else wouldn't compile).
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2answers
204 views

Cycle-Accurate Power Estimation for Altera Devices

I'll be doing some analysis which requires at least cycle-accurate power estimations. From what I gather, the PowerPlay tool only calculates total power consumption. I've also looked into Synplify, ...
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2answers
77 views

Trouble understanding timing simulations in Quartus?

I have tried my ALU on the functional simulation and I get the correct waveforms. However, I am confused about how to interpret the timing simulations. What causes the ripples in the carry_out, and ...
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1answer
37 views

What's the order of the array generated by Verilog? Syntax

What is the correct interpretation between these two lines: wire[2:0] w = SW[17:15] = {SW[17], SW[16], SW[15]} wire[2:0] w = SW[17:15] = {SW[15], SW[16], SW[17]} When I call w[0] will I get SW[15] ...
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2answers
2k views

Learn CPLD from zero [closed]

a) Should I learn VHDL or Verilog? Is one excel in some area while the other better fit another area? For simple "glue logic", says, 5 to 30 TTL chips equivalant, which is better? b) First ...
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1answer
119 views

Altera FPGA Pinout help [closed]

I recently bought an Altera FPGA Cyclone II board off of ebay, it says BAIXUN on the LCD display. It didnt come with any documentation. I'm trying to program the FPGA board but I have no idea what pin ...
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1answer
172 views

Is it technically feasible to design a microchip that won't fail foreign characters? [closed]

I used to work as web developer and did the same part of the project for several decades: Making sure that our Scandinavian characters åäöÅÄÖ... will work. It was feasible and it did work, basically ...
-4
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1answer
13k views

How can I generate a 1 Hz clock from 50 MHz clock coming from an Altera board? [duplicate]

I have an Altera DE2 board that outputs a 50 MHz clock and I'm trying to write a verilog module that can bring it down to 1 Hz. How can I do this?