Questions tagged [ise]
Xilinx Integrated Software Environment (ISE) is a suite of design and analysis software for their range of CPLD and FPGA devices.
96 questions
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A NAND gate with propagation delay in VHDL
I want to design a NAND gate (\$t_{PLH}\$ = \$t_{PHL}\$ = 10ns) with VHDL.
\$t_{PLH}\$ = Propagation delay low to high
\$t_{PHL}\$ = Propagation delay high to low
This is first code.
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What does an .ngc file do in Xilinx ISE?
A couple days ago we were given our last project assignment at the HDL course at my uni. Among the files provided was a .ngc file and we were told to place it inside the project folder. It is supposed ...
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Problems in UART communication using Nexys 3 board
I am trying to send 1 byte of data from my Nexys 3 board to my PC using UART communication.
The problem is that whenever I try to view the data on RealTerm no matter my input (hard coded into the code ...
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Xilinx ISE on Debian 10+
I have been working for quite some time now with Xilinx ISE 14.7 on Debian development machines. Before the suggestion comes: We use a Virtex-6 FPGA for our research and have no option to switch to ...
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ISE Design Suite simulation problem
I am new in Verilog language. I am trying to understand the basics. There is this question where the input is a 6-bit number named IN and the output is a 1-bit ...
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Duplication of working PWM signal leads to unexpected behaviour
I am trying to control 13 different servos with my Spartan3 FPGA. For that, I need 13 independent PWM signals generated by my FPGA. The PWM module that I am using works perfectly fine when only one ...
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Use SDC format for timing constraints on Xilinx CPLDs
Due to the chip shortage, I'm trying to perform timing analysis of an existing CPLD design for a number of alternative chips from different manufacturers.
I have existing hardware description source ...
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SDC constraint inside Xilinx ISE
Inside ISE timing constraint editor window, which following sub-section shall I use set_clock_group to solve the STA setup timing violation path #1 due to cross-clock signal ?
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347
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Combinatorial loop of SR latch
I implemented an SR latch in Verilog.
module sr_latch(
output Q,
output P,
input S,
input R
);
nor(P, S, Q);
nor(Q, R, P);
endmodule
However, ...
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New design with XC9500XL CPLDs, is it already obsolete?
I am in the middle of a new design for which a relatively small amount of logic is needed. This is a change to a previous version in which discrete 3.3V logic parts were used. We decided to go a CPLD ...
- 8,546
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In Xilinx ISE, why can't I rename the net of some of my ports?
In Xilinx ISE, most of the time, when I want to rename the net of a certain port, I have no problem. I right-click on the I/O marker, click Rename Port, and I get the window for Rename Net. However, ...
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4 bit synchronous counter circuit that counts from 1 to 6
I'm having trouble answering this question, it is for my laboratory. My online lab sessions only discussed how to answer it briefly.
I am not sure how to go from here, I've filled in the K-map with ...
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2
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364
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Verilog latch occurring with instantiating modules with in a generate statement
I am trying to create a register file in Verilog. To do this, I am instantiating multiple instances of a register module I designed in a generate statement. Each module uses a different input and ...
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349
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AND gate between 2 std_logic_vector Isn't working correctly
I am trying to do a multiplication between 2 std_logic_vector
have the following testbech:
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Feedback signal consumed in VHDL
Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema:
Where the "latch_rs" is written as follow:
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107
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ISE Design suite
im extremely new to ISE design suite. In fact, im waiting for my windows PC to arrive so i can actually download it.
But i wanted to ask, if i wrote some VHDL for a full adder logic circuit using 2 ...
user209109
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Hardware design
Is there a way to actually build components on something like Xilinx ISE?
i.e. MUX's, NAND's, AND gates.
From what I've learned so far, one can only use VHDL to describe hardware and the compilation ...
user200955
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718
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Using VHDL with the Mojo V3 FPGA
I was just wondering if there's any way for me to write VHDL code, that I can then upload to the Mojo V3 board?
The Mojo V3 IDE is Verilog/Lucid friendly, both languages that I'm unfamiliar with.
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3k
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different approaches to implementing program counter
I want to implement the following 32 bit program counter circuit:
and this is my current verilog code:
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159
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Can I estimate what CPLD I need?
I'm planning to design a driver for VGA connectors, and for testing purposes I have an evaluation board of one CPLD. Concretely, the board is the Digilent's CoolRunner-II with the Xilinx's XC2C256 ...
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shift whole design in Xillinx FPGA
How can I shift whole my design using ISE(FPGAditor,plan ahead,..) to new placement?
I want to no change in routing but change only in placement.
Thanks.
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Why Xilinx ISE doesn't infer Block Ram for this Array?
I have an Entity that has an array type as below :
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- 259
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How do I synchronize my FPGA clock frequency with RS-232 transmission baud rate?
My FPGA Spartan 3E supports 50 Mhz clock via ocillators. Now I am using RS-232 cable connection to send output bits serially into my computer system using HyperTerminal/RealTerm.
However the baud ...
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516
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How to probe into the internal signals and registers in FPGA without using JTAG?
I am using a Xilinx Spartan 3E FPGA kit in my academic project to synthesize a design comprising of a couple of 32 bit internal registers (eg few counters, shifters and some configuration registers) . ...
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How to decrease used LUTs in FPGA Design?
I am working with Spartan 2 XC2S50 FPGA Chip on Xilinx board
There is a problem on my design that increases number of used LUTs
and this is the Utility Library :
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Verilog: Writing to a Register Happens A Clock Cycle Late
I have a Verilog module acting as a register file (a slew of registers and some access ports) with a control signal coming from another module that controls when the write to one of the registers ...
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2
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284
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U and the end of vector in iSIM
I am making first steps in VHDL and ISE (from Xilinx).
I've tried to create a simple 16bit -> 32bit converter.
Converter receives a compliment to 2 number (16bit, so it is 1 bit for sign and 15 bits ...
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99
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Test in VHDL of working frequency of a combinatorial component
I want to measure approximately working frequency of a combinatorial component. To do this, I use a my implementation of scan-chain to wrap my ripple carry adder. This is my code:
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824
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measurement of the number of LUTs-FF pairs and logic cells under most efficient and inefficient condition
Can anyone tell me how to get the number of the LUTs-ff pairs and logic cell used under most efficient and inefficient condition in my ISE Design Summary.
I can see there are data of 'Number of Slice ...
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107
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How to view the optimized combinational function after HDL synthesis?
I am using Xilinx ISE v8.1, and VHDL language. I have a simple design implemented using behavioral approach, which gives me a set of combinatorial functions.
I can see the schematic of the outcome ...
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Driving a differential signal from FPGA
Disclaimer: I am not sure if this is the right place to ask this.
I am trying to create an sdram controller for the numato mimas v2 fpga. The board contains an LPDDR module (either the Micron ...
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556
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Run XST from Windows Command Line
I am attempting to build a C++ program that performs all of the necessary steps generate a bit file using the ISE (14.7) tool chain. I generate the Command line Log File for my project and try to run ...
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Signal is connected to following multiple drivers
This is the top module combining the Circular Shift Register, Multiplexer and Adder.
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what is the difference between ISE and Vivado? [closed]
I am xilinx ISE and virtex 5 engineer.
I found Vivado something when I ran across the internet.
What is the difference between ISE and Vivado?
Should I have to move to Vivado from ISE?
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HDMI (TMDS) output with Digilent Atlys - examples do not compile with ISE 14.7
I'm working on XAPP495 on Digilent Atlys board with ISE 14.7
I want to run and test "vct_demo" coming with the XAP 495. I tried to compile it (with ISE 14.7) and failed because of the following ...
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Is there support XC5VLX110 list in ISE Project setting?
I'm just trying to setup ISE envirmonent.
But There's not XC5VLX110 in Device list at the Project Settings in ISE as below picture.
What should I do for solving in this situation?
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How to get a default UCF file of Xilinx Virtex-5 XC5VLX110?
How to get a default UCF file of the Xilinx Virtex-5 XC5VLX110?
It doesn't seem to be anyhere. If I have to make it by myself, would you let me know how to ...
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489
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What is the purpose of a "BUF" in Xilinx ISE schematic?
I'm working on a schematic for a Xilinx CPLD using ISE. The schematic has a triangle symbol labeled "BUF" before every output, and also between some other nets. I can't really tell why some ...
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Why does output register remain x in the waveform even when clock changes?
I am using ISE to write my first Verilog code. I wrote a counter:
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732
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FPGA : program that doesn't work everytime
I'm making an ADC (in VHDL) for Spartan-3AN. Unfortunately I have to program my FPGA (program FPGA only) a random time before the programmable gain amplifier (Spartan 3AN User Guide page 73) works ...
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198
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Using the UCF constraints to assign one of two output ports
I've got a CPLD design which has one spare (Debug) pin. I'm trying to find out if it's possible to use the UCF file to select which output port (NET) that pin becomes.
The problem is however, that I'...
- 349
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Exclude certain module from optimization in Xilinx ISE 14.4
I'm synthesizing a quite large design in Xilinx ISE 14.4 and would like to exclude certain modules from optimization. Is that possible?
The design I'm synthesizing is the LEON3 microprocessor. I have ...
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Xilinx ISE Synthesis taking too long
I just finished to write a pretty complete design on ISE 14.7 targetting a Virtex7 device. The behavioural simulation (on Isim) takes a while but works perfectly.
Therefore, I tried to move to the ...
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164
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Synthesis error when using "-opt_mode area" in Xilinx XST
I am experiencing fatal errors when synthesising my design with Xilinx XST 14.7 and the -opt_mode option set to area. With ...
- 883
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157
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Searching for a bus value in ISim 14.2
One of the signals I've traced in ISim is a 16-bit bus. How do I find all time points when its level became a given value?
Running the simulation takes several hours, and I don't know in advance what ...
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1k
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470
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Xilinx CORDIC 4.0 Translate parameters question
I'm developing a SysGen model using a CORDIC 4.0 Translate core to pass from rectangular coordinates to polar coordinates.
I need understand the Coarse rotation and Compensation scaling options.
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Clock doesn't seem to tick
I have been working on a program for class which acts as a stopwatch, but I've been having troubles where it doesn't work. (Only one digit, the first that would be shown on the four digit display is ...
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