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Questions tagged [ise]

Xilinx Integrated Software Environment (ISE) is a suite of design and analysis software for their range of CPLD and FPGA devices.

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Feedback signal consumed in VHDL

Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema: Where the "latch_rs" is written as follow: ...
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54 views

ISE Design suite

im extremely new to ISE design suite. In fact, im waiting for my windows PC to arrive so i can actually download it. But i wanted to ask, if i wrote some VHDL for a full adder logic circuit using 2 ...
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93 views

Hardware design

Is there a way to actually build components on something like Xilinx ISE? i.e. MUX's, NAND's, AND gates. From what I've learned so far, one can only use VHDL to describe hardware and the compilation ...
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41 views

Exporting RAM content to text file in ISim

I'm trying to learn about Xilinx IP cores and FFT implementation on FPGA-s. For that I've created a simple project where I instantiate LogiCore FFT 8.0 core, ROM core and a RAM core. The ROM core ...
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1answer
152 views

Using VHDL with the Mojo V3 FPGA

I was just wondering if there's any way for me to write VHDL code, that I can then upload to the Mojo V3 board? The Mojo V3 IDE is Verilog/Lucid friendly, both languages that I'm unfamiliar with. ...
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157 views

different approaches to implementing program counter

I want to implement the following 32 bit program counter circuit: and this is my current verilog code: ...
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1answer
34 views

Can I estimate what CPLD I need?

I'm planning to design a driver for VGA connectors, and for testing purposes I have an evaluation board of one CPLD. Concretely, the board is the Digilent's CoolRunner-II with the Xilinx's XC2C256 ...
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59 views

Propagate data bits with 8 BIT register in ISE SR8RLED

I had some issues propagating the input from the 8 BIT register to the output using the SR8RLED 8 BIT Register in Xilinx ISE. The register has the following parameters: ...
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2answers
62 views

shift whole design in Xillinx FPGA

How can I shift whole my design using ISE(FPGAditor,plan ahead,..) to new placement? I want to no change in routing but change only in placement. Thanks.
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4answers
565 views

Why Xilinx ISE doesn't infer Block Ram for this Array?

I have an Entity that has an array type as below : ...
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1answer
194 views

How do I synchronize my FPGA clock frequency with RS-232 transmission baud rate?

My FPGA Spartan 3E supports 50 Mhz clock via ocillators. Now I am using RS-232 cable connection to send output bits serially into my computer system using HyperTerminal/RealTerm. However the baud ...
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1answer
176 views

How to probe into the internal signals and registers in FPGA without using JTAG?

I am using a Xilinx Spartan 3E FPGA kit in my academic project to synthesize a design comprising of a couple of 32 bit internal registers (eg few counters, shifters and some configuration registers) . ...
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3answers
422 views

How to decrease used LUTs in FPGA Design?

I am working with Spartan 2 XC2S50 FPGA Chip on Xilinx board There is a problem on my design that increases number of used LUTs and this is the Utility Library : ...
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2k views
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1k views

Verilog: Writing to a Register Happens A Clock Cycle Late

I have a Verilog module acting as a register file (a slew of registers and some access ports) with a control signal coming from another module that controls when the write to one of the registers ...
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33 views

Are there any methods to simulate time-base power usage of a Xilinx/Altera FPGA?

Old versions of Xilinx ISE suite got XPower tool which had -tb option to simulate time-based power usage of an FPGA by an input .vcd file like this: ...
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2answers
184 views

U and the end of vector in iSIM

I am making first steps in VHDL and ISE (from Xilinx). I've tried to create a simple 16bit -> 32bit converter. Converter receives a compliment to 2 number (16bit, so it is 1 bit for sign and 15 bits ...
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2answers
88 views

Test in VHDL of working frequency of a combinatorial component

I want to measure approximately working frequency of a combinatorial component. To do this, I use a my implementation of scan-chain to wrap my ripple carry adder. This is my code: ...
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1answer
345 views

measurement of the number of LUTs-FF pairs and logic cells under most efficient and inefficient condition

Can anyone tell me how to get the number of the LUTs-ff pairs and logic cell used under most efficient and inefficient condition in my ISE Design Summary. I can see there are data of 'Number of Slice ...
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2answers
90 views

How to view the optimized combinational function after HDL synthesis?

I am using Xilinx ISE v8.1, and VHDL language. I have a simple design implemented using behavioral approach, which gives me a set of combinatorial functions. I can see the schematic of the outcome ...
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1answer
1k views

Driving a differential signal from FPGA

Disclaimer: I am not sure if this is the right place to ask this. I am trying to create an sdram controller for the numato mimas v2 fpga. The board contains an LPDDR module (either the Micron ...
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338 views

Run XST from Windows Command Line

I am attempting to build a C++ program that performs all of the necessary steps generate a bit file using the ISE (14.7) tool chain. I generate the Command line Log File for my project and try to run ...
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1answer
859 views

Signal is connected to following multiple drivers

This is the top module combining the Circular Shift Register, Multiplexer and Adder. ...
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1answer
2k views

what is the difference between ISE and Vivado? [closed]

I am xilinx ISE and virtex 5 engineer. I found Vivado something when I ran across the internet. What is the difference between ISE and Vivado? Should I have to move to Vivado from ISE?
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1answer
249 views

HDMI (TMDS) output with Digilent Atlys - examples do not compile with ISE 14.7

I'm working on XAPP495 on Digilent Atlys board with ISE 14.7 I want to run and test "vct_demo" coming with the XAP 495. I tried to compile it (with ISE 14.7) and failed because of the following ...
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1answer
61 views

Is there support XC5VLX110 list in ISE Project setting?

I'm just trying to setup ISE envirmonent. But There's not XC5VLX110 in Device list at the Project Settings in ISE as below picture. What should I do for solving in this situation?
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2answers
908 views

How to get a default UCF file of Xilinx Virtex-5 XC5VLX110?

How to get a default UCF file of the Xilinx Virtex-5 XC5VLX110? It doesn't seem to be anyhere. If I have to make it by myself, would you let me know how to ...
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1answer
300 views

What is the purpose of a “BUF” in Xilinx ISE schematic?

I'm working on a schematic for a Xilinx CPLD using ISE. The schematic has a triangle symbol labeled "BUF" before every output, and also between some other nets. I can't really tell why some ...
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2answers
4k views

the output register remains x in the waveform even when clock changes?

I am using ISE to write my first verilog code . i wrote a counter : ...
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2answers
454 views

FPGA : program that doesn't work everytime

I'm making an ADC (in VHDL) for Spartan-3AN. Unfortunately I have to program my FPGA (program FPGA only) a random time before the programmable gain amplifier (Spartan 3AN User Guide page 73) works ...
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1answer
103 views

Using the UCF constraints to assign one of two output ports

I've got a CPLD design which has one spare (Debug) pin. I'm trying to find out if it's possible to use the UCF file to select which output port (NET) that pin becomes. The problem is however, that I'...
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0answers
299 views

Exclude certain module from optimization in Xilinx ISE 14.4

I'm synthesizing a quite large design in Xilinx ISE 14.4 and would like to exclude certain modules from optimization. Is that possible? The design I'm synthesizing is the LEON3 microprocessor. I have ...
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2answers
2k views

Xilinx ISE Synthesis taking too long

I just finished to write a pretty complete design on ISE 14.7 targetting a Virtex7 device. The behavioural simulation (on Isim) takes a while but works perfectly. Therefore, I tried to move to the ...
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113 views

Synthesis error when using “-opt_mode area” in Xilinx XST

I am experiencing fatal errors when synthesising my design with Xilinx XST 14.7 and the -opt_mode option set to area. With ...
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130 views

Searching for a bus value in ISim 14.2

One of the signals I've traced in ISim is a 16-bit bus. How do I find all time points when its level became a given value? Running the simulation takes several hours, and I don't know in advance what ...
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1answer
734 views

How to solve ERROR Xst:528 in ISE?

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3answers
1k views

How to simulate an 8x4 memory using VHDL?

Why does this code: ...
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1answer
296 views

Xilinx CORDIC 4.0 Translate parameters question

I'm developing a SysGen model using a CORDIC 4.0 Translate core to pass from rectangular coordinates to polar coordinates. I need understand the Coarse rotation and Compensation scaling options. ...
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1answer
248 views

Clock doesn't seem to tick

I have been working on a program for class which acts as a stopwatch, but I've been having troubles where it doesn't work. (Only one digit, the first that would be shown on the four digit display is ...
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1answer
462 views

syntax error verilog code

this sub-code that read the selection line s4-s1 and take the summation of a,b in the selection line =0000, When running this code in ISE project negotiator it gives syntax error tell " Syntax ...
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410 views

Can't Search for specific value at RAM - verilog

My module has search for specific value at RAM and then return its location address. when I wrote a test bench, I see that the module didn't work correctly! always the output value is "don't care". ...
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545 views

searching in memory at verilog

I need to make a module which responsible to search overall memory to find a specific value and return the address location, but I have the following error after do Synthesize in Xilinx. ...
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1answer
1k views

Which is the best way to version control Xilinx PlanAhead projects?

Actually I'm migrating some mature projects from Xilinx ISE to Xilinx PlanAhead. I need to take advantage of TCL scripting and partitioning of PlanAhead. This ISE projects are under version control ...
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2answers
286 views

VHDL Overmapping and Time Constaint issues in Xilinx-ISE

I have an issue with a module I use for rotation of a vector. I have two operations one uses 2 rotLeft modules and the other uses 2 rotRights. Originally I had occupied Slices overmapping issues which ...
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1answer
473 views

Why does Xilinx Translate for Virtex-6 not know IOSTANDARD LVDS?

I'm using several Xilinx FPGAs and boards from Spartan3E up to KC705/VC707 and I'm very familiar with UCF files, but there is one question that bothers me... Why does translate for Virtex-6 not know ...
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1answer
359 views

How to assign the same value to a bus in Xilinx ISE (Schematic)?

How to set all the bits for example in bus(7:0) to the value in net0?
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0answers
152 views

Macrocell and Function Block optimization ISE XILINX

I get the following result when I compile my code in ISE. It says the CPLD is full, but I can't help but notice that the optimizer should be able to move elements from different function blocks to ...
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1answer
4k views

Convert C to FPGA

I'm new to programming for FPGAs so I was recommended to use some available C/C++ to VHDL translator. Problem is, there are tons of information out there and almost all good programs need an ...
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1answer
175 views

FPGA - Routing Diagram - what are the physical parts

In Xilinx ISE I've generated a very simple piece of hardware and when looking at the routed design I'm unsure what some of the parts are and require some clarification on what some of these parts are. ...
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1answer
1k views

Use Xilinx Primitive elements in Verilog inside ISE

I generated Verilog Post-Route simulation model of my original Verilog module, using Xilinx ISE. It will generate a Verilog module using LUT and fpga level primitives such as IBUF,X_LUT4, ... When ...