Questions tagged [ise]

Xilinx Integrated Software Environment (ISE) is a suite of design and analysis software for their range of CPLD and FPGA devices.

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List of Xilinx file suffixes (for ISE)

I asked Xilinx for such a list but they don't have a complete list. I wish to make sure all input files are in source control and all output files aren't. This is with 13.1-13.2 with ISE and PlanAhead ...
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6 votes
1 answer
2k views

Preventing Verilog module from being optimised away

I have tried to put lots of inverters to stress test my Spartan 6 power supply as recommended here. Here is the basic module: ...
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6 votes
1 answer
340 views

Minimal redistributable coregen output for command-line rebuilds

I'm building an SoC with my own soft-core, and I want people to be able to easily rebuild it using Xilinx webpack command-line tools. I'm using coregen's Clock Wizard to create a clock module, but ...
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4 votes
1 answer
4k views

How to get rid of the warning "WARNING:PhysDesignRules:367 - The signal IBUF is incomplete."

I'm working on a simple neuron implementation on a Xilinx Spartan-3E starter kit and getting the warning in the topic. Can anyone explain me why I am getting this error? My code: ...
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4 votes
1 answer
2k views

Why Xilinx ISE can't get access to my custom package?

I am trying to create a custom data type which I am creating in a package using Xilinx ISE 14.5. I am trying to create a generic DEMUX to switch between buses, here is the code of the generic DEMUX: <...
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3 votes
1 answer
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what is the difference between ISE and Vivado? [closed]

I am xilinx ISE and virtex 5 engineer. I found Vivado something when I ran across the internet. What is the difference between ISE and Vivado? Should I have to move to Vivado from ISE?
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  • 59
3 votes
2 answers
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How to connect Spartan-6 with ISE 14.2 on Ubuntu

I bought my first FPGA and I'm trying to implement a simple VHDL program on it, but I don't know how to connect it's Atlys board to ISE 14.2. I'm using Ubuntu 64-bit.
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  • 649
3 votes
1 answer
2k views

Setting single unused pin in Xilinx ISE

I have a Xilinx CPLD design that I'm not using all of the pins in, however, I have reserved some for future use and bonded them out to a microcontroller. I am defining my pinout in a constraint (UCF) ...
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  • 3,417
3 votes
1 answer
123 views

Duplication of working PWM signal leads to unexpected behaviour

I am trying to control 13 different servos with my Spartan3 FPGA. For that, I need 13 independent PWM signals generated by my FPGA. The PWM module that I am using works perfectly fine when only one ...
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  • 41
2 votes
3 answers
914 views

How to decrease used LUTs in FPGA Design?

I am working with Spartan 2 XC2S50 FPGA Chip on Xilinx board There is a problem on my design that increases number of used LUTs and this is the Utility Library : ...
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2 votes
2 answers
1k views

Why my FPGA programs does not work?

I am very new to FPGA and sorry for this elementary question. I just made a very simple XOR code like this with Webpack ISE to download to XC2S100 ( just for test!) but it does not work. EDITION1: ...
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2 votes
2 answers
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How to assign physical pins of FPGA to Xilinx ISE Verilog modules?

Recently I started learning FPGA programming. I have the " Verilog QuickStart book" and downloaded Xilinx ISE Webpack v14 and watched a number of YouTube videos. At this moment I can build my circuits ...
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2 votes
1 answer
1k views

Which is the best way to version control Xilinx PlanAhead projects?

Actually I'm migrating some mature projects from Xilinx ISE to Xilinx PlanAhead. I need to take advantage of TCL scripting and partitioning of PlanAhead. This ISE projects are under version control ...
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2 votes
1 answer
6k views

Why is my simple counter VHDL not working? Where did my signals go?

I'm a complete beginner with VHDL and an almost beginner with digital logic and I'm having a problem working through a book I'm reading. In particular, an exercise asks to build a counter with an ...
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2 votes
2 answers
1k views

BCD to 7 Segment Decoder Schematic: Need help fitting in page

I am working on the schematic for a BCD to 7 segment decoder right now. I understand the logic, but it is the design of the schematic that I need help with. Here is my schematic so far: As you can ...
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  • 125
2 votes
1 answer
217 views

FPGA - Routing Diagram - what are the physical parts

In Xilinx ISE I've generated a very simple piece of hardware and when looking at the routed design I'm unsure what some of the parts are and require some clarification on what some of these parts are. ...
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2 votes
1 answer
59 views

ISE Design Suite simulation problem

I am new in Verilog language. I am trying to understand the basics. There is this question where the input is a 6-bit number named IN and the output is a 1-bit ...
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  • 173
2 votes
1 answer
426 views

New design with XC9500XL CPLDs, is it already obsolete?

I am in the middle of a new design for which a relatively small amount of logic is needed. This is a change to a previous version in which discrete 3.3V logic parts were used. We decided to go a CPLD ...
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  • 8,146
2 votes
1 answer
2k views

Driving a differential signal from FPGA

Disclaimer: I am not sure if this is the right place to ask this. I am trying to create an sdram controller for the numato mimas v2 fpga. The board contains an LPDDR module (either the Micron ...
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  • 195
2 votes
1 answer
508 views

How to assign the same value to a bus in Xilinx ISE (Schematic)?

How to set all the bits for example in bus(7:0) to the value in net0?
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  • 147
2 votes
1 answer
383 views

VHDL latch for Xilinx Spartan 3E

I am coding a display control for the Spartan 3E. It has 8 LEDs. When the ALU's state signal (from other block) is "00" the MSBs and LSBs are time-multiplexed for one second each byte. When state is ...
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2 votes
2 answers
442 views

Prevent ISE from bitswapping the configuration file

For some reason unknown to me, ISE provides a bitswapped configuration image: each byte has its bits swapped. Is there a way to disable this bitswapping? (Having to do it again in C code slows down ...
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  • 10.6k
2 votes
1 answer
408 views

What is the purpose of a "BUF" in Xilinx ISE schematic?

I'm working on a schematic for a Xilinx CPLD using ISE. The schematic has a triangle symbol labeled "BUF" before every output, and also between some other nets. I can't really tell why some ...
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2 votes
1 answer
3k views

Using Xilinx ISE tools, "does not have a port named" error

I'm a verilog Beginner. I created a design using straight-up Verilog then tested it using the ISE design tools. Works great. I would like to synthesize this to see the resources that will be ...
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2 votes
2 answers
1k views

ISE: Force the compiler to accept long loops

At the moment ISE limits generate loops to 64. When I go above, it produces the error: Loop count limit exceeded. Condition is never false. I found that the <...
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  • 10.6k
2 votes
1 answer
861 views

Determine version of Xilinx ISE programatically

I'm using the Xilinx toolchain and I'd like to automate (with TCL scripts) some things. While the ISE Suite can be extensively automated via TCL and their TCL shell (...
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  • 3,417
2 votes
2 answers
9k views

the output register remains x in the waveform even when clock changes?

I am using ISE to write my first verilog code . i wrote a counter : ...
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  • 203
2 votes
1 answer
131 views

Using the UCF constraints to assign one of two output ports

I've got a CPLD design which has one spare (Debug) pin. I'm trying to find out if it's possible to use the UCF file to select which output port (NET) that pin becomes. The problem is however, that I'...
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2 votes
1 answer
5k views

Convert C to FPGA

I'm new to programming for FPGAs so I was recommended to use some available C/C++ to VHDL translator. Problem is, there are tons of information out there and almost all good programs need an ...
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2 votes
1 answer
2k views

Use Xilinx Primitive elements in Verilog inside ISE

I generated Verilog Post-Route simulation model of my original Verilog module, using Xilinx ISE. It will generate a Verilog module using LUT and fpga level primitives such as IBUF,X_LUT4, ... When ...
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  • 384
2 votes
1 answer
681 views

How does Xilinx ISE determine compilation order?

I’m working on a VHDL project which is a small SDRAM test. I have these entities: top sdramwrapper sdram <– generated IP core sdrampkg <– contains a package containing constants used several ...
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2 votes
0 answers
352 views

Exclude certain module from optimization in Xilinx ISE 14.4

I'm synthesizing a quite large design in Xilinx ISE 14.4 and would like to exclude certain modules from optimization. Is that possible? The design I'm synthesizing is the LEON3 microprocessor. I have ...
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2 votes
0 answers
188 views

Macrocell and Function Block optimization ISE XILINX

I get the following result when I compile my code in ISE. It says the CPLD is full, but I can't help but notice that the optimizer should be able to move elements from different function blocks to ...
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2 votes
1 answer
1k views

Xilinx ISE Prevent Trimming For CPU

I am creating a custom CPU and would like it to be programmable on the fly instead of hard coded in VHDL. The issue I am having is that without initial code for the CPU to run, ISE will trim large ...
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  • 23
1 vote
2 answers
1k views

How to get a default UCF file of Xilinx Virtex-5 XC5VLX110?

How to get a default UCF file of the Xilinx Virtex-5 XC5VLX110? It doesn't seem to be anyhere. If I have to make it by myself, would you let me know how to ...
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  • 417
1 vote
1 answer
98 views

Combinatorial loop of SR latch

I implemented an SR latch in Verilog. module sr_latch( output Q, output P, input S, input R ); nor(P, S, Q); nor(Q, R, P); endmodule However, ...
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  • 113
1 vote
1 answer
120 views

Hardware design

Is there a way to actually build components on something like Xilinx ISE? i.e. MUX's, NAND's, AND gates. From what I've learned so far, one can only use VHDL to describe hardware and the compilation ...
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1 vote
4 answers
980 views

Why Xilinx ISE doesn't infer Block Ram for this Array?

I have an Entity that has an array type as below : ...
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1 vote
1 answer
1k views

Analyzing Xilinx Design Summary?

What are: "Number using O6 output only: 1,511", "Number using O5 output only: 37", "Number of Slice registers: 1,866", "Number of 36k BlockRAM used : 2" How ...
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  • 319
1 vote
3 answers
2k views

How to simulate an 8x4 memory using VHDL?

Why does this code: ...
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  • 647
1 vote
1 answer
588 views

Why does Xilinx Translate for Virtex-6 not know IOSTANDARD LVDS?

I'm using several Xilinx FPGAs and boards from Spartan3E up to KC705/VC707 and I'm very familiar with UCF files, but there is one question that bothers me... Why does translate for Virtex-6 not know ...
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  • 3,797
1 vote
1 answer
360 views

why fork- join is not supported in ISE Webpack?

I am using the newest version of Xilinx ISE Webpack(v14.7). every time I try to use fork-join statement ( in Verilog ), I receive this error: ERROR:Xst:850 : Unsupported Fork Statement. Is this ...
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  • 1,531
1 vote
1 answer
554 views

Using VHDL with the Mojo V3 FPGA

I was just wondering if there's any way for me to write VHDL code, that I can then upload to the Mojo V3 board? The Mojo V3 IDE is Verilog/Lucid friendly, both languages that I'm unfamiliar with. ...
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1 vote
1 answer
117 views

Can I estimate what CPLD I need?

I'm planning to design a driver for VGA connectors, and for testing purposes I have an evaluation board of one CPLD. Concretely, the board is the Digilent's CoolRunner-II with the Xilinx's XC2C256 ...
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  • 181
1 vote
2 answers
70 views

shift whole design in Xillinx FPGA

How can I shift whole my design using ISE(FPGAditor,plan ahead,..) to new placement? I want to no change in routing but change only in placement. Thanks.
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1 vote
2 answers
191 views

How to best synthesize a systolic circuit on FPGA?

I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions. I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the ...
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  • 367
1 vote
2 answers
4k views

Synthesis timing summary in Xilinx tool (ISE)

I'm getting the following timing summary from the synthesis: ...
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1 vote
1 answer
88 views

Use SDC format for timing constraints on Xilinx CPLDs

Due to the chip shortage, I'm trying to perform timing analysis of an existing CPLD design for a number of alternative chips from different manufacturers. I have existing hardware description source ...
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  • 2,433
1 vote
1 answer
1k views

Signal is connected to following multiple drivers

This is the top module combining the Circular Shift Register, Multiplexer and Adder. ...
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1 vote
1 answer
286 views

HDMI (TMDS) output with Digilent Atlys - examples do not compile with ISE 14.7

I'm working on XAPP495 on Digilent Atlys board with ISE 14.7 I want to run and test "vct_demo" coming with the XAP 495. I tried to compile it (with ISE 14.7) and failed because of the following ...
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